CN1508868A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN1508868A
CN1508868A CNA2003101206605A CN200310120660A CN1508868A CN 1508868 A CN1508868 A CN 1508868A CN A2003101206605 A CNA2003101206605 A CN A2003101206605A CN 200310120660 A CN200310120660 A CN 200310120660A CN 1508868 A CN1508868 A CN 1508868A
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dielectric constant
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梶成彦
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Toshiba Corp
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Semiconductor Leading Edge Technologies Inc
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Abstract

在硅衬底1上形成多孔性MSQ(2)，在其上形成SiC掩模3。通过以该SiC掩模3为掩模的等离子体刻蚀，在多孔性MSQ(2)上形成布线沟槽5。在包含布线沟槽5的侧面的硅衬底1的整个面上形成氟化聚(苯二甲基)膜6，除去在布线沟槽5的侧面以外形成的不需要的氟化聚(苯二甲基)膜6。在布线沟槽5内形成阻挡层金属膜和籽晶层，淀积金属。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体集成电路中的布线结构，特别是涉及使用了由多孔性的低介电常数膜构成的层间绝缘膜和铜布线的多层布线结构。
背景技术
伴随着半导体集成电路的微细化，金属布线的信号延迟正成为日益严重的问题。
为了解决这一问题，用铜(Cu)作为布线材料以降低布线电阻，用低介电常数膜作为层间绝缘膜以降低静电电容正变得不可或缺。
特别是，在下一代的半导体集成电路中，为了进一步降低层间电容，正在研究使用在绝缘膜中具有众多空洞的所谓多孔性低介电常数膜(以下称为“多孔性低k膜”)。
而且，为了防止金属向多孔性低k膜的扩散，提出了在布线用沟槽的表面上形成CVD氧化膜的方法(例如，请参照专利文献)。
专利文献1
特开平9-298241号公报(第5页，图1)
在下一代的65nm节点的半导体集成电路中，布线间的距离更加缩短。与此同时，对于布线间的多孔性低k膜的宽度，在布线用沟槽的侧面形成的上述CVD氧化膜的膜厚相对地增大。即，在布线用沟槽侧面形成的物质的介电常数对线间电容的影响增大。
然而，由于上述CVD氧化膜的介电常数k为4.1～4.3左右，所以存在作为层间绝缘膜的多孔性低k膜的有效介电常数keff增高，得不到所希望的有效介电常数的问题。
发明内容
本发明是为了解决上述现有的课题而进行的，其目的在于将层间绝缘膜的有效介电常数的增加抑制到最小限度，同时形成使用了多孔性的低介电常数膜和铜布线的多层布线。
本发明的半导体器件的特征在于，包括：
在衬底上形成的多孔性的低介电常数膜；
在上述低介电常数膜内形成的布线沟槽；
仅覆盖上述布线沟槽的侧面、介电常数为3以下的绝缘膜；以及
在上述布线沟槽内形成的导电体膜。
附图说明
图1是用于说明本发明的实施例的半导体器件的剖面图。
图2是用于说明本实施例的半导体器件的制造方法的剖面图。
具体实施方式
以下，参照附图说明本发明的实施例。在图中，对相同或相当的部分标以同一符号，其说明予以简化或省略。
首先，说明本发明的实施例的半导体器件。
图1是用于说明本发明的实施例的半导体器件的图。
如图1所示，在硅衬底等的衬底1上，形成作为具有空洞21的多孔性低介电常数膜(以下也称为“多孔性低k膜”)2的多孔性MSQ。该多孔性低K膜2除了多孔性MSQ外，例如还有多孔性HSQ、含有甲基和羟基双方的混合膜、以碳为主成分的多孔性有机膜。另外，在多孔性MSQ(2)上形成作为硬掩模3的SiC掩模，在多孔性MSQ(2)内形成布线掩埋用的作为开口部的布线沟槽5。以下，对开口部为布线沟槽(trench)的情况进行说明，但本发明也能适用于开口部为通路孔(viahole)的情况。在该布线沟槽5的侧面形成介电常数k在3以下，在2.5以下则更好的绝缘膜6。该绝缘膜6不是多孔性膜，而是例如氟化聚(苯二甲基)膜等的氟化聚(丙炔)膜或无定形氟化碳。在布线沟槽5内，作为阻挡层金属膜和籽晶层10、金属11的Cu形成为导电体膜。
下面，说明上述半导体器件的制造方法。
图2是说明本实施例的半导体器件的制造方法的图。详细地说，图2(a)是示出在多孔性MSQ上形成了SiC掩模后的状态的图，图2(b)是示出在多孔性MSQ内形成了布线沟槽后的状态的图，2(c)是示出在衬底的整个面上形成了低介电常数膜后的状态的图，2(d)是示出刻蚀掉不需要的低介电常数膜后的状态的图。
再有，在图2中，省略了关于图1所示的阻挡层金属膜和籽晶层10以及金属(Cu)的形成的图示。
首先，如图2(a)所示，在硅衬底1上形成具有众多空洞21的多孔性MSQ(2)。多孔性MSQ(2)的空洞21的大小例如为数埃～数百埃左右。其次，在多孔性MSQ(2)上形成SiC掩模3。
接着，如图2(b)所示，以SiC掩模3为掩模，对多孔性MSQ(2)进行等离子体刻蚀。这里，在本实施例中，作为等离子体刻蚀装置使用配备了将硅衬底1放置在其上表面的下部电极和与之相向的上部电极的双频率激发平行平板型RIE(反应性离子刻蚀)装置(图示予以省略)。
在详述多孔性MSQ(2)的等离子体刻蚀时，首先在与上部电极相向的下部电极上配置硅衬底1。使用热交换器等使硅衬底1的温度保持在约25℃。其次，在反应室内作为工艺气体，分别以10/225/1400sccm的流量导入C4F8/N2/Ar，使用排气机构使反应室内的压力保持在150m乇。然后，在对上部电极施加频率为60MHz、输出功率为1000W的RF电力(高频电力)，对下部电极施加频率为13.56MHz、输出功率为1400W的RF电力时，在反应室内产生等离子体4。通过用该等离子体4对多孔性MSQ(2)进行各向异性刻蚀，在多孔性MSQ(2)内形成布线沟槽5。在刻蚀结束后，布线沟槽5的侧面借助于多孔性MSQ(2)的空洞21形成为凹凸形状。
接着，如图2(c)所示，在包含布线沟槽5的侧面的硅衬底1的整个面上形成介电常数为3以下的绝缘膜(以下称为“低介电常数膜”)6。以下，作为低介电常数膜6，说明形成介电常数为2.2左右没有空洞的氟化聚(苯二甲基)膜[CF2-C6H4-CF2]n的情形。
首先，在盛原料的容器中，使结合了氟的苯二甲基化合物加热气化，将由此得到的原料气体以5sccm的流量供给加热反应机构。然后，在该加热反应机构内通过在600℃的温度下使原料气体活化，形成前体。其次，将该前体置于保持在20m乇左右的成膜室内的静电卡盘上，导入保持在负30℃的硅衬底1的表面上。由此，在硅衬底1表面上引起前体的聚合反应，在硅衬底1上以10nm左右的膜厚形成氟化聚(苯二甲基)膜6。其后，将形成了该氟化聚(苯二甲基)膜6的硅衬底1移入立式炉内，通过在大气压的N2气氛下，在400℃下进行60分钟的热处理，使该氟化聚(苯二甲基)膜6稳定。
接着，如图2(d)所示，使用上述刻蚀装置除去在布线沟槽5的侧面以外形成的不需要的氟化聚(苯二甲基)膜6。
在详述该氟化聚(苯二甲基)膜6的等离子体刻蚀时，首先用热交换器等使配置在下部电极上的硅衬底1保持在约25℃。其次，在反应室内分别以150/250sccm的流量导入N2/H2作为工艺气体，应用排气机构使反应室内的压力保持在300m乇。然后，在对上部电极施加频率为60MHz、输出功率为1500W的RF电力(高频电力)，对下部电极施加频率为13.56MHz、输出功率为600W的RF电力时，在反应室内产生等离子体7。通过用该等离子体7对氟化聚(苯二甲基)膜6进行各向异性刻蚀，仅在布线沟槽5的侧面保留低介电常数膜6，去除掉除此以外的不需要的氟化聚(苯二甲基)膜6。
再有，进行使用了Ar气体的溅射刻蚀以替代使用了上述N2/H2气体的等离子体刻蚀，可除去不需要的氟化聚(苯二甲基)膜6。
采取以上做法，形成了仅覆盖在多孔性MSQ(2)内形成的布线沟槽5的侧面的氟化聚(苯二甲基)膜6。
最后，虽然未图示，但在布线沟槽5内形成导电体膜。详细地说，在依次形成阻挡层金属膜和籽晶层(10)后，淀积Cu等金属(11)，用CMP除去不需要的金属，使之变得平坦。由此，得到图1所示的半导体器件。
如以上说明的那样，在本实施例中，在多孔性MSQ(2)内形成了布线沟槽5后，在该布线沟槽5的侧面形成氟化聚(苯二甲基)膜6，其后，在布线沟槽5内形成导电体膜。按照本实施例，在形成导电体膜时，用氟化聚(苯二甲基)膜6覆盖布线沟槽5侧面的空洞21，使凹凸形状趋于平缓。从而，在布线沟槽5内可形成覆盖性良好且紧密接触性高的导电体膜。
另外，在本实施例中，通过用介电常数为3以下的低介电常数膜6覆盖布线沟槽5侧面，使层间绝缘膜2的有效介电常数的增加受到抑制。从而，可将有效介电常数的增加抑制到最小，同时用铜作为布线材料，可形成使用了多孔性低k膜作为层间绝缘膜的多层布线(Cu/低k多层布线)。因而，可使半导体器件的微细化成为可能，使半导体器件的可靠性得到提高。
再有，在本实施例中，虽然取氟化聚(苯二甲基)膜6的膜厚为10nm左右，但不限于此，可在考虑到作为布线沟槽5的沟槽和孔径以及在除去不需要的氟化聚(苯二甲基)膜6的膜厚时(参照图2(d))的膜厚减少量等后适当地设定膜厚。
另外，在本实施例中，用有机系的低介电常数膜6覆盖布线沟槽5侧面。该有机系的低介电常数膜6与无机系的低介电常数膜不同，在膜中不含水分(H2O)。因此，即使在阻挡层金属10的覆盖性差、Cu漏到低介电常数膜6内的情况下，也能抑制Cu向低介电常数膜6内的扩散，提高工艺容限。
另外，出于提高导电体膜的紧密接触性的目的，希望采用完全没有空洞的膜作为低介电常数膜6。但是，如果可防止导电材料在多孔性MSQ(2)内扩散，则可将具有空洞且其空隙率低的膜用作低介电常数膜6。这时，与没有空洞的膜相比，提高了防止有效介电常数的增加的效果。
另外，当作为布线沟槽5的沟槽和孔分别在不同的工序中形成时，在形成了该沟槽和孔后在它们的侧面可同时形成氟化聚(苯二甲基)膜6，每当形成沟槽或孔时也可分别形成氟化聚(苯二甲基)膜6。从生产率的观点看，前者是所希望的。
发明效果
按照本发明，可将层间绝缘膜的有效介电常数的增加抑制到最小限度，同时形成使用了多孔性的低介电常数膜和铜布线的多层布线。

Claims (6)

1.一种半导体器件，其特征在于，包括：
在衬底上形成的多孔性的低介电常数膜；
在上述低介电常数膜内形成的开口部；
仅覆盖上述开口部的侧面、介电常数为3以下的绝缘膜；以及
在上述开口部内形成的导电体膜。
2.如权利要求1所述的半导体器件，其特征在于：
上述绝缘膜是氟化聚(丙炔)膜或无定形氟化碳。
3.如权利要求1或2所述的半导体器件，其特征在于：
上述低介电常数膜是多孔性MSQ、多孔性HSQ、含有甲基和羟基双方的混合膜、以碳为主成分的多孔性有机膜中的某一种。
4.一种半导体器件的制造方法，其特征在于，包含：
在衬底上形成多孔性的低介电常数膜的工序；
在上述低介电常数膜内形成开口部的工序；
在包含上述开口部的侧面的上述衬底的整个面上，形成介电常数为3以下的绝缘膜的工序；
除去在上述开口部的侧面以外形成的不需要的上述绝缘膜的工序；以及
在上述开口部内形成导电体膜的工序。
5.如权利要求4所述的半导体器件的制造方法，其特征在于：
上述绝缘膜是氟化聚(丙炔)膜或无定形氟化碳。
6.如权利要求4或5所述的半导体器件的制造方法，其特征在于：
上述低介电常数膜是多孔性MSQ、多孔性HSQ、含有甲基和羟基双方的混合膜、以碳为主成分的多孔性有机膜中的某一种。
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