CN1841673A - 在半导体元件中蚀刻介电材料的方法 - Google Patents
在半导体元件中蚀刻介电材料的方法 Download PDFInfo
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Abstract
本发明提供一种在半导体元件中蚀刻介电材料的方法。提供一导电区域之后,形成一介电层于导电区域之上;再形成一抗反射层于介电层上;执行去除湿气步骤以去除该抗反射层以及该介电层与该抗反射层间的界面区域的湿气;转换一光罩图案至该抗反射层与该介电层中。本发明提供的在半导体元件中蚀刻介电材料的方法,通过在覆盖光刻胶前执行去除湿气步骤,可以一致且完全地蚀刻介层洞。
Description
技术领域
本发明有关于一种集成电路设计,特别有关于放宽在各种低介电系数材料制程间所需的等候时间的方法。
背景技术
集成电路的生产是通过金属化及化学机械研磨法平坦化的介电材料。一般而言,每层金属层之上沉积有一蚀刻终止层,并提供两个目的。第一个目的是作为一特别金属层扩散至下一介电层的屏障,无论该介电层是典型的氧化物或特殊的低介电系数材料层;第二个目的是提供作为介层洞蚀刻的蚀刻终止层,介层洞蚀刻可能被设计向下蚀刻至特定金属层,而没有该蚀刻终止层,后续的介层洞蚀刻可能在全部属于深的介层洞蚀刻完成之前攻击此特定的金属层。
为使电路速度最大化,低介电系数材料使用于金属层之间。较低的介电系数表示两金属层间有较低的电容。较低的电容允许一集成电路内的元件有较快的信号传递,因而提升该集成电路全面的性能。然而,目前市场上可获得的低介电系数材料具有一些副作用。例如,若一光刻胶直接覆盖于一低介电系数材料之上,有可能发生太多用于微影曝光的光线被该光刻胶与该低介电系数材料间的界面反射。这样的反射将扭曲微影结果,而严重偏离光刻胶所欲提供的图像。为解决此一问题,目前是在覆盖该光刻胶之前沉积一抗反射层于该低介电系数材料层上,如碳氧化合物。虽然该抗反射层改善了光学性能,但它还有其他副作用,例如该抗反射层会吸收大气中的湿气,而湿气通常出现在先前的半导体制程中,其被导入半导体制造设备的大气中以防止静电。在一般生产的间隔时间内,该抗反射层会吸收湿气,通常存在抗反射层与低介电系数材料层间的界面。当界面潮湿,将变得具导电性,而使电荷容易流失,且阻碍电荷建立。然而,在干式蚀刻过程中是非常需要建立电荷来吸引解离气体,而减少的电荷数量会严重减慢蚀刻的过程。
此外,电荷数量降低会造成晶圆内蚀刻的不均匀。例如,独立介层窗与群集介层窗的电荷流失量是不同的。此不同造成蚀刻电压的差异,进而导致独立介层窗与群集介层窗的蚀刻速率不同。当蚀刻速率不同,在每个集成电路晶圆上的介层窗蚀刻可能是一致或不一致。如此的一致或不一致是集成电路失败的典型原因。因此,最重要的是通过减少电荷流失量以增加抗反射层与低介电系数材料层间的界面的蚀刻速率及均匀性。
因此,目前集成电路设计所需要的是一种减低抗反射层吸收湿气的方法与在低介电系数制程中所需放宽等候时间以限制水气吸收的方法。
发明内容
鉴于上述,下列提供一种在半导体元件中蚀刻介电材料的方法:在提供导电区域后,形成一介电层于该导电区域之上,并于该介电层上形成一抗反射层;执行去除湿气步骤,以去除抗反射层及抗反射层与介电层间的界面的湿气;转换光罩图案至抗反射层与介电层中。
湿气去除步骤可能包括:真空烘烤界面,在设定好的温度及时间下;紫外光固化;热板固化;或以各种的等离子作一或多次的等离子处理。等离子处理可能发生于一反应室中,该反应室用于在光刻胶制程之前沉积抗反射层或如低介电系数材料的介电层。
本发明所述的在半导体元件中蚀刻介电材料的方法,该介电层包括低介电系数的介电材料。
本发明所述的在半导体元件中蚀刻介电材料的方法,该低介电系数材料可为掺杂碳的氧化硅、介电系数低于3.4的有机低介电系数材料、或介电系数低于3.4的多孔低介电系数材料。
本发明所述的在半导体元件中蚀刻介电材料的方法,该抗反射层可为无氮介电材料、硅的氮氧化合物、或是具有介电性质的含碳材料。
本发明所述的在半导体元件中蚀刻介电材料的方法,该去除湿气步骤是一热处理步骤,其温度范围介于200至400℃之间,时间范围介于2至60分钟之间。
本发明所述的在半导体元件中蚀刻介电材料的方法,该去除湿气步骤是一快速热处理操作,具有温度范围400至700℃之间及时间范围1至60秒钟之间。
本发明还提供一种在半导体元件中蚀刻介电材料的方法,包括:提供一导电区域;形成一低介电系数材料层于该导电区域之上,并形成另一介电层于该低介电系数材料层上;执行一去除湿气步骤以去除上述另一介电层及该低介电系数材料层与该另一介电层间的界面的湿气;及转换一光罩的图案至该低介电系数材料层及该另一介电层中。
本发明所述的在半导体元件中蚀刻介电材料的方法,该导电区域包括铜、铜合金、金属硅化物或多晶硅,并且该转换一光罩的图案至该抗反射层与该介电层的步骤包括形成一开孔以暴露该导电区域。
本发明所述的在半导体元件中蚀刻介电材料的方法,该去除湿气步骤包括真空烘烤、紫外光固化或热板固化。
本发明所述的在半导体元件中蚀刻介电材料的方法,该等离子处理操作包括惰性气体,其至少包括氩气或氦气。
本发明提供的在半导体元件中蚀刻介电材料的方法,通过在覆盖光刻胶前执行去除湿气步骤,可以一致且完全地蚀刻介层洞。
附图说明
图1是示出集成电路制程中具有一低介电系数材料层的剖面图;
图2是示出集成电路制程中具有各种成功的介层洞蚀刻;
图3是示出本发明实施例的制程流程图。
具体实施方式
为使本发明的操作方法和其他目的、优点能被更加了解,下列是具体叙述并配合所附的图示。
基于说明所需,以下将对关于放宽在低介电系数材料制程中的等候时间以及改善低介电系数材料的蚀刻速率及蚀刻均匀性的方法提供详细的叙述。而其他类型的介电材料可能也可以应用类似的制程制作半导体元件。
请参照图1,其是集成电路制程中具有一低介电系数材料层的剖面100。此剖面100具有在第一层金属完成的生产阶段的半导体基材102,其包括填有金属的介层洞104以及填有金属的沟渠106。该第一层金属与所围绕的介电材料的组成可视为一导电区域。其中该金属以铜、铜合金或其他金属为佳。之后,沉积一蚀刻终止层于其上,该蚀刻终止层以碳化硅为佳。该蚀刻终止层为防止金属扩散至介电层,并且作为随后的介层洞蚀刻步骤的蚀刻终止层。
一低介电系数材料层110沉积于蚀刻终止层108上,其具有一低介电常数K。该低介电系数材料层可为有机、掺杂碳的氧化硅或为多孔材料,其介电常数小于3.4。低介电系数材料层有助于降低金属层间的电容,然而,该低介电系数材料层110具有反射性,因此很难在微影时转换图像。若将光刻胶直接沉积于低介电系数材料层110上,在由光刻胶转换图案过程中,光线会反射回光刻胶,因而降低转换图案的品质。因此,一抗反射层112沉积于低介电系数材料层110之上,其中以硅的碳氧化合物为佳。接着将光刻胶114沉积于抗反射层112上,转换图案可得到高品质的图案。
然而,使用低介电系数材料层110及抗反射层112在制程中导入新的困难。抗反射层112会吸收湿气,在光刻胶114沉积前湿气将会渗入其中。一半孤立(semi-isolated)的介层窗图案116,其在光刻胶作用下以干式蚀刻将图案蚀刻至抗反射层112及低介电系数材料层110。然而,干式蚀刻在集成电路上方的低压等离子及在集成电路表面上待蚀刻层之间需要一强大的电压降。而一界面区域118,其位于抗反射层112及低介电系数材料层110之间,可能会聚集水气而变为具导电性,若湿气不以本发明提供的方法去除,此导电界面118将遗失所建立的电荷,而难以维持干式蚀刻所需的电压。
一群集的介层窗从干式蚀刻的等离子收集电荷的速度比从具导电性的界面区域118流失电荷的速度快。在此案例,一孤立或半孤立的介层窗图案116,电荷流失超过电荷建立,造成在等离子及欲蚀刻层之间较低的电压降,而降低蚀刻速率。因此,若不以本发明提供的方法去除湿气,在抗反射层112将产生一蚀刻不完全的介层洞蚀刻。在此情况下,电荷传导不能到达较下面的金属,而造成集成电路的失败。
在沉积抗反射层与光刻胶制程之间需要较短的时间间隔以处理湿气渗入的效应。虽然较短的时间间隔可使较少的湿气由抗反射层渗入至界面区域,但要在较短的时间间隔提供足以控制制程的可靠度的能力是非常有限的。
在本发明,可通过在形成抗反射层112后的一或多道制程以放宽在沉积抗反射层及光刻胶制程间的时间间隔。由此,去除聚集在抗反射层112以及抗反射层112与低介电系数材料层110间的界面区域118的湿气。例如,以热处理,如:真空烘烤晶圆300℃持续30分钟去除湿气,使造成界面区域具导电性的湿气去除,使集成电路晶圆的状态接近刚沉积抗反射层时的状态。在湿气去除步骤、光刻胶制程及干式蚀刻步骤中,可能希望执行越快越好,但在沉积抗反射层与光刻胶制程之间的等候时间可被放宽,而不影响蚀刻品质。
请参照图2,其是本发明实施例的集成电路制程中具有各种成功的介层洞蚀刻的剖面200。此剖面200具有在第一层金属完成的生产阶段的半导体基材102,其包括填有金属的介层洞104以及填有金属的沟渠106。蚀刻终止层108、低介电系数材料层110、抗反射层112以及界面区域118皆维持相同,除了被干式蚀刻作用的部分外。光刻胶114已被去除,半孤立介层窗116图案如同图1。不同之处是在抗反射层112与低介电系数材料层110间的界面区域118已经以一些步骤处理,例如:一真空烘烤步骤,其降低界面区域118的导电性,以维持干式蚀刻所需电压。介层洞蚀刻将持续直到所有介层洞被蚀刻至蚀刻终止层108为止。蚀刻终止层108将被后续的蚀刻步骤去除。
由于填有金属的沟渠106内的金属材料被完全暴露以与用来填入介层洞的下一层金属建立电荷的传导性,因此电荷传导性可被完整地建立。
请参照图3,其是本发明实施例的制程流程图300,其由至少一传统的化学机械研磨法步骤开始。首先,在制程304中,沉积一低介电系数材料层110。其次,在制程306中,沉积一抗反射层112,如氧化硅。某种程度上,只使用传统制程。接续在步骤308中,包括一去除湿气步骤。在一实施例中,湿气去除步骤可能以真空烘烤300℃持续30分钟,可去除出现于抗反射层或抗反射层与低介电系数材料层间的界面的湿气。可能可运用不同的温度及烘烤时间或相关的热处理方式确定除去足够的湿气以防止蚀刻的缓慢或不均匀。例如,可执行一热处理于烤箱中,温度范围在200至400℃,或执行紫外光固化或热板固化,每一种方法的时间范围可能为2至60分钟。热处理亦可通过快速热处理步骤,其执行于烤箱温度范围400至700℃,时间范围1至60秒。一已决定的压力可运用于此步骤,抗反射层可为无氮、氮氧化硅或含碳的材料。
在另一实施例中,制程308的去除湿气步骤可为一等离子处理,其可去除聚集于界面区域及抗反射层的湿气。例如,该等离子处理步骤的气体可为如氩或氦的惰性气体;等离子处理步骤的气体还可为含氧的等离子,如:臭氧;其他例子中,等离子处理步骤的气体可为氢气或氨气等离子。
另可在光刻胶制程之前执行等离子处理步骤于一反应室中,该等离子处理步骤发生的反应室另用于形成抗反射层或低介电系数材料层。例如:提供一反应室,于其中先形成一低介电系数材料层,之后于该反应室形成抗反射层;最后,执行等离子处理步骤于该反应室以确定湿气被去除。任何前述的等离子处理范例可适用于相同反应室的等离子处理。
经过一去除湿气步骤后,在制程310中,覆盖并图案化一光刻胶以进行介层洞蚀刻。在制程310后,执行传统的制程步骤而完成生产制程。在此实施例,介层洞被蚀刻一致且完全,是由于在制程310中的光刻胶覆盖前执行制程308中的真空烘烤所致。
虽然本发明已通过较佳实施例说明如上,但该较佳实施例并非用以限定本发明。本领域的技术人员,在不脱离本发明的精神和范围内,应有能力对该较佳实施例做出各种更改和补充,因此本发明的保护范围以权利要求书的范围为准。
附图中符号的简单说明如下:
110:集成电路制程的剖面
102:半导体基材
104:介层洞
106:金属填充沟渠
108:蚀刻终止层
110:低介电系数材料层
118:低介电系数材料层与抗反射层间的界面区域
112:抗反射层
114:光刻胶
116:介层洞图案
200:集成电路完成介层洞蚀刻的剖面图
Claims (14)
1.一种在半导体元件中蚀刻介电材料的方法,包括:
提供一导电区域;
形成一介电层于该导电区域之上,并于该介电层上形成一抗反射层;
执行一去除湿气步骤以去除该抗反射层及该抗反射层与介电层间的界面的湿气;及
转换一光罩的图案至该抗反射层及该介电层中。
2.根据权利要求1所述的在半导体元件中蚀刻介电材料的方法,其特征在于,该介电层包括低介电系数的介电材料。
3.根据权利要求2所述的在半导体元件中蚀刻介电材料的方法,其特征在于,该低介电系数材料可为掺杂碳的氧化硅、介电系数低于3.4的有机低介电系数材料、或介电系数低于3.4的多孔低介电系数材料。
4.根据权利要求1所述的在半导体元件中蚀刻介电材料的方法,其特征在于,该抗反射层可为无氮介电材料、硅的氮氧化合物、或是具有介电性质的含碳材料。
5.根据权利要求1所述的在半导体元件中蚀刻介电材料的方法,其特征在于,该去除湿气步骤是一热处理步骤,其温度范围介于200至400℃之间,时间范围介于2至60分钟之间。
6.根据权利要求1所述的在半导体元件中蚀刻介电材料的方法,其特征在于,该去除湿气步骤是一快速热处理操作,具有温度范围400至700℃之间及时间范围1至60秒钟之间。
7.根据权利要求1所述的在半导体元件中蚀刻介电材料的方法,其特征在于,该去除湿气步骤是一等离子处理操作。
8.根据权利要求1所述的在半导体元件中蚀刻介电材料的方法,其特征在于,该去除湿气步骤包括热板固化或紫外光固化。
9.根据权利要求1所述的在半导体元件中蚀刻介电材料的方法,其特征在于,该去除湿气步骤是一等离子处理操作,其于一反应室中进行,且该反应室另用于该介电层或该抗反射层的形成。
10.根据权利要求1所述的在半导体元件中蚀刻介电材料的方法,其特征在于,该去除湿气步骤是一真空烘烤。
11.一种在半导体元件中蚀刻介电材料的方法,包括:
提供一导电区域;
形成一低介电系数材料层于该导电区域之上,并形成另一介电层于该低介电系数材料层上;
执行一去除湿气步骤以去除上述另一介电层及该低介电系数材料层与该另一介电层间的界面的湿气;及
转换一光罩的图案至该低介电系数材料层及该另一介电层中。
12.根据权利要求11所述的在半导体元件中蚀刻介电材料的方法,其特征在于,该导电区域包括铜、铜合金、金属硅化物或多晶硅,并且该转换一光罩的图案至该抗反射层与该介电层的步骤包括形成一开孔以暴露该导电区域。
13.根据权利要求11所述的在半导体元件中蚀刻介电材料的方法,其特征在于,该去除湿气步骤包括真空烘烤、紫外光固化或热板固化。
14.根据权利要求11所述的在半导体元件中蚀刻介电材料的方法,其特征在于,该等离子处理操作包括惰性气体,其至少包括氩气或氦气。
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CN101908481A (zh) * | 2009-06-04 | 2010-12-08 | 东京毅力科创株式会社 | 用于形成含有非晶碳膜的构造的分批处理方法 |
CN101593690B (zh) * | 2008-05-30 | 2011-10-05 | 中芯国际集成电路制造(北京)有限公司 | 层叠介质层的形成方法和金属前介质层的形成方法 |
CN102376637A (zh) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | 形成通孔的方法 |
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JP2012004401A (ja) * | 2010-06-18 | 2012-01-05 | Fujitsu Semiconductor Ltd | 半導体装置の製造方法 |
US9196551B2 (en) * | 2011-08-26 | 2015-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Automatically adjusting baking process for low-k dielectric material |
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US6930056B1 (en) * | 2001-06-19 | 2005-08-16 | Lsi Logic Corporation | Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for integrated circuit structure |
JP4778660B2 (ja) * | 2001-11-27 | 2011-09-21 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
CN1203540C (zh) * | 2001-11-30 | 2005-05-25 | 联华电子股份有限公司 | 双重镶嵌结构的制造方法 |
US20040018697A1 (en) * | 2002-07-26 | 2004-01-29 | Chung Henry Wei-Ming | Method and structure of interconnection with anti-reflection coating |
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CN101593690B (zh) * | 2008-05-30 | 2011-10-05 | 中芯国际集成电路制造(北京)有限公司 | 层叠介质层的形成方法和金属前介质层的形成方法 |
CN101908481A (zh) * | 2009-06-04 | 2010-12-08 | 东京毅力科创株式会社 | 用于形成含有非晶碳膜的构造的分批处理方法 |
US8652973B2 (en) | 2009-06-04 | 2014-02-18 | Tokyo Electron Limited | Processing method for forming structure including amorphous carbon film |
CN102376637A (zh) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | 形成通孔的方法 |
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