JP6049871B2 - エッチング及びアッシング中での低誘電率材料の側壁保護 - Google Patents
エッチング及びアッシング中での低誘電率材料の側壁保護 Download PDFInfo
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- JP6049871B2 JP6049871B2 JP2015518556A JP2015518556A JP6049871B2 JP 6049871 B2 JP6049871 B2 JP 6049871B2 JP 2015518556 A JP2015518556 A JP 2015518556A JP 2015518556 A JP2015518556 A JP 2015518556A JP 6049871 B2 JP6049871 B2 JP 6049871B2
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1052—Formation of thin functional dielectric layers
- H01L2221/1057—Formation of thin functional dielectric layers in via holes or trenches
- H01L2221/1063—Sacrificial or temporary thin dielectric films in openings in a dielectric
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
- Chemical Vapour Deposition (AREA)
Description
Claims (18)
- 露出したlow−k表面を保護する方法であって:
上に生成されるlow−k絶縁層と、該low−k絶縁層の上に位置する、パターンが内部に生成されている1層以上のマスク層と、を有する基板を供する工程;
1つ以上のエッチングプロセスを用いて前記1層以上のマスク層中のパターンを前記low−k絶縁層へ転写することで前記low−k絶縁層中に構造上の特徴を形成する工程;
前記1つ以上のエッチングプロセス中及び/又は前記1つ以上のエッチングプロセス後に、前記基板をC,H,及びNを含む膜生成処理組成物へ曝露することによって前記構造上の特徴の露出表面上に絶縁保護層を形成する工程;並びに、
マスク除去プロセスを用いることによって前記1層以上のマスク層の少なくとも一部を除去する工程;
を含み、
前記膜生成処理組成物がピロール(C 4 H 4 NH)又はアニリン(C 6 H 5 NH 2 )である、
方法。 - 前記1層以上のマスク層の上面及び前記low−k絶縁層内の前記構造上の特徴の底面から前記絶縁保護層を異方的に除去しながら、前記構造上の特徴の側壁表面上の前記絶縁保護層の残りの部分を保持する工程をさらに含む、請求項1に記載の方法。
- 前記絶縁保護層を形成する工程が、プラズマを生成するプラズマ支援堆積プロセスを実行する工程を含む、請求項1に記載の方法。
- 前記プラズマ支援堆積プロセスが、上に前記基板が存在する基板ホルダへの高周波(RF)バイアスの印加を含まない、請求項3に記載の方法。
- 前記基板の温度が50℃乃至100℃の範囲である、請求項3に記載の方法。
- 圧力が200mTorr乃至1000mTorrの範囲である、請求項3に記載の方法。
- 前記プラズマ支援堆積プロセスを実行する工程が、前記プラズマ支援堆積プロセスにおける少なくとも1つのプロセスパラメータを調節することで、前記マスク除去プロセスに対する前記絶縁保護層のエッチング耐性を向上させる工程を含む、請求項3に記載の方法。
- 前記1層以上のマスク層が、ソフトマスク層、ハードマスク層、放射線感受性材料層、反射防止コーティング(ARC)層、有機平坦化層(OPL)、又は有機誘電層(ODL)からなる群から選ばれる1層以上の層を含む、請求項1に記載の方法。
- 前記ハードマスク層が金属ハードマスク層を含む、請求項8に記載の方法。
- 前記ハードマスク層がTiNを含む、請求項9に記載の方法。
- 前記構造上の特徴が、トレンチ−ビア構造である、請求項1に記載の方法。
- 前記絶縁保護層がCとNを含む、請求項1に記載の方法。
- 前記絶縁保護層がC,N,及びOを含む、請求項1に記載の方法。
- 前記1層以上のマスク層の少なくとも一部の除去に続いて、前記構造上の特徴の前記露出表面から前記絶縁保護層の残りの部分を選択的に除去する工程をさらに含む、請求項1に記載の方法。
- 前記パターンを転写する工程と前記絶縁保護層を形成する工程は、前記パターンの転写が前記low−k絶縁層中において完了するまで代わる代わる順次に複数サイクル実行される、請求項1に記載の方法。
- 前記low−k絶縁層が2.5未満の誘電率を有する、請求項1に記載の方法。
- 前記パターンを転写する工程が:
上に生成される前記low−k絶縁層と、該low−k絶縁層の上に位置する第1ハードマスク層と、該第1ハードマスク層の上に位置する第2ハードマスク層と、を有する前記基板を受け取る工程;
トレンチパターンが中に形成された第1リソグラフィマスク層を前記第2ハードマスク層上に準備する工程;
前記トレンチパターンを前記第2ハードマスク層へ転写し、かつ、前記第1ハードマスク層上で止める工程;
前記第1リソグラフィマスク層を除去する工程;
ビアパターンが中に形成された第2リソグラフィマスク層を前記第2ハードマスク層上に準備する工程;
前記ビアパターンを、前記第1ハードマスク層を貫通するように転写し、かつ、前記low−k絶縁層の少なくとも一部に入り込むように転写する工程;
前記第2リソグラフィマスク層を除去する工程;
前記第2ハードマスク層中の前記トレンチパターンを、前記第1ハードマスク層を貫通し、かつ、前記low−k絶縁層へ所定の深さにまで入り込むように転写することで、前記構造上の特徴を形成する工程であって、前記構造上の特徴はトレンチ−ビア構造である、工程;
を有する、請求項1に記載の方法。 - 前記第2ハードマスク層が金属を含む、請求項17に記載の方法。
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US13/530,546 US8859430B2 (en) | 2012-06-22 | 2012-06-22 | Sidewall protection of low-K material during etching and ashing |
US13/530,546 | 2012-06-22 | ||
PCT/US2013/046606 WO2013192323A1 (en) | 2012-06-22 | 2013-06-19 | Sidewall protection of low-k material during etching and ashing |
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US (1) | US8859430B2 (ja) |
EP (1) | EP2865000A4 (ja) |
JP (1) | JP6049871B2 (ja) |
KR (1) | KR101683405B1 (ja) |
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WO (1) | WO2013192323A1 (ja) |
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WO2013192323A1 (en) | 2013-12-27 |
KR101683405B1 (ko) | 2016-12-06 |
KR20150021584A (ko) | 2015-03-02 |
US20130344699A1 (en) | 2013-12-26 |
EP2865000A1 (en) | 2015-04-29 |
EP2865000A4 (en) | 2016-03-02 |
TWI524423B (zh) | 2016-03-01 |
JP2015521799A (ja) | 2015-07-30 |
US8859430B2 (en) | 2014-10-14 |
TW201417181A (zh) | 2014-05-01 |
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