Classifications

• • G—PHYSICS
  • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
  • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
  • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F7/26—Processing photosensitive materials; Apparatus therefor
  • G03F7/42—Stripping or agents therefor
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/311—Etching the insulating layers by chemical or physical means
  • H01L21/31127—Etching organic layers
  • H01L21/31133—Etching organic layers by chemical means
  • H01L21/31138—Etching organic layers by chemical means by dry-etching
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
  • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
  • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
  • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
  • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks

Definitions

• the present invention relates to the stripping of a photoresist. More
• the invention relates to the stripping of a photoresist from an IC structure
• organosilicate glass (OSG) material having an organosilicate glass (OSG) material.
• transistors are formed on a semiconductor wafer substrate that is typically made of
• conductive layers may be deposited on the different layers in order to build a desired IC.
• conductive layers may be deposited on the different layers in order to build a desired IC.
• conductive layers may be deposited on the different layers in order to build a desired IC.
• the dielectric materials are insulated from one another with dielectric materials.
• the dielectric materials have
• dielectric layers formed of Si0 2 may not effectively insulate
• OSG is a low-k material that can be deposited either by spin-on or CVD methods.
• the typical OSG k value ranges from 2.6 to 2.8.
• Porous OSG (pOSG) can be
• porous materials such as pOSG are
• low-k materials are incorporated into IC fabrication using a copper
• a dual damascene structure employs an etching process that
• the organic photoresist is stripped or removed using well
• organosilicate glass (OSG) dielectric For example, the use of oxygen (O 2 ) raises the
• ammonia (NH 3 ) may result in particle generation.
• the stripping process provides a
• the photoresist is an organic photoresist. The method permits the
• photoresist is one of a plurality of steps performed during a dual damascene process.
• the stripping process is applied to an illustrative
• IC structure that includes a first photoresist layer, a second
• organosilicate glass (OSG) layer a third organosilicate glass (OSG) layer.
• OSG organosilicate glass
• the method feeds nitrous oxide (N 2 0) into a reactor. A plasma is then
• the method is applied to a via first etch sequence in which a via is etched into
• the second intermediate layer is a cap layer.
• the illustrative cap layer is configured to provide protection to the OSG layer during the reworking of the photoresist layer.
• the illustrative cap layer is
• silicon and oxygen containing material such as Silicon Dioxide (SiO 2 ) or Silicon
• the illustrative via first method includes etching a via into the
• ARC bottom antireflective coating
• BARC bottom antireflective coating
• a N 2 O gas mixture is then applied to etch back the ARC or BARC and
• the organic plug occupies a portion of the third OSG
• the method then proceeds to etch a trench into the second cap layer and the
• a N O gas mixture is then fed into the reactor and generates a
• the method may also be applied to a trench first etch sequence in which the
• second intermediate layer is a hardmask layer.
• the hardmask layer may be composed of such materials as Silicon Nitride
• Si 3 N Tantalum Nitride (TaN), Titanium Nitride (TiN), and Silicon Carbide (SiC).
• the first photoresist layer is then stripped with the N 2 O gas mixture.
• Another first photoresist layer that is patterned for via etching is applied.
• a via is then
• ARC antireflective coating
• BARC that fills the via of the illustrative IC structure.
• the N 2 O gas mixture is then applied to etch back the ARC or BARC and results
• the third OSG layer is
• FIG. 1 is an illustrative apparatus capable of removing a photoresist from an IC
• FIG. 2 is a flowchart for stripping photoresist in a via first dual damascene
• FIG. 3 A through FIG. 3H is an isometric view of the via etch and strip
• FIG. 4 is a flowchart for stripping photoresist in a trench first dual damascene
• FIG. 5 A through FIG. 5J is an isometric view of the trench etch and strip
• FIG. 1 there is shown an illustrative system for stripping
• system is a parallel plate plasma system 100 such as a 200 mm EXELAN HPT system
• the system 100 includes a chamber having an interior 102 maintained at a
• a vacuum pump 104 connected to an outlet in a wall of
• Etching gas can be supplied to the plasma reactor supplying gas from gas
• a medium density plasma can be generated in the reactor by a dual frequency arrangement wherein RF energy from RF source 108 is supplied through a
• the RF source 108 is configured
• Electrode 114 is a grounded electrode.
• substrate 116 is supported by the powered electrode 112 and is etched and/or stripped
• Coupled reactors can also be used such as reactors where RF power is supplied to both
• the plasma can be produced in various other types of plasma
• ECR electrochemical resonance
• reactors typically have energy sources which use RF energy, microwave energy,
• FIG. 2 there is shown a flowchart for stripping a photoresist in a
• the illustrative IC structure includes a first organic
• photoresist layer a second intermediate layer, a third OSG layer, and a fourth barrier
• the photoresist layer is an organic photoresist such as the 193 run photoresist or 248 nm photoresist from the Shipley
• the illustrative second intermediate layer is a cap layer composed of such
• SiO 2 Silicon Dioxide
• SiON Silicon Oxynitride
• the cap layer provides protection to the
• the third layer is an OSG
• layer and may include materials such as CORALTM from Novellus Systems of San
• OSG material may also be a porous OSG (pOSG)
• the pOSG may have a void space
• the illustrative fourth barrier layer is composed of such barrier
• silicon nitride Si 3 N 4
• silicon carbide SiC
• the barrier layer provides protection from copper diffusion.
• the flowchart in FIG. 2 describes the method 200 for performing a via first
• intermediate layer is a cap layer.
• the method is initiated at process block 202 in
• the IC structure is positioned in the illustrative reactor 100.
• the IC structure is positioned in the illustrative reactor 100.
• photolithography uses a
• a via is etched into the second cap layer, and the third OSG layer.
• the via is etched up to the barrier layer.
• N 2 0 is added to the reaction
• processing parameters may be practiced at operating pressures of 10 - 1000 mTorr, at
• processing parameters may be practiced at operating pressures of 100 - 350
• an inert gas may be used as a
• the inert gas may include nobles gases such as Argon, Helium, Neon,
• the inert gas may be used to control uniformity during the
• Table 1 Illustrative Process Parameter For Stripping Photoresist with N 2 O
• Table 1 the process parameters for a number of different "runs" are shown. The runs were performed on a 200 mm wafer at 20°C. During each run the pressure, power and N 2 O flow rate are adjusted. The resulting photoresist strip rate is shown at the far right of Table 1.
• the plasma strips the photoresist from the structure and generates a volatile by-product such as carbon dioxide (C0 2 ). For purposes of removing the
• the method then generates an organic plug for the via.
• the organic plug is
• the organic plug is generated by applying an organic
• the organic material is an antireflective coating (ARC) or a bottom antireflective
• BARC coating coating
• N 2 0 is added to the illustrative reactor 100 using the
• the N 2 O gas is
• organic plug By way of example and not of limitation, the organic plug has a plug
• the plug height needs to be of sufficient height to prevent fence formation
• the method described above permits the stripping of the photoresist to be performed in
• the other gases or gas mixtures include ammonia (NH 3 ), oxygen (0 2 ), and the nitrogen and hydrogen (N 2 / H 2 ) gas mixture.
• FTIR Fourier Transform Infrared
• a blanket CORALTM wafer was used as the illustrative OSG material.
• the CORALTM wafer was exposed to different gasses to determine changes in the ratio of the Si-C peak to the SiO peak. The Si-C and SiO peaks indicate changes to the OSG material.
• N 2 O results in the lowest change in the SiC/SiO ratio which indicates that the OSG material is affected least by the N 2 0 stripping.
• N 2 0 a strip rate is comparable to the NH 3 strip rate, however N 2 0 stripping operates with significantly lower power demands than NH 3 stripping. Additionally, N 2 0 stripping may avoid the particle generation associated with NH 3 stripping.
• the N 2 O stripping process is a milder oxidant than O 2 which results in less oxidation of the OSG material. Less oxidation of the OSG
• FIG. 3 A through FIG. 3H there is shown an isometric view of the
• FIG. 3 A shows an isometric
• intermediate cap layer 304 a third OSG layer 306, and a fourth barrier layer 308.
• the illustrative IC structure is positioned in the illustrative reactor
• FIG. 3B shows the illustrative IC structure after performing the via first etch in
• FIG. 3C there is shown the illustrative IC structure after having added the
• remaining IC structure includes inter alia the visible cap layer 304 and the via 310.
• FIG. 3D there is shown the illustrative IC structure after adding an
• organic plug 314 is shown within the via 310.
• the organic plug 314 is generated by
• FIG. 3F the IC structure is shown after adding a layer of
• photoresist 316 as described in block 216.
• the photoresist 316 is patterned for trench
• the trench 318 is then etched as shown in FIG. 3G according to the trench etch process 218.
• the trench 318 is etched into the second cap layer and the third OSG
• the organic plug 314 prevents the faceting of the via 310.
• the method 200 permits the stripping of the photoresist to be
• FIG. 4 there is shown a flowchart for a method of stripping a
• photoresist in a trench first dual damascene process is applied to an
• the illustrative IC structure includes a first
• organic photoresist layer a second intermediate layer, a third OSG layer, and a fourth
• the photoresist layer is an organic photoresist as described above.
• illustrative second intermediate layer is a hardmask layer composed of such hardmask
• silicon nitride Si 3 N 4
• tantalum nitride TaN
• titanium nitride TiN
• SiC silicon carbide
• the IC structure is directly exposed to plasma during the etching process without the
• the third layer is an OSG layer such as CORALTM, and BLACK DIAMONDTM or any other such OSG materials. Additionally, the OSG
• pOSG porous OSG
• illustrative fourth barrier layer is composed of such barrier materials as silicon nitride
• Si 3 N silicon carbide
• SiC silicon carbide
• the flowchart in FIG. 4 describes the method 400 for performing a trench etch
• patterned into the photoresist layer is positioned in the illustrative reactor 100.
• N 2 O is added to the reaction chamber and a plasma is
• the operating parameters for the removal of the photoresist are similar to
• the plasma strips the photoresist from the structure and
• This other photoresist layer is patterned to for via etching.
• gases and process parameters used for via etching are dependent on a variety of parameters such as the type of
• N 2 O is again applied to illustrative system 100 at process
• the plasma is then formed when the N 2 O is
• the organic plug is generated by first applying an organic material such as BARC
• N 2 O is used to etch back the BARC or
• parameters for performing the trench etch are dependent on such parameters as the IC
• N 2 O plasma is used to remove the organic plug.
• FIG. 5 A through FIG. 5J there is shown an isometric view of the
• photoresist layer 502 a second intermediate hardmask layer 504, a third OSG layer
• the first organic photoresist layer has a trench
• FIG. 5B shows the illustrative IC structure after performing the process 404 in which the trench 510 is etched into the
• FIG. 5C there is shown the illustrative IC structure after having added the
• N 2 O from process 406 to chamber 100.
• the N 2 O is converted to a plasma that strips
• FIG. 5D there is shown the illustrative IC structure after adding
• FIG. 514 is etched into the IC structure as described in block 410.
• FIG. 5F shows the IC
• the organic plug is generated by first applying an organic material such as
• ARC 516 as described in block 414.
• the IC structure having the applied ARC 516 is
• FIG. 5G In FIG. 5H, there is shown the IC structure after an N 2 0 gas
• the OSG layer has been trench etched to the desired
• FIG. 5J shows the resulting IC structure

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• General Chemical & Material Sciences (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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• 2003
  • 2003-10-08 US US10/680,895 patent/US7202177B2/en not_active Expired - Lifetime
• 2004
  • 2004-10-04 TW TW093130026A patent/TW200523689A/zh unknown
  • 2004-10-05 WO PCT/US2004/032793 patent/WO2005038892A1/en not_active Ceased
  • 2004-10-05 CN CNB2004800291641A patent/CN100426469C/zh not_active Expired - Fee Related
  • 2004-10-05 JP JP2006534260A patent/JP2007508698A/ja active Pending
  • 2004-10-05 KR KR1020067008588A patent/KR101197070B1/ko not_active Expired - Fee Related
  • 2004-10-05 EP EP04794216A patent/EP1671363A4/en not_active Withdrawn

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