JP2007501526A5 - - Google Patents

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JP2007501526A5
JP2007501526A5 JP2006522694A JP2006522694A JP2007501526A5 JP 2007501526 A5 JP2007501526 A5 JP 2007501526A5 JP 2006522694 A JP2006522694 A JP 2006522694A JP 2006522694 A JP2006522694 A JP 2006522694A JP 2007501526 A5 JP2007501526 A5 JP 2007501526A5
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Japan
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semiconductor
pfet
nfet
single crystal
gate stack
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JP2006522694A
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Japanese (ja)
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JP4808618B2 (ja
JP2007501526A (ja
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Priority claimed from US10/604,607 external-priority patent/US6891192B2/en
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JP2006522694A 2003-08-04 2004-08-04 格子不整合のソースおよびドレイン領域を有する歪み半導体ｃｍｏｓトランジスタを有する集積回路および製作方法 Expired - Lifetime JP4808618B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/604,607 2003-08-04
US10/604,607 US6891192B2 (en) 2003-08-04 2003-08-04 Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions
PCT/US2004/025152 WO2005017964A2 (en) 2003-08-04 2004-08-04 Structure and method of making strained semiconductor cmos transistors having lattice-mismatched source and drain regions

Publications (3)

Publication Number Publication Date
JP2007501526A JP2007501526A (ja) 2007-01-25
JP2007501526A5 true JP2007501526A5 (enExample) 2007-09-06
JP4808618B2 JP4808618B2 (ja) 2011-11-02

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JP2006522694A Expired - Lifetime JP4808618B2 (ja) 2003-08-04 2004-08-04 格子不整合のソースおよびドレイン領域を有する歪み半導体ｃｍｏｓトランジスタを有する集積回路および製作方法

Country Status (10)

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US (3) US6891192B2 (enExample)
EP (1) EP1654770B1 (enExample)
JP (1) JP4808618B2 (enExample)
KR (1) KR100791441B1 (enExample)
CN (1) CN100428497C (enExample)
AT (1) ATE504078T1 (enExample)
DE (1) DE602004032035D1 (enExample)
IL (1) IL173422A (enExample)
TW (1) TWI284961B (enExample)
WO (1) WO2005017964A2 (enExample)

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