JP2007123923A - 触媒及び化学気相蒸着法を用いて銅配線及び薄膜を形成する方法 - Google Patents
触媒及び化学気相蒸着法を用いて銅配線及び薄膜を形成する方法 Download PDFInfo
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Abstract
【解決手段】能動及び受動素子を配線連結するために、銅配線導電体を形成する方法が開示される。ここに開示された発明は、触媒と共に銅を配線導電体物質の原料とするCVD工程を含む。トレンチ、ビアホール、コンタクト、広い受動素子だけでなく電力素子と電力線のための大きいトレンチとホールを充填する配線方法がここに開示されて提供される。ここに提示された他の方法は、狭くて深いトレンチと小径で深いホールのような小さな陥没部を触媒を使用した銅CVDで充填する方法であり、湿式または乾式エッチバックまたは高温プラズマエッチバック工程により後続工程段階に備えて除去されるように扁平な最上部の表面に非常に薄い薄膜を形成する方法である。
【選択図】図1d
Description
触媒を使用した銅CVD方法でトレンチ、ビアホール及びコンタクトのような配線導電体を形成する方法が後述される。
シリコン基板に埋め込まれた配線導電体は多様な形と大きさを有する。電力及び信号適用のための配線導電体は一般に大きい。しかし、前記の第1実施例で説明したような本発明による触媒を使用した銅CVDに基づいた銅充填方法は、入力/出力(I/O)信号及び電力線のためのパッドのように非常に小さな縦横比の広い面積を充填するには適していない。
第1実施例で既に説明したように、図2aを参照すれば、最上面だけでなくトレンチ220内部にバリヤー膜230とシード層240を有するシリコン基板サンプルが備えられる。一般に、スパッタリング方法がシード層240だけでなくバリヤー膜230を形成するのに利用される。しかし、トレンチ及びビアホールの上端開口部が狭い場合にはTaNまたはTiNを使用してバリヤー膜230を形成するのにCVD方法が利用されることがあり、またシード層240を形成するのに触媒としてヨード化エチルを使用する銅CVD方法も利用されうる。銅原料物質(hfac)Cu(vtms)は第1実施例と同様にここに再び使われる。
一般に、二重ダマシン構造に電気メッキを使用することは難しいが、これは図3aでスタックされたトレンチ324で表現されたようにビアホールとスタックされたトレンチが深いからである。本発明による触媒を使用した銅充填方法はこのような二重ダマシン構造の状況でより適した方法である。
回路密度が増加するにつれてデザインルールは益々厳しくなり、トレンチとホールの上端開口部は益々狭くなって小さくなる。このような場合に、触媒は底部に深く浸透できなくて従来のスパッタリング方法は銅シード層を形成するのに適していない。したがって“触媒を加えてから銅を蒸着する”サイクルを反復的に行う必要がある。本実施例ではこのような場合の解決法を提示する。
本発明によれば、触媒を使用した銅CVDで配線導電体を形成する方法は既に言及したように多くの長所を有する。まず、銅層成長速度はトレンチ、ビアホール及びコンタクトのように狭くて深い構造の底部で最も速い。順次に銅層が成長するにつれて成長速度は急激に減少し、一般に上面で最も遅くなる。結果的に、例えば図5aを参照すれば、トレンチ520は銅で速く充填されるが、上面には銅層554が一般に遅く成長して薄い銅層554だけ形成される。後続の段階で、良好な配線導電体を形成するために、導電層530、540、554は導電体の次の層が積もるように除去されねばならない。
これは本発明によって図5aの上部導電層530、540、554をCMP方法で除去して平坦化する他の例示的方法である。図5cを参照すれば、化学エッチング剤580が銅層554の全面に加わって、図5dに示したように導電層のない扁平な表面が形成される。これは本発明により図5aの上面導電層530、540、554が非常に薄いために可能である。
これは本発明によって図5aの上面導電層530、540、554を高温プラズマエッチングで除去して平坦化するさらに他の例示的方法である。図5eを参照すれば、高温プラズマエッチング582が図5aの上面導電層530、540、554を除去するために全面に加えられる。その結果、図5fの平坦な表面を得られる。これは本発明によって図5aの上面の導電層530、540、554が非常に薄いために可能である。
これは本発明によって図5aの上面の導電層530、540、554を選択的エッチングで除去して平坦化するさらに他の例示的方法である。図5gを参照すれば、フォトレジストバリヤー膜584が必要に応じて形成される。次に残っている部分がエッチングされて、表面に導電体が残っていない扁平な上面だけでなく“突出した”導電体570dが形成される。これは本発明によって図5aの上面導電層530、540、554が非常に薄いために可能である。この“突出した”導電体570dは、例えばI/O端子のパッドとして使われうる。
Claims (30)
- シリコン基板の絶縁膜に陥没部を形成する段階と、
全面にシード層を形成する段階と、
前記全面に触媒を加える段階と、
前記全面にCVD方法で銅物質を蒸着する段階とを順に含む配線導電体の形成方法。 - 前記シード層を形成する前にシリコン基板の全面にバリヤー膜を蒸着する請求項1に記載の配線導電体の形成方法。
- 前記バリヤー膜はTaNまたはTiN、または両方ともで形成する請求項2に記載の配線導電体の形成方法。
- 前記バリヤー膜はTa、Ti、Ta−Si−N及びTi−Si−Nまたはこれらの任意の組合わせを利用して形成する請求項2に記載の配線導電体の形成方法。
- 前記陥没部は互いに連結されるようにシリコン基板の絶縁膜内にトレンチ、ホール、空洞、コンタクトとこれらの組合わせとを含む請求項1に記載の配線導電体の形成方法。
- 前記陥没部は単一または二重ダマシンまたはこれらの組合わせを含む請求項1に記載の配線導電体の形成方法。
- 前記触媒はヨードまたはブロム、または両方ともである請求項1に記載の配線導電体の形成方法。
- 前記触媒はハロゲン元素族の元素またはこれらの任意の組合わせである請求項1に記載の配線導電体の形成方法。
- CVDに使われる銅物質は(hfac)Cu(vtms)である請求項1に記載の配線導電体の形成方法。
- 銅を蒸着するためのCVDチャンバの温度は50℃より高く、250℃より低い請求項9に記載の配線導電体の形成方法。
- 前記銅シード層の厚さは100nmを超えない請求項1に記載の配線導電体の形成方法。
- 銅を蒸着するためのCVDチャンバの作動圧力は10Torr未満である請求項1に記載の配線導電体の形成方法。
- シリコン基板の絶縁膜に単一ダマシン、二重ダマシンまたはこれらの組合わせを形成する段階と、
全面にシード層を形成する段階と、
二重ダマシン構造を構成するためにバリヤー膜と銅シード層とを形成する段階を反復する段階と、
前記銅シード層は触媒を使用した銅CVD方法で形成する段階と、
残っている伝導性銅層を前記銅シード層を電極として使用する電気メッキ技術で形成する段階とを順に含む配線導電体の形成方法。 - 前記シード層を形成する前にシリコン基板の全面にバリヤー膜を蒸着する請求項13に記載の配線導電体の形成方法。
- 前記バリヤー膜を形成するのに使われる物質はTa、Ti、TaN、TiN、Ta−Si−N及びTi−Si−Nである請求項14に記載の配線導電体の形成方法。
- 前記触媒はヨードまたはブロムまたは両方とも、またはハロゲン元素族の任意の元素を含む請求項13に記載の配線導電体の形成方法。
- 銅CVDを使用して前記銅シード層を形成するための銅物質は(hfac)Cu(vtms)である請求項13に記載の配線導電体の形成方法。
- 前記銅シード層はスパッタリングで形成し、前記残っている伝導性銅層は前記バリヤー膜及び前記銅シード層を形成した後、触媒を使用した銅CVDで形成する請求項13に記載の配線導電体の形成方法。
- 前記触媒はヨードまたはブロムまたは両方とも、またはハロゲン元素族の任意の元素を含む請求項18に記載の配線導電体の形成方法。
- 前記バリヤー膜を形成するのに使われる物質はTa、Ti、TaN、TiN、Ta−Si−N及びTi−Si−Nである請求項18に記載の配線導電体の形成方法。
- 触媒を利用する銅CVDを使用して前記残っている伝導性銅層を形成するための銅物質は(hfac)Cu(vtms)である請求項18に記載の配線導電体の形成方法。
- 互いに連結されるようにシリコン基板の絶縁膜内にトレンチ、ホール、空洞、コンタクトとこれらの組合わせのような陥没部を形成する段階と、
全面にシード層を形成する段階と、
前記全面に触媒を加える段階と、
トレンチ、ホール、空洞、コンタクトなどを充填するために銅CVD方法で前記全面に銅物質を蒸着する段階と、
前記表面の扁平な部分に薄い銅層が形成されるまで銅を蒸着する段階と、
後続の工程段階で前記薄い銅層を除去する段階とを順に含む配線導電体の形成方法。 - 前記シード層を形成する前にシリコン基板の全面にバリヤー膜を蒸着する請求項22に記載の配線導電体の形成方法。
- 前記バリヤー膜を形成するのに使われる物質はTa、Ti、TaN、TiN、Ta−Si−N及びTi−Si−Nである請求項23に記載の配線導電体の形成方法。
- 前記触媒はヨードまたはブロムまたは両方とも、またはハロゲン元素族の任意の元素を含む請求項22に記載の配線導電体の形成方法。
- 銅CVDを使用して前記銅シード層を形成するための銅物質は(hfac)Cu(vtms)である請求項22に記載の配線導電体の形成方法。
- 前記薄い銅層を除去する段階はCMP方法で行う請求項22に記載の配線導電体の形成方法。
- 前記薄い銅層を除去する段階は湿式化学的エッチング方法で行う請求項22に記載の配線導電体の形成方法。
- 前記薄い銅層を除去する段階は高温プラズマ−エッチング方法で行う請求項22に記載の配線導電体の形成方法。
- 前記薄い銅層を除去する段階は、パッドとして使用するためのトレンチ、ホール、空洞、コンタクトなどの陥没部の上部を保存するためのフォトレジストパターンを使用して選択的湿式エッチングで行う請求項22に記載の配線導電体の形成方法。
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Also Published As
Publication number | Publication date |
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JP3925780B2 (ja) | 2007-06-06 |
DE60041522D1 (de) | 2009-03-19 |
JP4792379B2 (ja) | 2011-10-12 |
KR100465982B1 (ko) | 2005-01-13 |
US20010019891A1 (en) | 2001-09-06 |
US6720262B2 (en) | 2004-04-13 |
JP2003517205A (ja) | 2003-05-20 |
EP1247292A1 (en) | 2002-10-09 |
JP2007123924A (ja) | 2007-05-17 |
WO2001045149A1 (en) | 2001-06-21 |
EP1247292B1 (en) | 2009-02-04 |
KR20020065574A (ko) | 2002-08-13 |
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