JP2007013085A - 半導体素子の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000001312 dry etching Methods 0.000 claims abstract description 25
- 238000002955 isolation Methods 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 239000011259 mixed solution Substances 0.000 claims description 13
- 239000000243 solution Substances 0.000 claims description 13
- 125000000896 monocarboxylic acid group Chemical group 0.000 claims description 11
- 229910052754 neon Inorganic materials 0.000 claims description 10
- 229910017840 NH 3 Inorganic materials 0.000 claims description 5
- 229910017855 NH 4 F Inorganic materials 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 5
- 239000003054 catalyst Substances 0.000 claims description 5
- 229910052801 chlorine Inorganic materials 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 5
- 229910052734 helium Inorganic materials 0.000 claims description 5
- 229910052743 krypton Inorganic materials 0.000 claims description 5
- 229910052704 radon Inorganic materials 0.000 claims description 5
- 229910052724 xenon Inorganic materials 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 4
- 230000009257 reactivity Effects 0.000 claims description 3
- 239000002184 metal Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
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Abstract
【解決手段】 アクティブ領域を画定する素子分離膜2が形成された半導体基板1を設けるステップと、半導体基板1上に絶縁膜3を形成するステップと、絶縁膜3上にリセス予定領域を画定するマスクパターンを形成するステップと、マスクパターンをエッチングマスクに絶縁膜3をエッチングしてリセス予定領域を露出させるステップと、露出されたリセス予定領域を一次等方性エッチングして第1溝7を形成するステップと、第1溝7の底面下の半導体基板部分を2次ドライエッチングして第2溝8を形成するステップと、第2溝8を含む第1溝7上にゲート13を形成するステップとを含む。
【選択図】 図1E
Description
2 素子分離膜
3 酸化膜
4 ポリシリコン膜
5 反射防止膜
6 マスクパターン
7 第1溝
8 第2溝
9 ゲート酸化膜
10 ゲートポリシリコン膜
11 ゲート金属シリサイド膜
12 ゲートハードマスク膜
13 リセスゲート
Claims (19)
- アクティブ領域を画定する素子分離膜が形成された半導体基板を設けるステップと、
前記半導体基板全面上に酸化膜、ポリシリコン膜、及び反射防止膜を順次形成するステップと、
前記反射防止膜上に前記半導体基板の前記アクティブ領域におけるリセス予定領域を画定するマスクパターンを形成するステップと、
前記マスクパターンをエッチングマスクとして用い、前記反射防止膜、前記ポリシリコン膜、及び前記酸化膜を順次エッチングして前記アクティブ領域の前記リセス予定領域を露出させるステップと、
露出された前記リセス予定領域を1次エッチングして、第1の幅及び第1の深さを有する第1溝を形成するステップと、
前記マスクパターン及び前記反射防止膜を順次除去するステップと、
エッチングされた前記ポリシリコン膜をエッチングマスクとして用い、前記第1溝の底面下の前記半導体基板部分を2次エッチングして、前記第1の幅より狭い第2の幅及び第2の深さを有する第2溝を形成するステップと、
前記ポリシリコン膜及び前記酸化膜を順次除去するステップと、
前記第2溝を含む第1溝の上にゲートを形成するステップと、を含むことを特徴とする半導体素子の製造方法。 - 前記1次エッチングは、HF、NH4F、HNO3、CH3COOH、H2O2及びH2Oの混合溶液を利用したウェトエッチングであることを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記CH3COOH溶液は、前記混合溶液全体に対する比率が約1〜50%であることを特徴とする請求項2に記載の半導体素子の製造方法。
- 前記HNO3溶液は、前記混合溶液全体に対する比率が約1〜50%であることを特徴とする請求項2に記載の半導体素子の製造方法。
- 前記1次エッチングは、反応性が向上するように約25〜100℃の温度で行われることを特徴とする請求項2に記載の半導体素子の製造方法。
- 前記第1溝は、約10〜1000Åの深さを有するように形成されることを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記2次エッチングは、 HBr、N2、Ar、Ne及びCl基を含んだ混合ガスを利用したドライエッチングであることを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記2次エッチングは、前記第1溝のエッチング底面にダメージを与えて結晶格子を破壊するプラズマドライエッチングであることを特徴とする請求項7に記載の半導体素子の製造方法。
- 前記プラズマドライエッチングは、約25〜700℃の温度、約13.3〜13332.2Pa(0.1〜100Torr)の圧力、約10〜2000Wのパワー、そして、還元雰囲気下で行われることを特徴とする請求項8に記載の半導体素子の製造方法。
- 前記プラズマドライエッチングは、Ne、He、NH3、Kr、Xe及びRnから構成されるグループより選択されるいずれか一つのガスを触媒ガスとして添加して行われることを特徴とする請求項8に記載の半導体素子の製造方法。
- 前記第2溝は、約300〜3000Åの深さを有するように形成されることを特徴とする請求項1に記載の半導体素子の製造方法。
- アクティブ領域を画定する素子分離膜が形成された半導体基板を設けるステップと、
前記半導体基板全面上に絶縁膜を形成するステップと、
前記絶縁膜上に前記半導体基板の前記アクティブ領域におけるリセス予定領域を画定するマスクパターンを形成するステップと、
前記マスクパターンをエッチングマスクとして用い、前記絶縁膜をエッチングして前記アクティブ領域の前記リセス予定領域を露出させるステップと、
露出された前記アクティブ領域の前記リセス予定領域を一次等方性エッチングして、第1の幅及び第1の深さを有する第1溝を形成するステップと、
前記第1溝の底面下の前記半導体基板部分を2次ドライエッチングして、前記第1の幅より狭い第2の幅及び第2の深さを有する第2溝を形成するステップと、
前記第2溝を含む前記第1溝の上にゲートを形成するステップと、を含むことを特徴とする半導体素子の製造方法。 - 前記1次等方性エッチングは、HF、NH4F、HNO3、CH3COOH、H2O2及びH2Oの混合溶液を用いて行われることを特徴とする請求項12に記載の半導体素子の製造方法。
- 前記CH3COOH溶液は、前記混合溶液全体に対する比率が約1〜50%であることを特徴とする請求項13に記載の半導体素子の製造方法。
- 前記HNO3溶液は、前記混合溶液全体に対する比率が約1〜50%であることを特徴とする請求項13に記載の半導体素子の製造方法。
- 前記2次ドライエッチングは、HBr、N2、Ar、Ne及びCl基を含む混合ガスを使用して行われることを特徴とする請求項12に記載の半導体素子の製造方法。
- 前記2次ドライエッチングは、前記第1溝のエッチング底面にダメージを与えて結晶格子を破壊するプラズマドライエッチングであることを特徴とする請求項16に記載の半導体素子の製造方法。
- 前記プラズマドライエッチングは、約25〜700℃の温度、約13.3〜13332.2Pa(0.1〜100Torr)の圧力、約10〜2000Wのパワー、そして、還元雰囲気下で行われることを特徴とする請求項17に記載の半導体素子の製造方法。
- 前記プラズマドライエッチングは、Ne、He、NH3、Kr、Xe及びRnから構成されるグループから選択されるいずれか一つのガスを触媒ガスとして添加して行われることを特徴とする請求項18に記載の半導体素子の製造方法。
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KR1020050058570A KR100608386B1 (ko) | 2005-06-30 | 2005-06-30 | 반도체 소자의 제조방법 |
KR10-2005-0058570 | 2005-06-30 |
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JP5127137B2 JP5127137B2 (ja) | 2013-01-23 |
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US (2) | US7413969B2 (ja) |
JP (1) | JP5127137B2 (ja) |
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CN (1) | CN100463113C (ja) |
TW (1) | TWI263307B (ja) |
Cited By (2)
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KR100849189B1 (ko) | 2007-02-12 | 2008-07-30 | 주식회사 하이닉스반도체 | 리세스 게이트를 갖는 반도체 소자 및 그 제조 방법 |
JP2008210994A (ja) * | 2007-02-27 | 2008-09-11 | Nec Electronics Corp | 横型mosfetおよびその製造方法 |
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KR100732767B1 (ko) * | 2005-12-29 | 2007-06-27 | 주식회사 하이닉스반도체 | 반도체 소자의 리세스 채널용 트렌치 형성방법 |
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US10008417B1 (en) * | 2017-06-12 | 2018-06-26 | International Business Machines Corporation | Vertical transport fin field effect transistors having different channel lengths |
CN107464749B (zh) * | 2017-07-28 | 2021-09-17 | 北京北方华创微电子装备有限公司 | 蚀刻方法和蚀刻系统 |
CN112885770A (zh) * | 2019-11-29 | 2021-06-01 | 长鑫存储技术有限公司 | 浅沟槽隔离结构、半导体结构及其制备方法 |
CN112864155B (zh) * | 2021-01-04 | 2022-05-03 | 长鑫存储技术有限公司 | 半导体结构的制造方法及半导体结构 |
CN113892176A (zh) * | 2021-08-31 | 2022-01-04 | 长江存储科技有限责任公司 | 半导体结构、制作方法及三维存储器 |
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Also Published As
Publication number | Publication date |
---|---|
JP5127137B2 (ja) | 2013-01-23 |
TWI263307B (en) | 2006-10-01 |
KR100608386B1 (ko) | 2006-08-08 |
CN1892988A (zh) | 2007-01-10 |
US20070004145A1 (en) | 2007-01-04 |
TW200701403A (en) | 2007-01-01 |
CN100463113C (zh) | 2009-02-18 |
US20080272431A1 (en) | 2008-11-06 |
US7413969B2 (en) | 2008-08-19 |
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