TWI263307B - A method of manufacturing semiconductor device having recess gate structure with varying recess width for increased channel length - Google Patents
A method of manufacturing semiconductor device having recess gate structure with varying recess width for increased channel length Download PDFInfo
- Publication number
- TWI263307B TWI263307B TW094146561A TW94146561A TWI263307B TW I263307 B TWI263307 B TW I263307B TW 094146561 A TW094146561 A TW 094146561A TW 94146561 A TW94146561 A TW 94146561A TW I263307 B TWI263307 B TW I263307B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- recessed hole
- recessed
- substrate
- width
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 69
- 238000000034 method Methods 0.000 claims description 24
- 239000000243 solution Substances 0.000 claims description 14
- 239000011259 mixed solution Substances 0.000 claims description 11
- 230000001681 protective effect Effects 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 7
- 229910052754 neon Inorganic materials 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 5
- 239000011241 protective layer Substances 0.000 claims description 5
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 claims description 4
- 230000003667 anti-reflective effect Effects 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 230000003197 catalytic effect Effects 0.000 claims description 3
- -1 HN03 Chemical compound 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 235000012054 meals Nutrition 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 229910052707 ruthenium Inorganic materials 0.000 claims 1
- 229910052709 silver Inorganic materials 0.000 claims 1
- 239000004332 silver Substances 0.000 claims 1
- 239000007789 gas Substances 0.000 description 7
- 238000009825 accumulation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052734 helium Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000002156 mixing Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 241000283690 Bos taurus Species 0.000 description 1
- 241000238631 Hexapoda Species 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 241000239226 Scorpiones Species 0.000 description 1
- 244000269722 Thea sinensis Species 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000001804 emulsifying effect Effects 0.000 description 1
- 229910052743 krypton Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000006138 lithiation reaction Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000008267 milk Substances 0.000 description 1
- 210000004080 milk Anatomy 0.000 description 1
- 235000013336 milk Nutrition 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 229910052704 radon Inorganic materials 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
Description
1263307 九、發明說明: … 【發明所屬之技術領域】 - 本發明是關於半導體元件的製造方法,特別是具 有凹孔結構以增加通道長度的半導體元件製造方法。 【先前技術】 傳統平面結構的電晶體已經無法符合近來 _ DRAM元件高集積度的技術需求,舉例來說,傳統 的電晶體結構已經無法符合高集積度電晶體的臨界 目標。隨著DRAM元件集積度的增加必須縮小最小 特徵尺寸,而縮小最小特徵尺寸會造成基板摻雜濃度 增加’使得電場強度和電晶體的界面漏電流增加。 因此,有一種稱為’’凹孔閘極結構π的主動結構, 這種具有三度空間的結構可以降低基板摻雜濃度和 界面漏電流。 籲 傳統的凹孔閘極結構’其形成閘極的主動區為凹 陷結構,而閘極則形成在主動區的凹孔,藉以增加通 道長度。該傳統形成在主動區的凹孔閘極結構,可以 ^ 降低基板的摻雜濃度,並增加資料維持時間。而且隨 ' 著通道長度增加(由於該主動區的凹孔通道結構),可 以改善源極引發能障衰退(drain induced barvier lowering, DIBL)和崩潰電壓(breakdown voltages, BVds)的特性,並改善整個元件的特性。 1263307 由於凹孔通道結構可以延長f料維持時間,例如 大於2〇〇mS,因此可以預期在小於9〇nm的Dram 元件中會使用凹孔通道結構。 、,如上述,形成在主動區凹孔的凹孔通道結構閘極 會η這長度。可是當該主動區縮小時,通道長度 也會跟者減少’因此即使使用凹孔閘極結構所能增加 的效;也會党限。因此’會減少抑制界面漏電流的效 C以^兀件在更新特性上的改善。結果變得很難碟 ”…有縮』主動區的元件維持一致的可靠度和良率。 【發明内容】 因此,為了解決習知技術的上述和其他問題, 發明之目的在提供一種可以充分增加通道長度的半 導體元件製造方法。 :發明之另一個目的在提出一種可以充分增加 並::ί:半導體疋件製造方法,以有效降低漏電流 亚改善更新特性。 =了達到這個目的,本發明提出—種半導體元件 々广方法,該方法具有下列步驟:在半導體 ?成定義主動區的隔離層;在半導體基板上依序形成 :化層、多晶矽層和抗反射層;在抗反射層上形成定 基板凹孔區的保護圖形;以保護圖形作為餘刻 预:】虫刻抗反射層、多晶矽層和氧化層’藉此露出 預疋基板凹孔區;在敎基板凹孔區進行第一餘刻, 1263307 藉此开/成%•狀第—溝槽;去除保護圖形和抗反射層; 以姓刻的多晶秒層作為餘刻保護層,在第—溝槽底部 =基板抽進仃第二餘刻,藉此形成具有垂直側壁的 弟一溝槽,去除多晶矽層和氧化層;並在具有第二溝 槽的第一溝槽上形成閘極。 第一蝕刻最好使用HF,NH4F,HN03’ CH3CO〇H,Η2〇α h2〇的混合溶液來進行。混合 =含有卜50%的CH3C〇〇H溶液。而混合溶液也 含有1〜50%的hno、、六、六 〇3,夺液。弟一蝕刻的溫度最好介於 和1〇〇。(:之間以增加㈣m 第一溝槽的深度約為10〜1000A。 第々二贼刻最好是以含有服鳴ϋ和 的乳體來進行。而且第二乾钱刻是破壞第一溝槽 虫刻面晶格的電漿飯刻。 電漿姓刻的溫度介於抓和辦,壓力介於 中進一二:功率介於10和2000瓦並在低壓氣氛 仃。包漿蝕刻時選擇添加Ne,He,NH3,Kr, 入e和尺n Ji Φ夕„ PL· ,、甲之一的氣體作為催化氣體。 第二溝槽的深度約為300〜3000A。 件的Si:殺明的另—實施態樣,提出-種半導體元 切該方法具有下列步驟:在半導體基板 緣層;動區的隔離層;在半導體基板上形成絕 9 、巴、’ 4上形成定義預定基板凹孔區的保護圖 1263307 圖形作為_護層名虫刻 出預疋基板凹孔區;在預定基板凹孔區進行第一等向 性蚀刻,藉以形成第-溝槽;在第-溝槽底部的基板 ^伤進行第,乾❹卜藉以形成第二溝槽;並在具有 第一溝槽的第一溝槽上形成閘極。 第一等向性蝕刻最好是以hf,NH4F,hn〇3, ch3cooh ’ h2o2和h2〇的混合溶液來進行。混合
溶液含有!〜50%@叫⑺⑽溶液。而混合溶液也 含有1〜50%的HN〇3溶液。 第二乾蝕刻最好是以含有HBr,n2, Ar,Ne*
Cl的氣體來進行。而且第二乾蝕刻是破壞第一溝槽 飯刻面晶格的電漿蝕刻。 私漿蝕刻的溫度介於25。(:和700〇c,壓力介於 0.1〜100牦耳,功率介於1〇和2000瓦並在低壓氣氛 中進行。電漿蝕刻時選擇添加Ne,He,Nh3, Kr, Xe和Rn其中之一的氣體作為催化氣體。 【實施方式】 接下來本發明的較佳具體實施例將參考附圖說 明如下^ 第1 A-1E圖是根據本發明實施例說明製造半導 體元件方法的橫截面圖。 茶考第1A圖,在半導體基板1中形成由隔離層 2兩個部份所定義的主動區。然後,依序在半導體基 1263307 ^的主動區和部份的隔離層2上形成氧化層3和多 日日:層4。之後,在多晶石夕層4上形成抗反射層$, 亚在抗反射層5上形成保護圖形6以定義可以凹入 (或钱刻)基板1的區域。 在本貫把例中,多晶矽層4用來作為在基板i中 形成凹孔的保護層。然而,也可以使用例如氮化物声 的絕緣層來取代。 曰 _ 芩考第1B圖,使用保護圖形6作為蝕刻保護層 依序飿刻抗反射層5、多晶石夕層4和氧化層3,露出 基板1主動區中預計形成凹孔的區域。 芩考第1C圖,露出的基板區以保護圖形6作為 蝕刻保護層,經由第一等向性溼蝕刻在基板〗中形成 第一凹孔7。如第1C圖,第一凹孔7的底面形狀可 以疋原弧形或碗狀;也可以是銳角形或其他形狀。第 一凹孔7從基板1表面量起的深度約為1〇〜1〇〇〇人。 ❿ 之後去除凹孔閘極保護圖形6和抗反射層5。 第一等向性溼蝕刻所使用的溶液為的HF、 NH4F、hn〇33、ch3co〇h、h2o2 和 H2o 的混合溶 ^ 液。為了增加蝕刻反應性,蝕刻的溫度介於25。(2和 100QC。在蝕刻溶液中作為穩定劑的cHsCOOH溶 液’其含量佔整個溶液的1〜50%。而HN〇3則作為 CH3C〇〇H反應耗盡時的補充劑。因此,hn〇3溶液 的量佔整個蝕刻溶液的1〜50%。
1263307 參考第ID圖,第一凹孔7的底面部份經由第二 乾蝕刻,形成寬度比第一凹孔7小的第二凹孔8。第 二凹孔8的深度從基板1的表面量起約為 300 3000A。之俊’去除多晶石夕層4和氧化層3。第 一乾蝕刻使用含有HBr、N2、Ar、Ne和C1的氣體 來進行。 此外,第二乾蝕刻是破壞第一溝槽7蝕刻面晶格 的電漿蝕刻。電漿蝕刻的溫度介於25〇c* 7〇〇。〔, 壓力介於0.1〜100托耳,功率介於10和2〇〇〇瓦並 在低壓氣氛中進行。電漿蝕刻時,可以選擇Ne,He, ΝΗ3,^,ΧΜσ Rn其中之—的氣體作為催化氣體。 ’考第1E圖’在基板!具有第二凹孔8和第一 二孔7的主動區上形成閘極氧化層9。然後,在閘極 乳化層9上,依序形成閘極多晶砍層1()、閘極金屬 石夕化物層11和閘極保護層12。 之後,將閘極保護層12钱刻出圖形,並以姓刻 =閘極保護層12來㈣閘極保護層12下面的問極金 屬石夕化㈣η、閘極多㈣層1Q和閘極氧化層9, :匕在第#第—凹孔7、8中形成凹孔閘極如 弟1E圖)。 藉著依序進行一系列未圖 步驟,完成本發明實施例具有 元件。 示於圖中的習知製程 凹孔閘極13的半導體 11 1263307 的半S述:f本發明實施例具有凹孔閉極(例如13) ==牛製程中,基板的主動區(例如υ經由兩 们蝕刻步驟形成凹孔。因此,相較於 4 半導體元件,本發明半導體元# 、早人X丨的 的通道長度。 …件的凹孔間極具有較長 因此,藉由本發明在基板預計形成 的主動區區域,進行兩次㈣,即使縮小主動區) 可以確保足夠㈣道長度。因此,本發心以有效降 低界面漏電流並改善更新特性。0此,本發明可 由降低漏電流達到改善半導體元件良率、可曰 更新特性的效果。 >本發明上述最佳實施例僅作為解釋目的,對於 何熟悉此項㈣的a員都有可能在不偏離本 請範圍的條件下,進行的各種修改、 加。 文取代或附
12 1263307 【圖式fs〗单說明】 第1A〜1E圖是根據本發明實施例說明半導體元 件製造方法的橫截面圖。
【主要元件符號說明】 1 : 基板 2 : 隔離層 3 : 氧化層 4 : 多晶矽層 5 : 抗反射層 6 : 保護圖形 7 : 第一凹孔 8 : 第二凹孔 9 : 閘極氧化層 10 : 閘極多層石夕晶層 11 : 閘極金屬矽化物層 12 : 閘極保護層 13 : 凹孔閘極 13
Claims (1)
1263307 十、申請專利範圍: L 一種具有由隔離層所定義的主動區的半導體元件 製造方法,該方法具有下列步驟: 在半導體基板的主動區依序形成··(1)氧化層 或具有氮化物層的絕緣層;(2)多晶矽層;和(3") 抗反射層; 在抗反射層上形成定義預定基板凹孔區的保 護圖形; 藉由保護圖形兹刻抗反射層、多晶矽層和氧 化層或絶緣層’並露出預定基板的凹孔區; 在預定基板凹孔區進行第一蝕刻,形成具有 第一凹孔寬度和第一凹孔深度的第一凹孔; 去除保護圖形和抗反射層; 在第一凹孔的部份底面進行第二蝕刻,並以 蝕刻的多晶矽層作為蝕刻保護層,形成具有第二 凹孔莧度第二凹孔深度的第二凹孔,其中,第一 凹孔寬度比第二凹孔寬度寬; 去除多晶石夕層和氧化層;和 在第一和第二凹孔中形成閘極。 2·如申請專利範圍第i項的方法,其中第一蝕刻是 以具有 HF,NH4F,HN03,CH3COOH,H2〇2 和H2〇的混合溶液來進行。 3·如申請專利範圍第2項的方法,其中混合溶液含 有1〜50%的CH3C〇〇H溶液。 14 !2633〇7 4·如申請專利範圍第2項的方法’其中的混合溶液 含有1〜50%的ΗΝ〇3溶液。 5·如申請專利範圍第2項的方法,其中第一蝕刻步 驟的溫度介於25°C和1〇〇。(:。 6. =申請專利第1項的方法,其中從基板表面 量起的第一凹孔深度為10〜1000人。 7. 如申請專利範圍帛1項的方法,其中第二蝕刻步 • 驟是以含有HBr,N2, Ar,Ne和C1的氣體來進 行。 8. 如申請專利範圍第7項的方法,其中第二蝕刻步 驟為破壞第一凹孔蝕刻面晶格的電漿蝕刻。 9·如申請專利範圍第δ項的方法,其中電漿蝕刻的 /皿度介於25°C和700°C,壓力介於〇 jhoo托耳 ,功率介於10和2000瓦並在低壓氣氛中進行。 1〇·如申請專利範圍第8項的方法,其中,電漿蝕刻 • 可以選擇仏,He,NH3, Kr,以和Rn其中之 一的氣體作為催化氣體。 11· ^申請專利範圍第}項的方法,其中從基板表面 量起的第二凹孔深度為3〇〇〜3〇〇〇A。 • 12· —種具有由隔離層所定義的主動區的半導體元件 製造方法,該方法具有下列步驟: 在半導體基板上形成絕緣層; 在絕緣層上形成定義預定基板凹孔區的保護 15 1263307 圖形; 勉刻絕緣層以保護圖形作為蝕刻保護層,藉 以露出預定基板凹孔區; 在預定基板凹孔區進行第一等向性银刻,藉 以形成具有第一凹孔寬度和第一凹孔深度的第— 凹孔; 在弟一凹孔底部的基板部份進行第二乾餘 刻’藉以形成具有第二凹孔寬度和第二凹孔深度 的第二凹孔,其中第一凹孔寬度比第二凹孔的寬 度寬;以及 牡乐一和弟二凹孔中形成閘極。 13. 如申請專利範圍第12項的方法,其中第一等向性 钱刻是以具有 HF, ΝΗ4Ρ,ΗΝ〇3,^3〇ΧΚ)Η, Η2〇2和HaO的混合溶液來進行。 14. =申請專利㈣第13項的方法,其中的混合溶液 έ有1〜50%的CH3CO〇H溶液。 15♦如申請專利範圍第13項的方法, 人丄 J乃法,其中的混合溶液 含有1〜50%的HN〇3溶液。 1”申請專利範圍第12項的方法,其中第二乾飯刻 =含有服’…’知和⑽中的氣體來 進仃。 如申請專利範圍第16項的方 at. g . _ /去其中弟二乾蝕刻 步私疋破壞第一凹孔蝕刻面曰 4 ^日日格的電漿姓刻。 16
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050058570A KR100608386B1 (ko) | 2005-06-30 | 2005-06-30 | 반도체 소자의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI263307B true TWI263307B (en) | 2006-10-01 |
TW200701403A TW200701403A (en) | 2007-01-01 |
Family
ID=37184957
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094146561A TWI263307B (en) | 2005-06-30 | 2005-12-26 | A method of manufacturing semiconductor device having recess gate structure with varying recess width for increased channel length |
Country Status (5)
Country | Link |
---|---|
US (2) | US7413969B2 (zh) |
JP (1) | JP5127137B2 (zh) |
KR (1) | KR100608386B1 (zh) |
CN (1) | CN100463113C (zh) |
TW (1) | TWI263307B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8035160B2 (en) | 2006-11-13 | 2011-10-11 | Micron Technology, Inc. | Recessed access device for a memory |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100732767B1 (ko) * | 2005-12-29 | 2007-06-27 | 주식회사 하이닉스반도체 | 반도체 소자의 리세스 채널용 트렌치 형성방법 |
DE102006045441B4 (de) * | 2006-09-26 | 2008-09-25 | Infineon Technologies Austria Ag | Verfahren zur Herstellung einer Halbleiterbauelementanordnung mit einer Trenchtransistorstruktur |
KR100842908B1 (ko) * | 2006-09-30 | 2008-07-02 | 주식회사 하이닉스반도체 | 리세스 게이트를 갖는 반도체 소자 및 그의 제조방법 |
KR100840789B1 (ko) | 2007-02-05 | 2008-06-23 | 삼성전자주식회사 | 리세스 트랜지스터 및 그 제조 방법 |
KR100849189B1 (ko) | 2007-02-12 | 2008-07-30 | 주식회사 하이닉스반도체 | 리세스 게이트를 갖는 반도체 소자 및 그 제조 방법 |
JP2008210994A (ja) * | 2007-02-27 | 2008-09-11 | Nec Electronics Corp | 横型mosfetおよびその製造方法 |
KR100951566B1 (ko) | 2007-03-15 | 2010-04-09 | 주식회사 하이닉스반도체 | 리세스 게이트를 갖는 반도체 소자의 제조 방법 |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
KR100908522B1 (ko) | 2007-06-28 | 2009-07-20 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
DE102007045734B3 (de) * | 2007-09-25 | 2008-11-13 | Qimonda Ag | Verfahren zur Herstellung eines Integrierten Schaltkreises und damit hergestellter Integrierter Schaltkreis |
KR20090076317A (ko) * | 2008-01-08 | 2009-07-13 | 삼성전자주식회사 | 반도체 장치 및 그의 형성방법 |
CN101587908B (zh) * | 2008-05-23 | 2010-11-17 | 南亚科技股份有限公司 | 凹入式沟道晶体管结构 |
US9012318B2 (en) | 2012-09-21 | 2015-04-21 | Micron Technology, Inc. | Etching polysilicon |
KR101506888B1 (ko) * | 2013-10-02 | 2015-03-30 | 주식회사 에스앤에스텍 | 블랭크 마스크 및 포토마스크 |
US10008417B1 (en) * | 2017-06-12 | 2018-06-26 | International Business Machines Corporation | Vertical transport fin field effect transistors having different channel lengths |
CN107464749B (zh) * | 2017-07-28 | 2021-09-17 | 北京北方华创微电子装备有限公司 | 蚀刻方法和蚀刻系统 |
CN112885770A (zh) * | 2019-11-29 | 2021-06-01 | 长鑫存储技术有限公司 | 浅沟槽隔离结构、半导体结构及其制备方法 |
CN112864155B (zh) * | 2021-01-04 | 2022-05-03 | 长鑫存储技术有限公司 | 半导体结构的制造方法及半导体结构 |
CN113892176A (zh) * | 2021-08-31 | 2022-01-04 | 长江存储科技有限责任公司 | 半导体结构、制作方法及三维存储器 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58202560A (ja) * | 1982-05-21 | 1983-11-25 | Hitachi Ltd | 半導体装置およびその製造方法 |
JPH02294031A (ja) * | 1989-05-09 | 1990-12-05 | Matsushita Electron Corp | トレンチ形成方法 |
DE69233314T2 (de) * | 1991-10-11 | 2005-03-24 | Canon K.K. | Verfahren zur Herstellung von Halbleiter-Produkten |
JP3353532B2 (ja) * | 1995-04-13 | 2002-12-03 | ソニー株式会社 | トレンチエッチング方法 |
US5880004A (en) * | 1997-06-10 | 1999-03-09 | Winbond Electronics Corp. | Trench isolation process |
JPH11111837A (ja) | 1997-10-03 | 1999-04-23 | Toyota Central Res & Dev Lab Inc | 半導体装置の製造方法 |
KR100275484B1 (ko) * | 1998-10-23 | 2001-01-15 | 정선종 | 트렌치형 게이트 전극을 갖는 전력소자 제조방법 |
JP2000208606A (ja) * | 1999-01-11 | 2000-07-28 | Nec Corp | 半導体装置及びその製造方法 |
KR100282452B1 (ko) * | 1999-03-18 | 2001-02-15 | 김영환 | 반도체 소자 및 그의 제조 방법 |
JP2001277488A (ja) * | 2000-03-30 | 2001-10-09 | Fuji Photo Film Co Ltd | インクジェット記録方法 |
US20020063282A1 (en) | 2000-11-29 | 2002-05-30 | Chiu-Te Lee | Buried transistor for a liquid crystal display system |
KR100433091B1 (ko) * | 2001-10-23 | 2004-05-28 | 주식회사 하이닉스반도체 | 반도체소자의 도전배선 형성방법 |
JP2005528796A (ja) | 2002-05-31 | 2005-09-22 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | トレンチ・ゲート半導体装置と製造方法 |
JP3870292B2 (ja) * | 2002-12-10 | 2007-01-17 | 関東化学株式会社 | エッチング液組成物とそれを用いた反射板の製造方法 |
US7326619B2 (en) * | 2003-08-20 | 2008-02-05 | Samsung Electronics Co., Ltd. | Method of manufacturing integrated circuit device including recessed channel transistor |
KR100505712B1 (ko) * | 2003-10-22 | 2005-08-02 | 삼성전자주식회사 | 리세스 채널 어레이 트랜지스터의 제조 방법 |
KR100532509B1 (ko) * | 2004-03-26 | 2005-11-30 | 삼성전자주식회사 | SiGe를 이용한 트렌치 커패시터 및 그 형성방법 |
US7326629B2 (en) * | 2004-09-10 | 2008-02-05 | Agency For Science, Technology And Research | Method of stacking thin substrates by transfer bonding |
KR100840789B1 (ko) * | 2007-02-05 | 2008-06-23 | 삼성전자주식회사 | 리세스 트랜지스터 및 그 제조 방법 |
-
2005
- 2005-06-30 KR KR1020050058570A patent/KR100608386B1/ko not_active IP Right Cessation
- 2005-12-26 TW TW094146561A patent/TWI263307B/zh not_active IP Right Cessation
- 2005-12-27 US US11/318,960 patent/US7413969B2/en active Active
- 2005-12-28 JP JP2005378696A patent/JP5127137B2/ja not_active Expired - Fee Related
-
2006
- 2006-02-27 CN CNB2006100549508A patent/CN100463113C/zh not_active Expired - Fee Related
-
2008
- 2008-07-17 US US12/174,735 patent/US20080272431A1/en not_active Abandoned
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8035160B2 (en) | 2006-11-13 | 2011-10-11 | Micron Technology, Inc. | Recessed access device for a memory |
US8319280B2 (en) | 2006-11-13 | 2012-11-27 | Micron Technology, Inc. | Recessed access device for a memory |
US8541836B2 (en) | 2006-11-13 | 2013-09-24 | Micron Technology, Inc. | Recessed access device for a memory |
Also Published As
Publication number | Publication date |
---|---|
CN1892988A (zh) | 2007-01-10 |
CN100463113C (zh) | 2009-02-18 |
KR100608386B1 (ko) | 2006-08-08 |
JP2007013085A (ja) | 2007-01-18 |
JP5127137B2 (ja) | 2013-01-23 |
TW200701403A (en) | 2007-01-01 |
US20070004145A1 (en) | 2007-01-04 |
US20080272431A1 (en) | 2008-11-06 |
US7413969B2 (en) | 2008-08-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI263307B (en) | A method of manufacturing semiconductor device having recess gate structure with varying recess width for increased channel length | |
TWI220063B (en) | Method for limiting divot formation in post shallow trench isolation processes | |
US20060065939A1 (en) | Metal gate electrode semiconductor device | |
US7459382B2 (en) | Field effect device with reduced thickness gate | |
JP2010533978A (ja) | バルク基板上に作製される分離トライゲートトランジスタ | |
TW200531210A (en) | Simiconductor device with shallow trench isolation and its manufacture method | |
TW201017776A (en) | Method for making a semiconductor device | |
JP2007123898A (ja) | チップ、fet製造方法(誘電体ストレッサ要素を有するトランジスタ) | |
TW200945583A (en) | Semiconductor device and method of manufacturing the same | |
TWI336948B (en) | Method for fabricating a recessed-gate mos transistor device | |
JP2007123896A (ja) | チップ、fet製造方法(面内剪断応力を加えるための誘電体ストレッサ要素を有するトランジスタ) | |
US20090020798A1 (en) | Transistor structure and method of making the same | |
JP5914865B2 (ja) | 半導体装置 | |
US6979867B2 (en) | SOI chip with mesa isolation and recess resistant regions | |
TWI254351B (en) | Manufacturing method for gate dielectric layer | |
JP3923218B2 (ja) | 半導体装置の製造方法 | |
CN107591399B (zh) | 半导体结构及其形成方法 | |
TWI236065B (en) | Method for providing an integrated active region on silicon-on-insulator devices | |
TWI299202B (en) | Methods of etching nickel silicide and cobalt silicide and methods of forming conductive lines | |
US20210057283A1 (en) | Method for manufacturing microelectronic components | |
TWI296826B (en) | Method for manufacturing semiconductor device | |
TWI814794B (zh) | 形成半導體裝置的方法 | |
US7148108B2 (en) | Method of manufacturing semiconductor device having step gate | |
TW200903654A (en) | Method of forming a gate oxide layer | |
TWI258844B (en) | Method for manufacturing flash device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |