JP2007012854A - 半導体チップ及びその製造方法 - Google Patents
半導体チップ及びその製造方法 Download PDFInfo
- Publication number
- JP2007012854A JP2007012854A JP2005191407A JP2005191407A JP2007012854A JP 2007012854 A JP2007012854 A JP 2007012854A JP 2005191407 A JP2005191407 A JP 2005191407A JP 2005191407 A JP2005191407 A JP 2005191407A JP 2007012854 A JP2007012854 A JP 2007012854A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- semiconductor chip
- wiring pattern
- hole
- external connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
【解決手段】 半導体基板11と、半導体基板11を貫通する貫通孔17に設けられた貫通ビア12と、半導体基板11上に積層された絶縁層21−1〜21−3、第1の配線パターン22、及び第2の配線パターン23を備えた多層配線構造体14と、多層配線構造体14の最上層に設けられた外部接続端子15とを有し、第2の配線パターン23により貫通ビア12と外部接続端子15との間を電気的に接続した。
【選択図】 図7
Description
11 半導体基板
11A 表面
11B 裏面
12,52 貫通ビア
13,18 絶縁膜
13A,32A,34A,34B,35A,35B,36A,56A 開口部
14 多層配線構造体
15 外部接続端子
16 保護膜
17,51 貫通孔
21−1〜21−3 絶縁層
22 第1の配線パターン
23,53 第2の配線パターン
25,29 配線
26,28A〜28C ビア
32,34,36,56 レジスト膜
33 シード層
M1 厚さ
R1,R2 直径
Claims (4)
- 半導体基板と、
前記半導体基板上に積層された複数の絶縁層と、該複数の絶縁層に設けられた第1の配線パターンとを備えた多層配線構造体と、
前記多層配線構造体の最上層に外部接続端子とを有する半導体チップにおいて、
前記半導体基板を貫通する貫通孔に貫通ビアを設け、
前記複数の絶縁層に貫通ビアと外部接続端子との間を電気的に接続する第2の配線パターンを設けたことを特徴とする半導体チップ。 - 前記第2の配線パターンは、複数のビア及び配線を有し、
前記貫通ビアを外部接続端子の略直下に位置する半導体基板に設け、
前記複数のビアは、貫通ビアと外部接続端子との間に位置する複数の絶縁層に、半導体基板の面と略直交するように配置されていることを特徴とする請求項1に記載の半導体チップ。 - 半導体基板と、該半導体基板上に積層された複数の絶縁層と該複数の絶縁層に設けられた第1の配線パターンとを備えた多層配線構造体と、該多層配線構造体の最上層に設けられた外部接続端子と、該半導体基板を貫通する貫通孔に設けられた貫通ビアと、該複数の絶縁層に貫通ビアと外部接続端子との間を電気的に接続する第2の配線パターンとを有する半導体チップの製造方法であって、
前記半導体基板上に、前記第1の配線パターンと第2の配線パターンとを同時に形成する第1及び第2の配線パターン形成工程と、
前記半導体基板に前記第2の配線パターンを露出する貫通孔を形成する貫通孔形成工程と、
前記貫通孔の側面に絶縁膜を形成する絶縁膜形成工程と、
前記絶縁膜が形成された貫通孔に前記貫通ビアを形成する貫通ビア形成工程とを設けたことを特徴とする半導体チップの製造方法。 - 前記貫通孔形成工程の前に、前記半導体基板を薄板化する半導体基板薄板化工程をさらに設けたことを特徴とする半導体チップの製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005191407A JP4250154B2 (ja) | 2005-06-30 | 2005-06-30 | 半導体チップ及びその製造方法 |
KR1020060058088A KR101178823B1 (ko) | 2005-06-30 | 2006-06-27 | 반도체 칩 및 그 제조 방법 |
US11/427,562 US7843068B2 (en) | 2005-06-30 | 2006-06-29 | Semiconductor chip and method of manufacturing the same |
EP06013661A EP1739747A3 (en) | 2005-06-30 | 2006-06-30 | Semiconductor chip and method of manufacturing the same |
US12/901,028 US8338289B2 (en) | 2005-06-30 | 2010-10-08 | Method of manufacturing a semiconductor chip including a semiconductor substrate and a through via provided in a through hole |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005191407A JP4250154B2 (ja) | 2005-06-30 | 2005-06-30 | 半導体チップ及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007012854A true JP2007012854A (ja) | 2007-01-18 |
JP4250154B2 JP4250154B2 (ja) | 2009-04-08 |
Family
ID=37054435
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005191407A Active JP4250154B2 (ja) | 2005-06-30 | 2005-06-30 | 半導体チップ及びその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7843068B2 (ja) |
EP (1) | EP1739747A3 (ja) |
JP (1) | JP4250154B2 (ja) |
KR (1) | KR101178823B1 (ja) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008210952A (ja) * | 2007-02-26 | 2008-09-11 | Sanyo Electric Co Ltd | 半導体装置の製造方法、シリコンインターポーザの製造方法および半導体モジュールの製造方法 |
JP2010166052A (ja) * | 2009-01-13 | 2010-07-29 | Taiwan Semiconductor Manufacturing Co Ltd | 低k誘電体ライナーを有するシリコン貫通ビア |
JP2010205921A (ja) * | 2009-03-03 | 2010-09-16 | Olympus Corp | 半導体装置および半導体装置の製造方法 |
JP2010232400A (ja) * | 2009-03-27 | 2010-10-14 | Panasonic Corp | 半導体基板と半導体基板の製造方法および半導体パッケージ |
JP2011171567A (ja) * | 2010-02-19 | 2011-09-01 | Elpida Memory Inc | 基板構造物の製造方法及び半導体装置の製造方法 |
JP2012222161A (ja) * | 2011-04-08 | 2012-11-12 | Elpida Memory Inc | 半導体装置 |
US8436448B2 (en) | 2008-12-31 | 2013-05-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via with air gap |
US8513058B2 (en) | 2010-02-03 | 2013-08-20 | Renesas Electronics Corporation | Semiconductor device and method for producing the same |
WO2013145043A1 (ja) * | 2012-03-27 | 2013-10-03 | パナソニック株式会社 | ビルドアップ基板およびその製造方法ならびに半導体集積回路パッケージ |
JP2013251511A (ja) * | 2012-06-04 | 2013-12-12 | Macronix Internatl Co Ltd | 3d積層マルチチップモジュールの製造方法 |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4809308B2 (ja) * | 2007-09-21 | 2011-11-09 | 新光電気工業株式会社 | 基板の製造方法 |
KR101374338B1 (ko) | 2007-11-14 | 2014-03-14 | 삼성전자주식회사 | 관통 전극을 갖는 반도체 장치 및 그 제조방법 |
JP2009224492A (ja) * | 2008-03-14 | 2009-10-01 | Oki Semiconductor Co Ltd | 半導体装置及びその製造方法 |
KR101458958B1 (ko) * | 2008-06-10 | 2014-11-13 | 삼성전자주식회사 | 반도체 칩, 반도체 패키지 및 반도체 칩의 제조 방법 |
US8227889B2 (en) * | 2008-12-08 | 2012-07-24 | United Microelectronics Corp. | Semiconductor device |
JP5412316B2 (ja) * | 2010-02-23 | 2014-02-12 | パナソニック株式会社 | 半導体装置、積層型半導体装置及び半導体装置の製造方法 |
JP2011238742A (ja) * | 2010-05-10 | 2011-11-24 | Shinko Electric Ind Co Ltd | 配線基板の製造方法及び配線基板 |
US8338294B2 (en) * | 2011-03-31 | 2012-12-25 | Soitec | Methods of forming bonded semiconductor structures including two or more processed semiconductor structures carried by a common substrate, and semiconductor structures formed by such methods |
US20120248621A1 (en) * | 2011-03-31 | 2012-10-04 | S.O.I.Tec Silicon On Insulator Technologies | Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods |
US8587127B2 (en) * | 2011-06-15 | 2013-11-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures and methods of forming the same |
US9111998B2 (en) | 2012-04-04 | 2015-08-18 | Samsung Electronics Co., Ltd | Multi-level stack having multi-level contact and method |
US9287162B2 (en) | 2013-01-10 | 2016-03-15 | Samsung Austin Semiconductor, L.P. | Forming vias and trenches for self-aligned contacts in a semiconductor structure |
JP6120964B2 (ja) * | 2013-07-05 | 2017-04-26 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
KR102094473B1 (ko) | 2013-10-15 | 2020-03-27 | 삼성전자주식회사 | Tsv 구조를 구비한 집적회로 소자 및 그 제조 방법 |
JP2016058628A (ja) * | 2014-09-11 | 2016-04-21 | 株式会社東芝 | 半導体装置、及び半導体装置の製造方法 |
JP2017009704A (ja) * | 2015-06-18 | 2017-01-12 | キヤノン株式会社 | 多層膜を用いた光学素子、光学系および光学機器 |
KR20210120399A (ko) | 2020-03-26 | 2021-10-07 | 삼성전자주식회사 | 관통 실리콘 비아를 포함하는 집적 회로 반도체 소자 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6423564A (en) | 1987-07-17 | 1989-01-26 | Sharp Kk | Space type semiconductor device |
JPH0533645Y2 (ja) | 1987-07-31 | 1993-08-26 | ||
JPH0529483A (ja) | 1991-07-19 | 1993-02-05 | Rohm Co Ltd | 半導体集積装置 |
JPH0964050A (ja) | 1995-08-29 | 1997-03-07 | Hitachi Ltd | 半導体素子およびその製造方法 |
JP3184493B2 (ja) | 1997-10-01 | 2001-07-09 | 松下電子工業株式会社 | 電子装置の製造方法 |
JP3563604B2 (ja) * | 1998-07-29 | 2004-09-08 | 株式会社東芝 | マルチチップ半導体装置及びメモリカード |
JP3726579B2 (ja) | 1999-08-20 | 2005-12-14 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
US6882045B2 (en) | 1999-10-28 | 2005-04-19 | Thomas J. Massingill | Multi-chip module and method for forming and method for deplating defective capacitors |
JP3779524B2 (ja) * | 2000-04-20 | 2006-05-31 | 株式会社東芝 | マルチチップ半導体装置及びメモリカード |
JP4123682B2 (ja) | 2000-05-16 | 2008-07-23 | セイコーエプソン株式会社 | 半導体装置及びその製造方法 |
US6444576B1 (en) | 2000-06-16 | 2002-09-03 | Chartered Semiconductor Manufacturing, Ltd. | Three dimensional IC package module |
KR100364635B1 (ko) * | 2001-02-09 | 2002-12-16 | 삼성전자 주식회사 | 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법 |
US6495912B1 (en) * | 2001-09-17 | 2002-12-17 | Megic Corporation | Structure of ceramic package with integrated passive devices |
EP1351288B1 (en) * | 2002-04-05 | 2015-10-28 | STMicroelectronics Srl | Process for manufacturing an insulated interconnection through a body of semiconductor material and corresponding semiconductor device |
US7030481B2 (en) * | 2002-12-09 | 2006-04-18 | Internation Business Machines Corporation | High density chip carrier with integrated passive devices |
JP4327644B2 (ja) | 2004-03-31 | 2009-09-09 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2007250561A (ja) | 2004-04-12 | 2007-09-27 | Japan Science & Technology Agency | 半導体素子および半導体システム |
JPWO2005101476A1 (ja) | 2004-04-16 | 2008-03-06 | 独立行政法人科学技術振興機構 | 半導体素子及び半導体素子の製造方法 |
JP3897036B2 (ja) | 2004-07-27 | 2007-03-22 | 株式会社ザイキューブ | 半導体集積回路装置およびその製造方法 |
JP5354765B2 (ja) | 2004-08-20 | 2013-11-27 | カミヤチョウ アイピー ホールディングス | 三次元積層構造を持つ半導体装置の製造方法 |
-
2005
- 2005-06-30 JP JP2005191407A patent/JP4250154B2/ja active Active
-
2006
- 2006-06-27 KR KR1020060058088A patent/KR101178823B1/ko active IP Right Grant
- 2006-06-29 US US11/427,562 patent/US7843068B2/en active Active
- 2006-06-30 EP EP06013661A patent/EP1739747A3/en not_active Withdrawn
-
2010
- 2010-10-08 US US12/901,028 patent/US8338289B2/en active Active
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008210952A (ja) * | 2007-02-26 | 2008-09-11 | Sanyo Electric Co Ltd | 半導体装置の製造方法、シリコンインターポーザの製造方法および半導体モジュールの製造方法 |
US8436448B2 (en) | 2008-12-31 | 2013-05-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via with air gap |
JP2010166052A (ja) * | 2009-01-13 | 2010-07-29 | Taiwan Semiconductor Manufacturing Co Ltd | 低k誘電体ライナーを有するシリコン貫通ビア |
US11600551B2 (en) | 2009-01-13 | 2023-03-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via with low-K dielectric liner |
US10707149B2 (en) | 2009-01-13 | 2020-07-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via with low-K dielectric liner |
US8399354B2 (en) | 2009-01-13 | 2013-03-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via with low-K dielectric liner |
US9064940B2 (en) | 2009-01-13 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via with low-K dielectric liner |
US8890322B2 (en) | 2009-03-03 | 2014-11-18 | Olympus Corporation | Semiconductor apparatus and method of manufacturing semiconductor apparatus |
JP2010205921A (ja) * | 2009-03-03 | 2010-09-16 | Olympus Corp | 半導体装置および半導体装置の製造方法 |
JP2010232400A (ja) * | 2009-03-27 | 2010-10-14 | Panasonic Corp | 半導体基板と半導体基板の製造方法および半導体パッケージ |
US8513058B2 (en) | 2010-02-03 | 2013-08-20 | Renesas Electronics Corporation | Semiconductor device and method for producing the same |
JP2011171567A (ja) * | 2010-02-19 | 2011-09-01 | Elpida Memory Inc | 基板構造物の製造方法及び半導体装置の製造方法 |
JP2012222161A (ja) * | 2011-04-08 | 2012-11-12 | Elpida Memory Inc | 半導体装置 |
WO2013145043A1 (ja) * | 2012-03-27 | 2013-10-03 | パナソニック株式会社 | ビルドアップ基板およびその製造方法ならびに半導体集積回路パッケージ |
JPWO2013145043A1 (ja) * | 2012-03-27 | 2015-08-03 | パナソニックIpマネジメント株式会社 | ビルドアップ基板およびその製造方法ならびに半導体集積回路パッケージ |
US9236338B2 (en) | 2012-03-27 | 2016-01-12 | Panasonic Intellectual Property Management Co., Ltd. | Built-up substrate, method for manufacturing same, and semiconductor integrated circuit package |
JP2013251511A (ja) * | 2012-06-04 | 2013-12-12 | Macronix Internatl Co Ltd | 3d積層マルチチップモジュールの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20070003591A (ko) | 2007-01-05 |
KR101178823B1 (ko) | 2012-09-03 |
EP1739747A2 (en) | 2007-01-03 |
US8338289B2 (en) | 2012-12-25 |
US7843068B2 (en) | 2010-11-30 |
JP4250154B2 (ja) | 2009-04-08 |
EP1739747A3 (en) | 2007-08-01 |
US20110027990A1 (en) | 2011-02-03 |
US20070001312A1 (en) | 2007-01-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4250154B2 (ja) | 半導体チップ及びその製造方法 | |
US7830018B2 (en) | Partitioned through-layer via and associated systems and methods | |
KR100641696B1 (ko) | 반도체 장치 제조방법 | |
JP5222459B2 (ja) | 半導体チップの製造方法、マルチチップパッケージ | |
JP4716819B2 (ja) | インターポーザの製造方法 | |
JP5596919B2 (ja) | 半導体装置の製造方法 | |
JP2009027174A (ja) | システムインパッケージ及びその製造方法 | |
US20110283535A1 (en) | Wiring board and method of manufacturing the same | |
KR20170009128A (ko) | 회로 기판 및 그 제조 방법 | |
US8129835B2 (en) | Package substrate having semiconductor component embedded therein and fabrication method thereof | |
JP2009272490A (ja) | 半導体装置および半導体装置の製造方法 | |
JP2011142291A (ja) | 半導体パッケージ及び半導体パッケージの製造方法 | |
JP5119623B2 (ja) | インターポーザ基板の製造方法 | |
US8519524B1 (en) | Chip stacking structure and fabricating method of the chip stacking structure | |
US20140042122A1 (en) | Method of manufacturing printed circuit board | |
TWI662662B (zh) | 晶片封裝結構及其製造方法 | |
EP1768177B1 (en) | Method of manufacturing semiconductor chip | |
JP2010141164A (ja) | 多層配線基板の製造方法 | |
JP2006049557A (ja) | 半導体装置 | |
JP7077005B2 (ja) | 配線基板及びその製造方法 | |
JP5834563B2 (ja) | 半導体装置の製造方法 | |
TW201611695A (zh) | 無核心層封裝基板與其製造方法 | |
JP6112857B2 (ja) | 配線基板及びその製造方法 | |
JP2011238742A (ja) | 配線基板の製造方法及び配線基板 | |
JP4580752B2 (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080213 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080826 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080828 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20081014 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20081104 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20081212 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090113 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090116 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120123 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4250154 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120123 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130123 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130123 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140123 Year of fee payment: 5 |