JP2006270044A - フラッシュメモリ素子の製造方法 - Google Patents
フラッシュメモリ素子の製造方法 Download PDFInfo
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- JP2006270044A JP2006270044A JP2005357154A JP2005357154A JP2006270044A JP 2006270044 A JP2006270044 A JP 2006270044A JP 2005357154 A JP2005357154 A JP 2005357154A JP 2005357154 A JP2005357154 A JP 2005357154A JP 2006270044 A JP2006270044 A JP 2006270044A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000005468 ion implantation Methods 0.000 claims abstract description 53
- 150000002500 ions Chemical class 0.000 claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 19
- 229910052796 boron Inorganic materials 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 12
- 239000007943 implant Substances 0.000 abstract 1
- 230000001939 inductive effect Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 238000005530 etching Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- -1 boron ions Chemical class 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000010405 reoxidation reaction Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61C—DENTISTRY; APPARATUS OR METHODS FOR ORAL OR DENTAL HYGIENE
- A61C19/00—Dental auxiliary appliances
- A61C19/02—Protective casings, e.g. boxes for instruments; Bags
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61C—DENTISTRY; APPARATUS OR METHODS FOR ORAL OR DENTAL HYGIENE
- A61C5/00—Filling or capping teeth
- A61C5/40—Implements for surgical treatment of the roots or nerves of the teeth; Nerve needles; Methods or instruments for medication of the roots
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
Abstract
【解決手段】高電圧PMOSトランジスタ領域および低電圧素子領域を有する半導体基板上に多数のゲートを形成する段階と、前記高電圧PMOSトランジスタ領域のゲート両側半導体基板内に低濃度p型イオン注入領域を形成する段階と、前記高電圧PMOSトランジスタ領域に高濃度BF2イオンを注入して前記低濃度p型イオン注入領域内に高濃度p型イオン注入領域を形成する段階と、前記高電圧PMOSトランジスタ領域および低電圧素子領域に低濃度のn型不純物イオンを注入する段階とを含む。
【選択図】図2
Description
21 ゲート
22 再酸化膜
23 低濃度p型イオン注入領域
24 低濃度n型イオン注入領域
25 高濃度p型イオン注入領域
Claims (8)
- (a)高電圧PMOSトランジスタ領域および低電圧素子領域を有する半導体基板上に多数のゲートを形成する段階と、
(b)前記高電圧PMOSトランジスタ領域のゲート両側半導体基板内に低濃度p型イオン注入領域を形成する段階と、
(c)前記高電圧PMOSトランジスタ領域に高濃度BF2イオンを注入して前記低濃度p型イオン注入領域内に高濃度p型イオン注入領域を形成する段階と、
(d)前記高電圧PMOSトランジスタ領域および前記低電圧素子領域に低濃度のn型不純物イオンを注入する段階とを含むことを特徴とするフラッシュメモリ素子の製造方法。 - 前記(b)段階および前記(c)段階は、前記高電圧PMOSトランジスタ領域をオープンするマスクを形成する段階と、
前記マスクを用いて低濃度p型イオンを注入して前記高電圧PMOSトランジスタ領域のゲート両側半導体基板内に低濃度p型イオン注入領域を形成する段階と、
前記マスクを用いて高濃度BF2イオンを注入して前記低濃度p型イオン注入領域内に高濃度p型イオン注入領域を形成する段階と、
前記マスクを除去する段階とを含んでなることを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。 - 前記低濃度p型イオンとして、2.0E12〜8.0E12ions/cm2の濃度を持つB11イオンを使用することを特徴とする請求項2に記載のフラッシュメモリ素子の製造方法。
- 前記低濃度p型イオン注入の際に、イオン注入エネルギーは25〜50KeVであることを特徴とする請求項2に記載のフラッシュメモリ素子の製造方法。
- 前記(c)段階で注入された高濃度BF2イオンのフッ素(F)成分の外方拡散現象によってボロン(B)成分の半導体基板の下部への拡散が抑制されるため、前記高濃度P型イオン注入領域は半導体基板の表面から下部に行くほど低い濃度を持つことを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。
- (a)高電圧PMOSトランジスタ領域および低電圧素子領域を有する半導体基板上に多数のゲートを形成する段階と、
(b)前記高電圧PMOSトランジスタ領域のゲート両側半導体基板内に低濃度p型イオン注入領域を形成する段階と、
(c)前記高電圧PMOSトランジスタ領域および前記低電圧素子領域に低濃度n型不純物イオンを注入する段階と、
(d)前記高電圧PMOSトランジスタ領域に高濃度BF2イオンを注入して前記低濃度p型イオン注入領域内に高濃度p型イオン注入領域を形成する段階とを含むことを特徴とするフラッシュメモリ素子の製造方法。 - 前記(b)段階は、前記高電圧PMOSトランジスタ領域をオープンするマスクを形成する段階と、
前記マスクを用いて低濃度p型イオンを注入して前記高電圧PMOSトランジスタ領域のゲート両側半導体基板内に低濃度p型イオン注入領域を形成する段階と、
前記マスクを除去する段階とを含んでなることを特徴とする請求項6に記載のフラッシュメモリ素子の製造方法。 - 前記(d)段階は、前記高電圧PMOSトランジスタ領域をオープンするマスクを形成する段階と、
前記マスクを用いて高濃度BF2イオンを注入して前記低濃度p型イオン注入領域内に高濃度p型イオン注入領域を形成する段階と、
前記マスクを除去する段階とを含んでなることを特徴とする請求項6に記載のフラッシュメモリ素子の製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050023471A KR100624912B1 (ko) | 2005-03-22 | 2005-03-22 | 플래쉬 메모리 소자의 제조방법 |
Publications (1)
Publication Number | Publication Date |
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JP2006270044A true JP2006270044A (ja) | 2006-10-05 |
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JP2005357154A Pending JP2006270044A (ja) | 2005-03-22 | 2005-12-12 | フラッシュメモリ素子の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7384844B2 (ja) |
JP (1) | JP2006270044A (ja) |
KR (1) | KR100624912B1 (ja) |
CN (1) | CN100431138C (ja) |
TW (1) | TWI286369B (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1930663A (zh) * | 2004-03-15 | 2007-03-14 | 皇家飞利浦电子股份有限公司 | 制造半导体器件的方法和用这种方法获得的半导体器件 |
KR100816755B1 (ko) | 2006-10-19 | 2008-03-25 | 삼성전자주식회사 | 플래시 메모리 장치 및 그 제조방법 |
US8026544B2 (en) | 2009-03-30 | 2011-09-27 | Sandisk Technologies Inc. | Fabricating and operating a memory array having a multi-level cell region and a single-level cell region |
CN104347501B (zh) * | 2013-08-07 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
US11018259B2 (en) * | 2015-12-17 | 2021-05-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device comprising gate structure and doped gate spacer |
CN108109908B (zh) * | 2016-11-25 | 2021-02-26 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法 |
CN110797342B (zh) * | 2019-10-17 | 2022-05-27 | 上海华力集成电路制造有限公司 | 存储器件的制造方法及该存储器件 |
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JPH0774355A (ja) * | 1993-08-31 | 1995-03-17 | Nec Corp | 半導体装置及びその製造方法 |
JPH08107156A (ja) * | 1994-10-05 | 1996-04-23 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置の製造方法 |
JPH10189973A (ja) * | 1996-12-19 | 1998-07-21 | Lsi Logic Corp | カウンタ及び非カウンタ・ドーパント要素を用いて形成されたldd領域を有する電界効果トランジスタ |
JP2000299390A (ja) * | 1999-04-16 | 2000-10-24 | Nec Corp | 半導体装置及びその製造方法 |
JP2001085533A (ja) * | 1999-09-14 | 2001-03-30 | Denso Corp | 半導体装置及びその製造方法 |
JP2002043436A (ja) * | 2000-07-28 | 2002-02-08 | Denso Corp | 半導体装置の製造方法 |
JP2002118177A (ja) * | 2000-10-11 | 2002-04-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2003051552A (ja) * | 2001-08-03 | 2003-02-21 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JP2005012227A (ja) * | 2003-06-20 | 2005-01-13 | Samsung Electronics Co Ltd | 不揮発性メモリが内蔵された単一チップデータ処理装置及びその製造方法 |
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-
2005
- 2005-03-22 KR KR1020050023471A patent/KR100624912B1/ko not_active IP Right Cessation
- 2005-12-07 US US11/297,147 patent/US7384844B2/en not_active Expired - Fee Related
- 2005-12-12 JP JP2005357154A patent/JP2006270044A/ja active Pending
- 2005-12-23 TW TW094146419A patent/TWI286369B/zh not_active IP Right Cessation
-
2006
- 2006-02-27 CN CNB2006100549546A patent/CN100431138C/zh not_active Expired - Fee Related
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH06334134A (ja) * | 1992-06-01 | 1994-12-02 | Seiko Instr & Electron Ltd | 半導体装置の製造方法 |
JPH0774355A (ja) * | 1993-08-31 | 1995-03-17 | Nec Corp | 半導体装置及びその製造方法 |
JPH08107156A (ja) * | 1994-10-05 | 1996-04-23 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置の製造方法 |
JPH10189973A (ja) * | 1996-12-19 | 1998-07-21 | Lsi Logic Corp | カウンタ及び非カウンタ・ドーパント要素を用いて形成されたldd領域を有する電界効果トランジスタ |
JP2000299390A (ja) * | 1999-04-16 | 2000-10-24 | Nec Corp | 半導体装置及びその製造方法 |
JP2001085533A (ja) * | 1999-09-14 | 2001-03-30 | Denso Corp | 半導体装置及びその製造方法 |
JP2002043436A (ja) * | 2000-07-28 | 2002-02-08 | Denso Corp | 半導体装置の製造方法 |
JP2002118177A (ja) * | 2000-10-11 | 2002-04-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2003051552A (ja) * | 2001-08-03 | 2003-02-21 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JP2005012227A (ja) * | 2003-06-20 | 2005-01-13 | Samsung Electronics Co Ltd | 不揮発性メモリが内蔵された単一チップデータ処理装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR100624912B1 (ko) | 2006-09-19 |
US7384844B2 (en) | 2008-06-10 |
TW200634996A (en) | 2006-10-01 |
US20060223264A1 (en) | 2006-10-05 |
CN100431138C (zh) | 2008-11-05 |
CN1841708A (zh) | 2006-10-04 |
TWI286369B (en) | 2007-09-01 |
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