JP2006173468A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2006173468A JP2006173468A JP2004366215A JP2004366215A JP2006173468A JP 2006173468 A JP2006173468 A JP 2006173468A JP 2004366215 A JP2004366215 A JP 2004366215A JP 2004366215 A JP2004366215 A JP 2004366215A JP 2006173468 A JP2006173468 A JP 2006173468A
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- 239000004065 semiconductor Substances 0.000 title claims description 61
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 158
- 238000002955 isolation Methods 0.000 claims abstract description 30
- 239000000463 material Substances 0.000 claims description 84
- 230000004888 barrier function Effects 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 37
- 229910052751 metal Inorganic materials 0.000 claims description 37
- 239000000470 constituent Substances 0.000 claims description 28
- 239000013256 coordination polymer Substances 0.000 abstract description 56
- 238000011156 evaluation Methods 0.000 description 15
- 230000000694 effects Effects 0.000 description 12
- 238000004088 simulation Methods 0.000 description 12
- 230000007423 decrease Effects 0.000 description 10
- 238000000034 method Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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Abstract
【解決手段】素子分離領域ISにより区画されて配置されたnチャネルトランジスタQnの形成領域とpチャネルトランジスタQpの形成領域とを有し、nチャネルトランジスタQnの形成領域においてそのコンタクトプラグCPに起因する応力とpチャネルトランジスタQpの形成領域においてそのコンタクトプラグCPに起因する応力とが互いに異なる状態に構成されている。この構成により、活性領域A、素子分離領域ISの寸法を変更することなく、nチャネルトランジスタQnとpチャネルトランジスタQpの駆動電流をともに増加させることができる。
【選択図】図7
Description
本発明の原理について図面を参照しながら説明する。
以下、本発明の実施の形態1について図面を参照しながら説明する。
図8(a)は本発明の実施の形態2における半導体装置の拡大平面図、図8(b)はその断面図である。
図9(a)は本発明の実施の形態3における半導体装置の拡大平面図、図9(b)はその断面図である。
図10(a)は本発明の実施の形態4における半導体装置の拡大平面図、図10(b)はその断面図である。
図11(a)は本発明の実施の形態5における半導体装置の拡大平面図、図11(b)はその断面図である。
図12(a)は本発明の実施の形態6における半導体装置の拡大平面図、図12(b)はその断面図である。また、図12(c)は図12(b)のコンタクトプラグの底部拡大図である。
図13(a)は本発明の実施の形態7における半導体装置の拡大平面図、図13(b)はその断面図である。
図14(a)は本発明の実施の形態8における半導体装置の拡大平面図、図14(b)はその断面図である。
11 エンコーダ部
12 ROM部
13 メモリ部
14 入出力(I/O)部
20 素子分離領域
Qn nチャネルトランジスタ
Qp pチャネルトランジスタ
A 活性領域
BM バリアメタル
CP コンタクトプラグ
Cn,Cp チャネル領域
En,Ep エクステンション領域
ES エッチストップ膜
G ゲート電極
IS 素子分離領域
SP 層間膜
Su シリコン基板
SW サイドウォール
P1 シミュレーション評価箇所(コンタクト直下)
P2 シミュレーション評価箇所(サイドウォール直下)
P3 シミュレーション評価箇所(ゲート電極下)
d サイドウォールとコンタクトプラグ間の距離
S コンタクトプラグ起因の応力により影響を受ける範囲
Claims (23)
- 素子分離領域により区画されて配置されたnチャネルトランジスタ形成領域とpチャネルトランジスタ形成領域とを有し、前記nチャネルトランジスタ形成領域においてそのコンタクトプラグに起因する応力と前記pチャネルトランジスタ形成領域においてそのコンタクトプラグに起因する応力とが互いに異なる状態に構成されている半導体装置。
- 前記nチャネルトランジスタ形成領域における応力と前記pチャネルトランジスタ形成領域における応力との相違が、単位面積当たりのコンタクトプラグ数の相違によるものである請求項1に記載の半導体装置。
- 前記コンタクトプラグの構成材料は圧縮応力を持つ材料であって、前記nチャネルトランジスタ形成領域の単位面積当たりのコンタクトプラグ数は相対的に少なく、前記pチャネルトランジスタ形成領域の単位面積当たりのコンタクトプラグ数は相対的に多い請求項2に記載の半導体装置。
- 前記コンタクトプラグの構成材料は引張応力を持つ材料であって、前記nチャネルトランジスタ形成領域の単位面積当たりのコンタクトプラグ数は相対的に多く、前記pチャネルトランジスタ形成領域の単位面積当たりのコンタクトプラグ数は相対的に少ない請求項2に記載の半導体装置。
- 前記nチャネルトランジスタ形成領域における応力と前記pチャネルトランジスタ形成領域における応力との相違が、コンタクトプラグの形状の相違によるものである請求項1に記載の半導体装置。
- 前記コンタクトプラグの構成材料は圧縮応力を持つ材料であって、前記nチャネルトランジスタ形成領域のコンタクトプラグの径は相対的に小さく、前記pチャネルトランジスタ形成領域のコンタクトプラグの径は相対的に大きい請求項5に記載の半導体装置。
- 前記コンタクトプラグの構成材料は引張応力を持つ材料であって、前記nチャネルトランジスタ形成領域のコンタクトプラグの径は相対的に大きく、前記pチャネルトランジスタ形成領域のコンタクトプラグの径は相対的に小さい請求項5に記載の半導体装置。
- 前記コンタクトプラグの構成材料は圧縮応力を持つ材料であって、前記nチャネルトランジスタ形成領域のコンタクトプラグは最小寸法であり、前記pチャネルトランジスタ形成領域のコンタクトプラグはチャネルと平行方向に前記最小寸法よりも大きくされている請求項5に記載の半導体装置。
- 前記コンタクトプラグの構成材料は引張応力を持つ材料であって、前記pチャネルトランジスタ形成領域のコンタクトプラグは最小寸法であり、前記nチャネルトランジスタ形成領域のコンタクトプラグはチャネルと平行方向に前記最小寸法よりも大きくされている請求項5に記載の半導体装置。
- 前記コンタクトプラグの構成材料は圧縮応力を持つ材料であって、前記nチャネルトランジスタ形成領域のコンタクトプラグは最小寸法であり、前記pチャネルトランジスタ形成領域のコンタクトプラグはゲート電極と平行方向に前記最小寸法よりも大きくされている請求項5に記載の半導体装置。
- 前記コンタクトプラグの構成材料は引張応力を持つ材料であって、前記pチャネルトランジスタ形成領域のコンタクトプラグは最小寸法であり、前記nチャネルトランジスタ形成領域のコンタクトプラグはゲート電極と平行方向に前記最小寸法よりも大きくされている請求項5に記載の半導体装置。
- 前記nチャネルトランジスタ形成領域における応力と前記pチャネルトランジスタ形成領域における応力との相違が、コンタクトプラグの構成材料の相違によるものである請求項1に記載の半導体装置。
- 前記nチャネルトランジスタ形成領域のコンタクトプラグの構成材料は引張応力を持つ材料であり、前記pチャネルトランジスタ形成領域のコンタクトプラグの構成材料は圧縮応力を持つ材料である請求項12に記載の半導体装置。
- 前記nチャネルトランジスタ形成領域における応力と前記pチャネルトランジスタ形成領域における応力との相違が、前記nチャネルトランジスタ形成領域のコンタクトプラグに用いるバリアメタルの構成と前記pチャネルトランジスタ形成領域のコンタクトプラグに用いるバリアメタルの構成の相違によるものである請求項1に記載の半導体装置。
- 前記nチャネルトランジスタ形成領域のコンタクトプラグに用いるバリアメタルの構成材料は引張応力を持つ材料であり、前記pチャネルトランジスタ形成領域のコンタクトプラグに用いるバリアメタルの構成材料は圧縮応力を持つ材料である請求項14に記載の半導体装置。
- 前記バリアメタルの構成材料は圧縮応力を持つ材料であって、前記nチャネルトランジスタ形成領域のコンタクトプラグに用いるバリアメタルの膜厚は相対的に薄く、前記pチャネルトランジスタ形成領域のコンタクトプラグに用いるバリアメタルの膜厚は相対的に厚い請求項14に記載の半導体装置。
- 前記バリアメタルの構成材料は引張応力を持つ材料であって、前記nチャネルトランジスタ形成領域のコンタクトプラグに用いるバリアメタルの膜厚は相対的に厚く、前記pチャネルトランジスタ形成領域のコンタクトプラグに用いるバリアメタルの膜厚は相対的に薄い請求項14に記載の半導体装置。
- 前記nチャネルトランジスタ形成領域における応力と前記pチャネルトランジスタ形成領域における応力との相違が、前記nチャネルトランジスタ形成領域のコンタクトプラグの高さと前記pチャネルトランジスタ形成領域のコンタクトプラグの高さの相違によるものである請求項1に記載の半導体装置。
- 前記コンタクトプラグの構成材料は圧縮応力を持つ材料であって、前記nチャネルトランジスタ形成領域のコンタクトプラグの高さは相対的に小さく、前記pチャネルトランジスタ形成領域のコンタクトプラグの高さは相対的に大きい請求項18に記載の半導体装置。
- 前記コンタクトプラグの構成材料は引張応力を持つ材料であって、前記nチャネルトランジスタ形成領域のコンタクトプラグの高さは相対的に大きく、前記pチャネルトランジスタ形成領域のコンタクトプラグの高さは相対的に小さい請求項18に記載の半導体装置。
- 前記nチャネルトランジスタ形成領域における応力と前記pチャネルトランジスタ形成領域における応力との相違が、前記nチャネルトランジスタ形成領域のコンタクトプラグとゲート電極の間隔と前記pチャネルトランジスタ形成領域のコンタクトプラグとゲート電極の間隔の相違によるものである請求項1に記載の半導体装置。
- 前記コンタクトプラグの構成材料は圧縮応力を持つ材料であって、前記nチャネルトランジスタ形成領域のコンタクトプラグとゲート電極の距離は相対的に広く、前記pチャネルトランジスタ形成領域のコンタクトプラグとゲート電極の距離は相対的に狭い請求項21に記載の半導体装置。
- 前記コンタクトプラグの構成材料は引張応力を持つ材料であって、前記nチャネルトランジスタ形成領域のコンタクトプラグとゲート電極の距離は相対的に狭く、前記pチャネルトランジスタ形成領域のコンタクトプラグとゲート電極の距離は相対的に広い請求項21に記載の半導体装置。
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US12/405,668 US7821138B2 (en) | 2004-12-17 | 2009-03-17 | Semiconductor device with an improved operating property |
US12/882,643 US20110001193A1 (en) | 2004-12-17 | 2010-09-15 | Semiconductor device with an improved operating property |
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US20110001193A1 (en) | 2011-01-06 |
JP4833544B2 (ja) | 2011-12-07 |
US20090200582A1 (en) | 2009-08-13 |
US7821138B2 (en) | 2010-10-26 |
US20060131662A1 (en) | 2006-06-22 |
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