CN109427680B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN109427680B
CN109427680B CN201710748816.6A CN201710748816A CN109427680B CN 109427680 B CN109427680 B CN 109427680B CN 201710748816 A CN201710748816 A CN 201710748816A CN 109427680 B CN109427680 B CN 109427680B
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layer
dummy gate
semiconductor
drain
source
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CN109427680A (zh
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to US16/113,067 priority patent/US10741670B2/en
Publication of CN109427680A publication Critical patent/CN109427680A/zh
Priority to US16/921,019 priority patent/US11189711B2/en
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Abstract

本发明公开了一种半导体装置及其制造方法。方法包括：提供半导体结构，其包括：衬底、在衬底上的鳍片和在鳍片上的伪栅极结构，伪栅极结构包括：在鳍片上的伪栅极绝缘物层和在伪栅极绝缘物层上的伪栅极；在半导体结构上沉积盖层，盖层包括在伪栅极结构侧面上的第一部分和在半导体鳍片之上的第二部分；在第一部分侧面上形成牺牲层；以伪栅极结构和牺牲层为掩模，刻蚀第二部分和半导体鳍片以形成第一凹陷和第二凹陷；在这两个凹陷中分别形成源极和漏极；形成层间电介质层并执行平坦化以露出伪栅极的上表面；和去除伪栅极和伪栅极绝缘物层的部分以形成露出半导体鳍片的部分表面的凹槽。本发明可以防止后续形成的金属栅极与源极和漏极连接。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体技术领域，特别涉及一种半导体装置及其制造方法。
背景技术
随着MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金属氧化物半导体场效应晶体管)器件的尺寸逐渐减小，短沟道效应(the short channel effect，简称为SCE)成为一个关键问题。FinFET(Fin Field Effect Transistor，鳍片式场效应晶体管) 器件对沟道电荷显示出比较好的栅极控制能力，从而可以进一步缩小 CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)器件的尺寸。
在FinFET器件的制造过程中，需要利用金属栅极代替多晶硅伪栅极，以及需要利用栅极电介质层代替伪栅极绝缘物层。在这个过程中，需要去除伪栅极和伪栅极绝缘物层来形成凹槽。然而在利用刻蚀工艺去除伪栅极绝缘物层的过程中，该刻蚀工艺可能会造成对STI (Shallow Trench Isolation，浅沟槽隔离)中的硅的氧化物的横向刻蚀，该横向刻蚀可能会使得该硅的氧化物产生缝隙从而露出在凹槽两侧的源极和漏极。然后在凹槽中形成金属栅极的过程中，金属栅极可以通过缝隙与源极和漏极连接，从而降低器件的可靠性。
发明内容
本发明的发明人发现上述现有技术中存在问题，并因此针对所述问题中的至少一个问题提出了一种新的技术方案。
根据本发明的第一方面，提供了一种半导体装置的制造方法，包括：提供半导体结构，所述半导体结构包括：半导体衬底、在所述半导体衬底上的半导体鳍片以及在所述半导体鳍片上的伪栅极结构，所述伪栅极结构至少包括：在所述半导体鳍片表面上的伪栅极绝缘物层和在所述伪栅极绝缘物层上的伪栅极；在所述半导体结构上沉积盖层；其中，所述盖层包括：在所述伪栅极结构两侧的侧面上的第一部分和在所述半导体鳍片之上的第二部分；在所述盖层的所述第一部分的侧面上形成牺牲层；以所述伪栅极结构和所述牺牲层作为掩模，刻蚀所述盖层的第二部分和所述半导体鳍片，以在所述伪栅极结构两侧分别形成第一凹陷和第二凹陷；在所述第一凹陷中形成源极并在所述第二凹陷中形成漏极；形成覆盖所述伪栅极结构、所述源极和所述漏极的层间电介质层；对形成所述层间电介质层之后的半导体结构执行平坦化以露出所述伪栅极的上表面；以及去除所述伪栅极以及所述伪栅极绝缘物层的一部分以形成露出所述半导体鳍片的部分表面的凹槽。
在一个实施例中，所述方法还包括：在所述凹槽中形成栅极结构；其中，所述栅极结构包括：在所述凹槽中覆盖在所述半导体鳍片的所述部分表面上的栅极电介质层和在所述栅极电介质层上的金属栅极。
在一个实施例中，在形成所述第一凹陷和所述第二凹陷之后且在形成所述源极和所述漏极之前，所述方法还包括：去除所述牺牲层。
在一个实施例中，所述盖层的材料包括：硅的氮化物；所述盖层的厚度范围为：
Figure BDA0001390650560000021
至
Figure BDA0001390650560000022
在一个实施例中，所述牺牲层的材料包括：硅的氧化物；所述牺牲层的厚度范围为：
Figure BDA0001390650560000023
至
Figure BDA0001390650560000024
在一个实施例中，所述盖层的所述第一部分包括：位于所述源极和所述伪栅极结构之间的源极侧部分和位于所述漏极和所述伪栅极结构之间的漏极侧部分；在去除所述牺牲层之后，在形成所述层间电介质层的过程中，所述层间电介质层的一部分将所述源极和所述源极侧部分间隔开，所述层间电介质层的另一部分将所述漏极和所述漏极侧部分间隔开。
在一个实施例中，在提供半导体结构的步骤中，所述半导体结构还包括：在所述半导体衬底上且在所述半导体鳍片周围的沟槽和部分地填充所述沟槽的沟槽绝缘物层；所述盖层还包括：覆盖在所述沟槽绝缘物层上的第三部分和在所述伪栅极结构的顶表面上的第四部分；其中，在刻蚀所述盖层的第二部分和所述半导体鳍片的步骤中，还去除了所述盖层的第四部分。
在一个实施例中，在提供半导体结构的步骤中，所述伪栅极结构还包括：在所述伪栅极上的硬掩模层和在所述伪栅极和所述硬掩模层的侧面上的间隔物层；其中，所述盖层的所述第一部分位于所述间隔物层的侧面上；在对形成所述层间电介质层之后的半导体结构执行平坦化的过程中，该平坦化工艺去除了所述硬掩模层。
在一个实施例中，在所述盖层的所述第一部分的侧面上形成牺牲层的步骤包括：在所述盖层上沉积牺牲层；以及对所述牺牲层执行刻蚀，其中，在该刻蚀过程中，保留所述牺牲层的在所述盖层的所述第一部分的侧面上的部分，去除所述牺牲层的其他部分。
在上述制造方法中，在形成源极和漏极之前，在半导体结构上沉积盖层并在盖层上形成位于伪栅极结构两侧的牺牲层，然后以该牺牲层和伪栅极结构作为掩模，刻蚀盖层和半导体鳍片，从而形成在伪栅极结构两侧的第一凹陷和第二凹陷，然后在第一凹陷和第二凹陷中分别形成源极和漏极，然后形成层间电介质层并进行平坦化以露出伪栅极的上表面，去除伪栅极和伪栅极绝缘物层的一部分以形成露出半导体鳍片的凹槽。在该制造过程中，相比现有技术，上述形成的盖层和牺牲层可以使得源极和漏极分别更加远离伪栅极结构，也即更加远离后续去除伪栅极和伪栅极绝缘物层而形成的凹槽，因此即使形成凹槽的过程中存在像现有技术中对沟槽绝缘物层的横向刻蚀问题，该横向刻蚀也不容易导致露出源极和漏极，因此在后续形成金属栅极的过程中，该金属栅极不容易出现与该源极和漏极连接的问题，从而可以提高器件的可靠性。
根据本发明的第二方面，提供了一种半导体装置，包括：半导体衬底；在所述半导体衬底上的半导体鳍片；在所述半导体鳍片上的栅极结构；至少部分地位于所述半导体鳍片中的源极和漏极；其中，所述源极和所述漏极分别位于所述栅极结构的两侧；在所述半导体鳍片之上和所述栅极结构两侧的侧面上的盖层；其中，所述盖层包括：在所述栅极结构两侧的侧面上的第一部分和在所述半导体鳍片之上的第二部分；以及在所述盖层上的层间电介质层；其中，所述层间电介质层覆盖所述源极和所述漏极；所述层间电介质层形成有露出所述半导体鳍片的部分表面的凹槽，所述栅极结构在所述凹槽中。
在一个实施例中，所述栅极结构包括：在所述凹槽中覆盖在所述半导体鳍片的所述部分表面上的栅极电介质层和在所述栅极电介质层上的金属栅极。
在一个实施例中，所述盖层的材料包括：硅的氮化物；所述盖层的厚度范围为：
Figure BDA0001390650560000041
至
Figure BDA0001390650560000042
在一个实施例中，所述盖层的所述第一部分包括：位于所述源极和所述栅极结构之间的源极侧部分和位于所述漏极和所述栅极结构之间的漏极侧部分。
在一个实施例中，所述层间电介质层的一部分将所述源极和所述源极侧部分间隔开，所述层间电介质层的另一部分将所述漏极和所述漏极侧部分间隔开。
在一个实施例中，所述源极和所述源极侧部分的间隔距离的范围为：
Figure BDA0001390650560000043
至
Figure BDA0001390650560000044
所述漏极和所述漏极侧部分的间隔距离的范围为：
Figure BDA0001390650560000045
至
Figure BDA0001390650560000046
在一个实施例中，所述半导体装置还包括：在所述盖层的所述第一部分的侧面上的牺牲层；其中，所述牺牲层的一部分将所述源极和所述源极侧部分间隔开，所述牺牲层的另一部分将所述漏极和所述漏极侧部分间隔开。
在一个实施例中，所述半导体装置还包括：在所述半导体衬底上且在所述半导体鳍片周围的沟槽和部分地填充所述沟槽的沟槽绝缘物层；所述盖层还包括：覆盖在所述沟槽绝缘物层上的第三部分。
在一个实施例中，所述栅极结构还包括：在所述凹槽中且在所述金属栅极的侧面上的间隔物层；其中，所述盖层的所述第一部分位于所述间隔物层的侧面上。
在上述实施例中，提供了一种半导体装置。相比现有技术，本发明实施例的半导体装置中，源极和漏极更加远离栅极结构，因此可以尽可能地防止金属栅极与源极和漏极连接，提高器件的可靠性。
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本发明的实施例，并且连同说明书一起用于解释本发明的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本发明，其中：
图1是示意性地示出现有技术中的半导体装置的制造过程中一个阶段的结构的横截面图。
图2是示意性地示出现有技术中的半导体装置的制造过程中一个阶段的结构的横截面图。
图3是示意性地示出现有技术中的半导体装置的制造过程中一个阶段的结构的横截面图。
图4是示意性地示出现有技术中的半导体装置的制造过程中一个阶段的结构的横截面图。
图5是示意性地示出现有技术中的半导体装置的制造过程中一个阶段的结构的横截面图。
图6A是示意性地示出现有技术中的半导体装置的制造过程中一个阶段的结构的横截面图。
图6B是示意性地示出现有技术中的半导体装置的制造过程中一个阶段的结构的横截面图。
图6C是示意性地示出现有技术中的半导体装置的制造过程中一个阶段的结构的顶视图，其中，图6A是沿着图6C中的线A-A’截取的结构的横截面图，图6B是沿着图6C中的线B-B’截取的结构的横截面图。
图7是示出根据本发明一个实施例的半导体装置的制造方法的流程图。
图8是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图9A是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图9B是示意性地示出沿着图9A中的线C-C’截取的结构的横截面图。
图10是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图11是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图12是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图13是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图14是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图15是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图16是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图17是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图18是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图19是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图20是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
图21是示意性地示出根据本发明一个实施例的半导体装置的制造过程中一个阶段的结构的横截面图。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本发明的范围。
同时，应当明白，为了便于描述，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为授权说明书的一部分。
在这里示出和讨论的所有示例中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它示例可以具有不同的值。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
图1至图5是示意性地示出现有技术中的半导体装置的制造过程中若干阶段的结构的横截面图。图6C是示意性地示出现有技术中的半导体装置的制造过程中一个阶段的结构的顶视图，其中，图6A是沿着图6C中的线A-A’截取的结构的横截面图，图6B是沿着图6C中的线B-B’截取的结构的横截面图。下面结合图1至图5以及图6A 至图6C详细描述现有技术中半导体装置的制造过程以及所可能出现的问题。
首先，如图1所示，提供半导体结构，该半导体结构包括：衬底 100、在该衬底100上的第一鳍片101和第二鳍片102、在这些鳍片周围的沟槽以及填充沟槽的硅的氧化物层103(该沟槽和沟槽中的硅的氧化物层103可以构成STI)。该半导体结构还包括：在第一鳍片101和第二鳍片102表面上的伪栅极绝缘物层104、在伪栅极绝缘物层104上的伪栅极(其材料可以是多晶硅)105、在该伪栅极105上的硬掩模层106以及在伪栅极两侧的侧面上的间隔物层107。
接下来，如图2所示，在伪栅极105两侧分别形成源极和漏极，例如用于NMOS(N-channel Metal Oxide Semiconductor，N型沟道金属氧化物半导体)器件的第一源极111和第一漏极112、用于PMOS (P-channel Metal Oxide Semiconductor，P型沟道金属氧化物半导体)器件的第二源极121和第二漏极122。
接下来，如图3所示，在图2所示的结构上沉积层间电介质层 132。
接下来，如图4所示，对图3所示的结构执行CMP(Chemical MechanicalPlanarization，化学机械平坦化)以露出伪栅极105的上表面。
接下来，如图5所示，去除伪栅极105，从而形成凹槽140。
接下来，如图6A、图6B和图6C所示(其中，图6A是沿着鳍片的延伸方向截取的结构的横截面图，图6B是沿着沟槽中的硅的氧化物层的延伸方向截取的结构的横截面图)，通过刻蚀工艺去除伪栅极绝缘物层104在凹槽140中的部分，从而露出鳍片(例如第一鳍片 101和第二鳍片102)的部分表面。
本发明的发明人发现，从图6B可以看出，在利用刻蚀工艺去除伪栅极绝缘物层的过程中，该刻蚀工艺可能会造成对沟槽中的硅的氧化物层103的横向刻蚀，该横向刻蚀可能会使得该硅的氧化物层103 产生缝隙(例如该缝隙可以与沟道相邻)从而露出在凹槽两侧的源极和漏极(例如，如图6B中在方框处所示的缝隙露出了第一源极111 和第一漏极112，在圆圈处所示的缝隙露出了第二源极121和第二漏极122)。然后在凹槽140中形成金属栅极时，金属栅极可以通过缝隙与源极和漏极连接，从而降低器件的可靠性。
图7是示出根据本发明一个实施例的半导体装置的制造方法的流程图。图8、图9A至图9B、图10至图21是示意性地示出根据本发明一个实施例的半导体装置的制造过程中若干阶段的结构的横截面图。下面结合图7以及图8、图9A至图9B、图10至图21详细描述根据本发明一个实施例的半导体装置的制造过程。
如图7所示，在步骤S701，提供半导体结构，该半导体结构包括：半导体衬底、在该半导体衬底上的半导体鳍片以及在该半导体鳍片上的伪栅极结构，该伪栅极结构至少包括：在半导体鳍片表面上的伪栅极绝缘物层和在该伪栅极绝缘物层上的伪栅极。
下结合图8、图9A至图9B以及图10详细描述形成根据本发明一个实施例的半导体结构的过程。
首先，如图8所示，提供初始结构，该初始结构包括：半导体衬底20和在该半导体衬底20上的半导体鳍片21。该半导体衬底和该半导体鳍片的材料可以均包括硅。例如图8示出了在半导体衬底20 上具有多个半导体鳍片21。可选地，该初始结构还可以包括：在半导体衬底20上且在半导体鳍片21周围的沟槽22和部分地填充该沟槽22的沟槽绝缘物层23。例如，该沟槽绝缘物层的材料可以包括二氧化硅。
接下来，如图9A和图9B所示，在半导体鳍片上形成伪栅极结构30。该伪栅极结构30可以包括：在半导体鳍片21表面上的伪栅极绝缘物层(例如二氧化硅)31和在该伪栅极绝缘物层31上的伪栅极32。例如，该伪栅极32的材料可以包括多晶硅。可选地，该伪栅极结构30还可以包括：在伪栅极32上的硬掩模层34。例如该硬掩模层34可以包括：在伪栅极上的氮化硅层和该氮化硅层上的硅的氧化物层等。可选地，该伪栅极结构30还可以包括：在伪栅极32与硬掩模层34之间的缓冲层(例如二氧化硅)33。
可选地，接下来，如图10所示，在伪栅极32和硬掩模层34的两侧的侧面上形成间隔物层35。例如，该间隔物层35的材料可以包括二氧化硅和/或氮化硅等。可选地，在形成间隔物层之后，该制造方法还可以包括：对半导体鳍片执行LDD(Lightly Doped Drain，轻掺杂漏区)离子注入操作。
至此，形成了图10所示的半导体结构。如图10所示，该半导体结构可以包括：半导体衬底20、在该半导体衬底20上的半导体鳍片 21以及在该半导体鳍片21上的伪栅极结构30。该伪栅极结构30至少包括：在半导体鳍片21表面上的伪栅极绝缘物层31和在该伪栅极绝缘物层31上的伪栅极32。图10中示出了分别在两个半导体鳍片 21上的两个相同或相似的伪栅极结构30。
可选地，如图10所示，该伪栅极结构30还可以包括：在伪栅极 32上的硬掩模层34以及在该伪栅极32和该硬掩模层34的侧面上的间隔物层35。可选地，该伪栅极结构30还可以包括：在伪栅极32 与硬掩模层34之间的缓冲层33。
可选地，如图10所示，该半导体结构还可以包括：在半导体衬底20上且在半导体鳍片21周围的沟槽22和部分地填充该沟槽的沟槽绝缘物层23。
回到图7，在步骤S702，在半导体结构上沉积盖层；其中，该盖层包括：在伪栅极结构两侧的侧面上的第一部分和在该半导体鳍片之上的第二部分。
图11是示意性地示出在步骤S702的结构的横截面图。如图11 所示，在图10所示的半导体结构上沉积盖层40。该盖层40可以包括：在伪栅极结构30两侧的侧面上的第一部分41和在该半导体鳍片 21之上的第二部分42。例如，该盖层40的第一部分41位于间隔物层35的侧面上。例如，该第二部分42可以形成在半导体鳍片21上的伪栅极绝缘物层31的表面上。可选地，该盖层40还可以包括：覆盖在沟槽绝缘物层23上的第三部分43和在伪栅极结构30的顶表面 (例如在硬掩模层34的顶表面)上的第四部分44。
在一个实施例中，该盖层40的材料可以包括：硅的氮化物。例如，该硅的氮化物可以包括：SiN(氮化硅)、SiCN(碳氮化硅)、 SiBCN(氮碳硼硅)或SiOCN(氮碳氧硅)等。
在一个实施例中，该盖层40的厚度范围可以为：
Figure BDA0001390650560000111
至
Figure BDA0001390650560000112
例如，该盖层40的厚度可以为
Figure BDA0001390650560000113
或
Figure BDA0001390650560000114
等。
回到图7，在步骤S703，在该盖层的第一部分的侧面上形成牺牲层。下面可以结合图12和图13详细描述形成该牺牲层的过程。
例如，如图12所示，该步骤S703可以包括：在盖层40上沉积牺牲层50。例如，该牺牲层50的材料可以包括：硅的氧化物(例如二氧化硅)。在一个实施例中，该牺牲层50的厚度范围可以为：
Figure BDA0001390650560000115
至
Figure BDA0001390650560000118
例如，该牺牲层50的厚度可以为
Figure BDA0001390650560000116
或
Figure BDA0001390650560000117
等。
接下来，如图13所示，该步骤S703还可以包括：对牺牲层50 执行刻蚀，其中，在该刻蚀过程中，保留该牺牲层的在盖层40的第一部分41的侧面上的部分，去除该牺牲层的其他部分。即，该刻蚀工艺去除了该牺牲层的在该盖层40的第二部分42、第三部分43和第四部分44上的部分，保留了该牺牲层的在第一部分41侧面上的部分。
回到图7，在步骤S704，以伪栅极结构和牺牲层作为掩模，刻蚀盖层的第二部分和半导体鳍片，以在伪栅极结构两侧分别形成第一凹陷和第二凹陷。
图14是示意性地示出在步骤S704的结构的横截面图。如图14 所示，以伪栅极结构30和牺牲层50作为掩模，自对准地刻蚀盖层40 的第二部分42和半导体鳍片21，以在伪栅极结构30两侧分别形成第一凹陷61和第二凹陷62。在该刻蚀过程中，还刻蚀了在半导体鳍片21表面上的伪栅极绝缘物层31的部分，从而可以进一步刻蚀该伪栅极绝缘物层下面的半导体鳍片，进而形成上述两个凹陷。
可选地，如图14所示，在该刻蚀盖层的第二部分和半导体鳍片的步骤中，还去除了该盖层40的第四部分44。
接下来，可选地，如图15所示，在形成第一凹陷61和第二凹陷 62之后，去除牺牲层50。这有利于在后续外延形成源极和漏极的过程中，可以使得源极和漏极的体积比较大，从而增加源极和漏极对沟道的应力，提高器件性能。
回到图7，在步骤S705，在第一凹陷中形成源极并在第二凹陷中形成漏极。
图16是示意性地示出在步骤S705的结构的横截面图。如图16 所示，例如通过外延工艺在第一凹陷61中形成源极81并在第二凹陷 62中形成漏极82。如图16所示，该盖层的第一部分41可以包括：位于源极81和伪栅极结构30之间的源极侧部分411和位于漏极82 和伪栅极结构30之间的漏极侧部分412。由于去除了牺牲层50，因此该源极侧部分411和源极81之间形成有间隙，该漏极侧部分412 和漏极之间也形成有间隙。
回到图7，在步骤S706，形成覆盖伪栅极结构、源极和漏极的层间电介质层。
图17是示意性地示出在步骤S706的结构的横截面图。如图17 所示，例如在图16所示的半导体结构上沉积层间电介质层85，从而形成覆盖伪栅极结构30、源极81和漏极82的层间电介质层85。该层间电介质层85的材料可以包括二氧化硅。
如图17所示，在形成该层间电介质层85的过程中，该层间电介质层85的一部分将源极81和源极侧部分411间隔开，该层间电介质层85的另一部分将漏极82和漏极侧部分412间隔开。即，该层间电介质层85填充了该源极侧部分411和源极81之间的间隙和该漏极侧部分412和漏极82之间的间隙。
回到图7，在步骤S707，对形成层间电介质层之后的半导体结构执行平坦化以露出伪栅极的上表面。
图18是示意性地示出在步骤S707的结构的横截面图。如图18 所示，对形成层间电介质层之后的半导体结构(例如图17所示的半导体结构)执行平坦化(例如CMP)以露出伪栅极32的上表面。在一个实施例中，在该平坦化的过程中，该平坦化工艺去除了硬掩模层34。在一个实施例中，该平坦化工艺还去除了缓冲层33。例如，该平坦化工艺可以包括第一平坦化处理和第二平坦化处理。例如利用第一平坦化处理去除层间电介质层85的一部分和硬掩模层34，然后利用第二平坦化处理去除层间电介质层85的另一部分和缓冲层33，从而露出伪栅极32的上表面。
回到图7，在步骤S708，去除伪栅极以及伪栅极绝缘物层的一部分以形成露出半导体鳍片的部分表面的凹槽。下面结合图19和图 20详细描述该步骤S708。
例如，如图19所示，该步骤S708可以包括：在露出伪栅极32 的上表面之后，去除伪栅极32，从而形成凹槽87。在该凹槽87的底部露出了伪栅极绝缘物层31的部分。
接下来，如图20所示，该步骤S708还可以包括：去除伪栅极绝缘物层31的一部分，从而露出半导体鳍片21的部分表面。至此形成了露出半导体鳍片21的部分表面的凹槽87。
至此，提供了根据本发明一个实施例的半导体装置的制造方法。在该制造方法中，在形成源极和漏极之前，在半导体结构上沉积盖层并在盖层上形成位于伪栅极结构两侧的牺牲层，然后以该牺牲层和伪栅极结构作为掩模，刻蚀盖层和半导体鳍片，从而形成在伪栅极结构两侧的第一凹陷和第二凹陷，然后在第一凹陷和第二凹陷中分别形成源极和漏极，然后形成层间电介质层并进行平坦化以露出伪栅极的上表面，去除伪栅极和伪栅极绝缘物层的一部分以形成露出半导体鳍片的部分表面的凹槽。在该制造过程中，相比现有技术，上述形成的盖层和牺牲层可以使得源极和漏极分别更加远离伪栅极结构，也即更加远离后续通过去除伪栅极和伪栅极绝缘物层而形成的凹槽，因此即使在形成凹槽的过程中存在像现有技术中对沟槽绝缘物层的横向刻蚀问题，该横向刻蚀也不容易导致露出源极和漏极，因此在后续形成金属栅极的过程中，该金属栅极不容易出现与源极和漏极连接的问题，从而可以提高器件的可靠性。
进一步地，由于相比现有技术，本发明的源极和漏极分别距离金属栅极更远些，因此可以允许将源极和漏极的体积制造得更大一些，这样可以提高源极和漏极对沟道的应力，从而可以提高器件性能。
在一个实施例中，在形成凹槽87之后，所述制造方法还可以包括：如图21所示，在凹槽87中形成栅极结构90。该栅极结构90可以包括：在凹槽87中覆盖在半导体鳍片21的部分表面上的栅极电介质层91和在该栅极电介质层上的金属栅极92。该栅极电介质层的材料可以包括：二氧化硅或高k电介质材料(例如TiO2或HfO2等) 等。例如，该金属栅极的材料可以包括钨等。由于在前面的制造过程中，相比现有技术，源极和漏极分别更加远离伪栅极结构，因此即使在去除伪栅极和伪栅极绝缘物层而形成凹槽的过程中，存在像现有技术中对沟槽绝缘物层的横向刻蚀问题，该横向刻蚀也不容易导致露出源极和漏极，因此在该形成金属栅极的过程中，该金属栅极不容易出现与源极和漏极连接的问题，从而可以提高器件的可靠性。
由上述制造方法，还形成了根据本发明一个实施例的半导体装置。例如21所示，该半导体装置可以包括：半导体衬底20、在该半导体衬底20上的半导体鳍片21和在该半导体鳍片21上的栅极结构90。该半导体装置还可以包括：至少部分地位于该半导体鳍片21中的源极 81和漏极82。其中，该源极81和该漏极82分别位于栅极结构90的两侧。该半导体装置还可以包括：在半导体鳍片21之上和栅极结构 90两侧的侧面上的盖层40。其中，该盖层40可以包括：在栅极结构 90两侧的侧面上的第一部分41和在该半导体鳍片21之上的第二部分 42。该半导体装置还可以包括：在盖层40上的层间电介质层85。该层间电介质层85覆盖源极81和漏极82。该层间电介质层85形成有露出半导体鳍片21的部分表面的凹槽87，该栅极结构90在该凹槽87 中。
在一个实施例中，如图21所示，该栅极结构90可以包括：在该凹槽87中覆盖在半导体鳍片21的部分表面上的栅极电介质层91和在该栅极电介质层91上的金属栅极92。在一个实施例中，如图21所示，该栅极结构90还可以包括：在凹槽87中且在金属栅极92的侧面上的间隔物层35。其中，盖层40的第一部分41位于该间隔物层35的侧面上。
在一个实施例中，该盖层40的材料可以包括：硅的氮化物。在一个实施例中，该盖层40的厚度范围可以为：
Figure BDA0001390650560000151
至
Figure BDA0001390650560000152
在一个实施例中，该盖层的第一部分41可以包括：位于源极81 和栅极结构90之间的源极侧部分411和位于漏极82和栅极结构90 之间的漏极侧部分412。
在一个实施例中，层间电介质层85的一部分将该源极81和该源极侧部分411间隔开，该层间电介质层85的另一部分将该漏极82和该漏极侧部分412间隔开。
在一个实施例中，该源极81和该源极侧部分411的间隔距离的范围可以为：
Figure BDA0001390650560000153
至
Figure BDA0001390650560000154
例如，该间隔距离可以是
Figure BDA0001390650560000158
或
Figure BDA0001390650560000159
等。在一个实施例中，该漏极82和该漏极侧部分412的间隔距离的范围可以为：
Figure BDA0001390650560000155
至
Figure BDA0001390650560000156
例如，该间隔距离可以是
Figure BDA0001390650560000157
或
Figure BDA00013906505600001510
等。
在另一个实施例中，该半导体装置还可以包括：在盖层的第一部分的侧面上的牺牲层。其中，该牺牲层的一部分将源极和源极侧部分间隔开，该牺牲层的另一部分将漏极和漏极侧部分间隔开。这里需要说明的是，虽然图21中没有示出该牺牲层，但是在前面的制造过程中，如果没有去除牺牲层50，则在最后形成的半导体装置中将包括该牺牲层50，因此本发明的范围并不仅限于图21所示的半导体装置的结构。在一个实施例中，该牺牲层的材料可以包括：硅的氧化物。在一个实施例中，该牺牲层的厚度范围可以为：
Figure BDA00013906505600001511
至
Figure BDA00013906505600001512
例如，该牺牲层的厚度可以为
Figure BDA00013906505600001513
或
Figure BDA00013906505600001514
等。
在一个实施例中，如图21所示，该半导体装置还可以包括：在半导体衬底20上且在半导体鳍片21周围的沟槽22和部分地填充该沟槽的沟槽绝缘物层23。该盖层还可以包括：覆盖在沟槽绝缘物层23上的第三部分43。
在一个实施例中，如图21所示，该半导体装置还可以包括：覆盖在半导体鳍片21上的伪栅极绝缘物层31，其中该盖层的第二部分 42覆盖在该伪栅极绝缘物层31上。
在上述实施例中，提供了一种半导体装置。相比现有技术，本发明实施例的半导体装置中，源极和漏极更加远离栅极结构，因此可以尽可能地防止金属栅极与源极和漏极连接，提高器件的可靠性。
至此，已经详细描述了根据本发明的制造半导体器件的方法和所形成的半导体器件。为了避免遮蔽本发明的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本发明的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本发明的范围。本领域的技术人员应该理解，可在不脱离本发明的范围和精神的情况下，对以上实施例进行修改。本发明的范围由所附权利要求来限定。

Claims (11)

1.一种半导体装置的制造方法，其特征在于，包括：
提供半导体结构，所述半导体结构包括：半导体衬底、在所述半导体衬底上的半导体鳍片、在所述半导体鳍片上的伪栅极结构、在所述半导体衬底上且在所述半导体鳍片周围的沟槽和部分地填充所述沟槽的沟槽绝缘物层，所述伪栅极结构至少包括：在所述半导体鳍片表面上的伪栅极绝缘物层、在所述伪栅极绝缘物层上的伪栅极、在所述伪栅极上的硬掩模层和在所述伪栅极和所述硬掩模层的侧面上的间隔物层；
在所述半导体结构上沉积盖层；其中，所述盖层包括：在所述伪栅极结构两侧的侧面上的第一部分、在所述半导体鳍片之上的第二部分、覆盖在所述沟槽绝缘物层上的第三部分和在所述伪栅极结构的顶表面上的第四部分，所述盖层的所述第一部分位于所述间隔物层的侧面上，所述盖层的厚度范围为：
Figure FDA0002963118610000011
至
Figure FDA0002963118610000012
在所述盖层的所述第一部分的侧面上形成牺牲层，所述牺牲层的厚度范围为：
Figure FDA0002963118610000013
至
Figure FDA0002963118610000014
以所述伪栅极结构和所述牺牲层作为掩模，刻蚀所述盖层的第二部分和所述半导体鳍片以在所述伪栅极结构两侧分别形成第一凹陷和第二凹陷，并且还去除所述盖层的第四部分；
在所述第一凹陷中形成源极并在所述第二凹陷中形成漏极；
形成覆盖所述伪栅极结构、所述源极和所述漏极的层间电介质层；
对形成所述层间电介质层之后的半导体结构执行平坦化以露出所述伪栅极的上表面，其中，该平坦化去除了所述硬掩模层；以及
去除所述伪栅极以及所述伪栅极绝缘物层的一部分以形成露出所述半导体鳍片的部分表面的凹槽。
2.根据权利要求1所述的方法，其特征在于，还包括：
在所述凹槽中形成栅极结构；其中，所述栅极结构包括：在所述凹槽中覆盖在所述半导体鳍片的所述部分表面上的栅极电介质层和在所述栅极电介质层上的金属栅极。
3.根据权利要求1所述的方法，其特征在于，在形成所述第一凹陷和所述第二凹陷之后且在形成所述源极和所述漏极之前，所述方法还包括：去除所述牺牲层。
4.根据权利要求1所述的方法，其特征在于，
所述盖层的材料包括：硅的氮化物。
5.根据权利要求1所述的方法，其特征在于，
所述牺牲层的材料包括：硅的氧化物。
6.根据权利要求3所述的方法，其特征在于，
所述盖层的所述第一部分包括：位于所述源极和所述伪栅极结构之间的源极侧部分和位于所述漏极和所述伪栅极结构之间的漏极侧部分；
在去除所述牺牲层之后，在形成所述层间电介质层的过程中，所述层间电介质层的一部分将所述源极和所述源极侧部分间隔开，所述层间电介质层的另一部分将所述漏极和所述漏极侧部分间隔开。
7.根据权利要求1所述的方法，其特征在于，在所述盖层的所述第一部分的侧面上形成牺牲层的步骤包括：
在所述盖层上沉积牺牲层；以及
对所述牺牲层执行刻蚀，其中，在该刻蚀过程中，保留所述牺牲层的在所述盖层的所述第一部分的侧面上的部分，去除所述牺牲层的其他部分。
8.一种半导体装置，其特征在于，包括：
半导体衬底；
在所述半导体衬底上的半导体鳍片；
在所述半导体衬底上且在所述半导体鳍片周围的沟槽和部分地填充所述沟槽的沟槽绝缘物层；
在所述半导体鳍片上的栅极结构；
至少部分地位于所述半导体鳍片中的源极和漏极；其中，所述源极和所述漏极分别位于所述栅极结构的两侧；
在所述半导体鳍片之上和所述栅极结构两侧的侧面上的盖层；其中，所述盖层包括：在所述栅极结构两侧的侧面上的第一部分、在所述半导体鳍片之上的第二部分和覆盖在所述沟槽绝缘物层上的第三部分，所述盖层的厚度范围为：
Figure FDA0002963118610000031
至
Figure FDA0002963118610000032
所述盖层的所述第一部分包括：位于所述源极和所述栅极结构之间的源极侧部分和位于所述漏极和所述栅极结构之间的漏极侧部分，其中，所述源极和所述源极侧部分的间隔距离的范围为：
Figure FDA0002963118610000033
至
Figure FDA0002963118610000034
所述漏极和所述漏极侧部分的间隔距离的范围为：
Figure FDA0002963118610000035
至
Figure FDA0002963118610000036
以及
在所述盖层上的层间电介质层；其中，所述层间电介质层覆盖所述源极和所述漏极；所述层间电介质层形成有露出所述半导体鳍片的部分表面的凹槽，所述栅极结构在所述凹槽中；
其中，所述栅极结构包括：在所述凹槽中覆盖在所述半导体鳍片的所述部分表面上的栅极电介质层、在所述栅极电介质层上的金属栅极和在所述凹槽中且在所述金属栅极的侧面上的间隔物层；其中，所述盖层的所述第一部分位于所述间隔物层的侧面上。
9.根据权利要求8所述的半导体装置，其特征在于，
所述盖层的材料包括：硅的氮化物。
10.根据权利要求8所述的半导体装置，其特征在于，
所述层间电介质层的一部分将所述源极和所述源极侧部分间隔开，所述层间电介质层的另一部分将所述漏极和所述漏极侧部分间隔开。
11.根据权利要求8所述的半导体装置，其特征在于，还包括：
在所述盖层的所述第一部分的侧面上的牺牲层；其中，所述牺牲层的一部分将所述源极和所述源极侧部分间隔开，所述牺牲层的另一部分将所述漏极和所述漏极侧部分间隔开。
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