TWI400741B - 利用預置金屬介電質線性應力之高性能互補金氧半導體電晶體 - Google Patents
利用預置金屬介電質線性應力之高性能互補金氧半導體電晶體 Download PDFInfo
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- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 17
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 16
- 229910052739 hydrogen Inorganic materials 0.000 claims description 16
- 239000001257 hydrogen Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 229910052707 ruthenium Inorganic materials 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 18
- 239000002184 metal Substances 0.000 description 18
- 239000003989 dielectric material Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 5
- 239000007943 implant Substances 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- NZIHMSYSZRFUQJ-UHFFFAOYSA-N 6-chloro-1h-benzimidazole-2-carboxylic acid Chemical compound C1=C(Cl)C=C2NC(C(=O)O)=NC2=C1 NZIHMSYSZRFUQJ-UHFFFAOYSA-N 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- DIOQZVSQGTUSAI-UHFFFAOYSA-N decane Chemical compound CCCCCCCCCC DIOQZVSQGTUSAI-UHFFFAOYSA-N 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910001507 metal halide Inorganic materials 0.000 description 2
- 150000005309 metal halides Chemical class 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- CXXKWLMXEDWEJW-UHFFFAOYSA-N tellanylidenecobalt Chemical compound [Te]=[Co] CXXKWLMXEDWEJW-UHFFFAOYSA-N 0.000 description 2
- 150000004772 tellurides Chemical class 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- -1 hafnium nitride Chemical class 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- SITVSCPRJNYAGV-UHFFFAOYSA-L tellurite Chemical compound [O-][Te]([O-])=O SITVSCPRJNYAGV-UHFFFAOYSA-L 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
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Description
本發明一般而言係有關積體電路製造的領域，且尤其是有關一種用於形成高性能金氧半導體電晶體的方法。
積體電路金氧半導體(MOS)電晶體之性能取決於一些元件參數，諸如介電質厚度、電晶體閘極長度與金氧半導體電晶體通道區中之電子及/或電洞移動率。電子及/或電洞(以下稱為載體)移動率是一種載體橫越電晶體通道區之速度的計量。一般而言，電晶體通道區內之載體移動率是與載體的速度及通道電場相關，其關係式係μ＝Vc a r r i e r s
/Ec h a n n e l
，其中μ是載體移動率，Vc a r r i e r s
是通道中載體的速度，而Ec h a n n e l
是金氧半導體電晶體通道中的電場。一般而言，當載體橫越電晶體通道區從電晶體源極區橫行到電晶體汲極區時，載體移動率係受一些包括載體散射的因素之影響。
金氧半導體電晶體性能的一重要計量是針對一給定閘極－源極電壓(VG S
)及一給定汲極－源極電壓(VD S
)所獲得的電晶體汲極電流(ID S
)的大小。除與VG S
及VD S
有關外，ID S
也與載體移動率μ成比例。因此重要的是使載體移動率μ最大，以改進電晶體性能。近來，已發現施加應力於電晶體通道區內是增加載體移動率μ之值的一重要因素。已利用一些方法以施加應力至包括在電晶體結構上形成高應力膜的電晶體通道區。頃發現，施加應力隨膜厚度而增加。然而，積體電路的高密度限制了可使用的膜厚度。因此需求一種藉由高應力膜增加產生在電晶體通道中之應力而不增加膜厚度的方法。本發明可解決此需要。
本揭露書揭示一種用於形成積體電路的方法。尤其是該方法包含在一半導體基板表面上形成一閘極介電層。一閘極電極係形成在該閘極介電層上，且側壁結構係形成鄰近該閘極電極。源極及汲極區係使用離子植入形成在鄰近該側壁結構的半導體基板中。
一氫濃度大於20原子百分比之氮化矽層(及具有一第一張應力)係形成在閘極電極及源極與汲極區上。該氮化矽層被熱退火，導致在氮化矽層中之第二張應力，其中第二張應力係大於第一張應力。在本發明一具體實施例中，該氮化矽層係在低於350℃之溫度處形成。退火後，該氮化矽層中的氫濃度在該熱退火後係大於12原子百分比。
圖1(a)顯示使用積體電路製造方法形成的金氧半導體電晶體。如圖1(a)中顯示，隔離區20係形成在一半導體10中。該等隔離區20可包含氧化矽或任何適合之介電材料，且可使用淺溝渠隔離(STI)或局部氧化(LOCOS)方法形成。包含一閘極介電層30及一閘極電極40的電晶體閘極堆疊係形成在半導體10表面上。通常閘極電極40包含一例如摻雜多晶矽、各種金屬及/或金屬矽化物的導電材料。閘極介電層30可包含任何例如氧化矽、氮化矽、氮氧化矽、高介電常數介電材料(諸如鉿)及其他適合材料的適合介電材料。在本揭露書中，高介電常數係指介電常數大於3.9之介電材料。電晶體閘極堆疊的典型厚度在500埃及5000埃之間。在電晶體閘極堆疊形成後，會施行一些自對準植入。此等自對準植入包括汲極/源極延伸植入及袋狀件植入。對準電晶體閘極堆疊之自對準植入將導致在半導體10中摻雜汲極延伸區50的形成。側壁結構60係使用標準處理技術形成與閘極電極40相鄰。側壁結構60通常包含的介電材料諸如氧化矽、氮化矽或任何其他適合之介電材料。側壁結構60形成後，電晶體源極及汲極區70係藉由植入適合的摻雜劑形成到半導體10中。在源極及汲極區70形成後，金屬矽化物層80及90係分別形成在源極及汲極區70及閘極電極40上。在一具體實施例中，金屬矽化物區80、90包含矽化鎳、矽化鈷、或任何其他適合之金屬矽化物材料。在其中閘極電極40包含一金屬或金屬矽化物之情況下，沒有矽化層90會形成在該閘極電極上。如圖1(a)中顯示，在此揭露書中，金氧半導體電晶體結構的通道區100係定義為基板10在閘極電極40下方限制反轉層的區域。在一金氧半導體電晶體中，該反轉層係當一超過第二電壓之第一電壓施加於閘極電極時形成，該第二電壓係藉由等於或大於該電晶體臨限電壓之量同時施加於電晶體源極區70。對於NMOS電晶體而言，該反轉層包含電子。以類似模式，該反轉層係當一超過第二電壓之第一電壓施加於電晶體源極區70時形成在一PMOS電晶體中，該第二電壓係藉由等於或大於電晶體臨限電壓之量施加於閘極電極40。對於一PMOS電晶體而言，該反轉層包含電洞。
在圖1(a)所示之金氧半導體電晶體結構形成後，一預置金屬介電質(PMD)襯覆蓋層110係形成在圖1(b)中顯示的電晶體結構上。在本發明一具體實施例中，PMD襯層110可包含一厚度X1
形成在50埃及1500埃間的氮化矽。可使用電漿增強化學汽相沉積方法(PECVD)，在200℃及400℃之溫度間與0.5 torr及6 torr壓力間，使用一些包含流量在25 sccm及250 sccm間之SiH4
及流量在500 sccm及4000 sccm間之NH3
的氣體，形成氮化矽PMD襯層110。需要低氮化矽層形成溫度(即，低於400℃)，以形成具有高氫濃度之介穩(meta－stable)層。在一範例性實例中，製程條件係：沉積溫度低於約350℃、室內壓力係控制至約3.5 torf或更多、以約150 sccm或更少的矽烷(SiH4
)氣流，及大約2500至3000 sccm的氨(NH3
)氣流、使用設定在13.56 MHz處約50瓦之高頻射頻功率，及設定在350 KHz處約10－20瓦之低頻功率。在上述條件下，一氮化矽PMD襯層110會形成具有超過20原子百分比的氫濃度。除高氫濃度外，PMD氮化矽層110係形成在具有將近500 MPa張應力之介穩狀態中。
在PMD襯層110形成後，及在PMD層(圖1(c)中的層120)形成前，PMD襯層110被熱退火。對於上述的具體實施例，在其中金屬矽化物層80包括矽化鎳時，可使PMD襯層在300℃及525℃之溫度間退火。另一選擇是，如果金屬矽化物層包括矽化鈷，可使PMD襯層在400℃及850℃之溫度間退火。在熱退火製程後，PMD襯層的張應力將增加到大約1.1 Gpa之值，且氫濃度將維持大於約12原子百分比之濃度位準。高張應力及高氫濃度的同時出現將藉由增加通道區100內之載體移動率μ而改進電晶體性能。在此揭露書中，高張應力係定義為在PMD襯層內大於800 Mpa之張應力，而高氫濃度係定義為在PMD襯層內超過17原子百分比之氫濃度。
一般而言，根據本發明，首先藉由在一金氧半導體電晶體上形成一介穩層而形成高應力PMD襯層。該介穩層包含一大於20原子百分比之氫濃度及一大於400 Mpa之張應力。在介穩層上形成任何額外層之前，該介穩層係在NH3
中或例如N2
、Ar等之惰性氣體中於300℃及900℃之溫度間熱退火，以形成具有高張應力(即大於800 MPa)且氫濃度大於12原子百分比之穩定PMD襯層。高應力PMD襯層110包含一可在通道區100中施加張應力之應力。如上述，在包含NMOS電晶體中反轉層之通道區100內的張應力將作用以增強電子的移動率。當氮化層包含一高氫含量及應力二者時，可觀察到到通道區100內的張應力將會造成PMOS電晶體最小程度之劣化。因此無須選擇性地施加不同應力於NMOS及PMOS電晶體。為了改進NMOS電晶體而不影響PMOS電晶體的性能，本發明避免需要在NMOS及PMOS電晶體上形成不同應力區的任何額外製造步驟。
在高應力PMD襯層110形成後，會形成PMD層120。PMD層120可包含氧化矽、磷摻雜矽酸鹽玻璃(PSG)或任何其他適合的介電材料。PMD層的厚度通常是400至1000奈米，其係比位於底下之氮化物襯層厚。此外，PMD層的應力通常是低於該氮化物襯層。因此，有利的是在於形成氮化物襯層後立即施行熱退火，以轉換該襯層成為高應力狀態，避免由於PMD層之可能限制而減少施加於該電晶體上之有效應力。如圖1(d)中顯示，金屬接觸130可形成在圖1(c)中顯示的金氧半導體電晶體結構之源極及汲極區70。可使用標準微影蝕刻以蝕刻接觸孔至覆蓋源極及汲極區70之矽化物區80。接著使用金屬填充接觸孔以在金氧半導體電晶體之源極及汲極區形成接觸結構130。
圖1(a)至圖1(d)中顯示的本發明具體實施例可同樣充分適用於NMOS及PMOS電晶體二者。不論電晶體是NMOS或PMOS，均將取決於基板10、摻雜延伸區50及源極與汲極區70的傳導型式。對於NMOS電晶體，源極與汲極區70及摻雜延伸區50將是n型，且基板將是p型。對於PMOS電晶體，源極與汲極區70及摻雜延伸區50將是p型，而基板將是n型。
10．．．半導體
20．．．隔離區
30．．．閘極介電層
40．．．閘極電極
50．．．延伸區
60．．．側壁結構
70．．．源極及汲極區
80,90．．．金屬矽化物層
100．．．通道區
110．．．預置金屬介電質(PMD)襯層
120．．．(PMD)層
130．．．金屬接觸
圖1(a)至1(d)是顯示本發明一具體實施例的斷面圖。
10．．．半導體
20．．．隔離區
30．．．閘極介電層
40．．．閘極電極
50．．．延伸區
60．．．側壁結構
70．．．源極及汲極區
80．．．金屬矽化物層
90．．．金屬矽化物層
100．．．通道區
110．．．預置金屬介電質(PMD)襯層
120．．．預置金屬介電質層
130．．．金屬接觸
Claims (6)
- 一種形成一積體電路的方法，其包含：提供一半導體基板；在該半導體基板之一表面上形成一閘極介電層；在該閘極介電層上形成一閘極電極；形成鄰近該閘極電極之側壁結構；在鄰近該等側壁結構的該半導體基板中形成源極及汲極區；形成一氮化矽層於該閘極電極及該源極與汲極區上方；其中該氮化矽層具有一大於20原子百分比之一第一氫濃度及一第一張應力；熱退火該氮化矽層，其造成不同於該第一氫濃度之一第二氫濃度以及在該氮化矽層中之一第二張應力，其中該第二張應力係大於該第一張應力；且在該氮化矽層上形成一介電層。
- 如請求項1之方法，其中該氮化矽層係在低於350℃之溫度處形成。
- 如請求項2之方法，其中該氮化矽層在該熱退火後包含一大於12原子百分比之氫濃度。
- 如請求項1之方法，其中該第一張應力係約500 MPa。
- 如請求項4之方法，其中該第二張應力係大於800 MPa。
- 如請求項5之方法，其中該氮化矽層係在300℃至900℃之溫度間熱退火。
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| US10/833,419 US7192894B2 (en) | 2004-04-28 | 2004-04-28 | High performance CMOS transistors using PMD liner stress |
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| US7192894B2 (en) * | 2004-04-28 | 2007-03-20 | Texas Instruments Incorporated | High performance CMOS transistors using PMD liner stress |
| JP2006165335A (ja) * | 2004-12-08 | 2006-06-22 | Toshiba Corp | 半導体装置 |
| US20060151843A1 (en) * | 2005-01-12 | 2006-07-13 | International Business Machines Corporation | Hot carrier degradation reduction using ion implantation of silicon nitride layer |
| TWI263265B (en) * | 2005-02-13 | 2006-10-01 | United Microelectronics Corp | Method for fabricating ultra-high tensile-stressed film and strained-silicon transistors thereof |
| US20060189167A1 (en) * | 2005-02-18 | 2006-08-24 | Hsiang-Ying Wang | Method for fabricating silicon nitride film |
| US8129290B2 (en) | 2005-05-26 | 2012-03-06 | Applied Materials, Inc. | Method to increase tensile stress of silicon nitride films using a post PECVD deposition UV cure |
| US8138104B2 (en) * | 2005-05-26 | 2012-03-20 | Applied Materials, Inc. | Method to increase silicon nitride tensile stress using nitrogen plasma in-situ treatment and ex-situ UV cure |
| US7888194B2 (en) * | 2007-03-05 | 2011-02-15 | United Microelectronics Corp. | Method of fabricating semiconductor device |
| US7867861B2 (en) | 2007-09-27 | 2011-01-11 | Infineon Technologies Ag | Semiconductor device employing precipitates for increased channel stress |
| US7863201B2 (en) * | 2008-03-24 | 2011-01-04 | Samsung Electronics Co., Ltd. | Methods of forming field effect transistors having silicided source/drain contacts with low contact resistance |
| JP2009295621A (ja) * | 2008-06-02 | 2009-12-17 | Panasonic Corp | 半導体装置及びその製造方法 |
| CN102623330B (zh) * | 2012-03-13 | 2015-01-21 | 上海华力微电子有限公司 | 一种形成前金属介电质层的方法 |
| US20130292766A1 (en) | 2012-05-03 | 2013-11-07 | International Business Machines Corporation | Semiconductor substrate with transistors having different threshold voltages |
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| US7256421B2 (en) * | 2002-05-17 | 2007-08-14 | Semiconductor Energy Laboratory, Co., Ltd. | Display device having a structure for preventing the deterioration of a light emitting device |
| KR100500451B1 (ko) * | 2003-06-16 | 2005-07-12 | 삼성전자주식회사 | 인장된 채널을 갖는 모스 트랜지스터를 구비하는반도체소자의 제조 방법 |
| US6930007B2 (en) * | 2003-09-15 | 2005-08-16 | Texas Instruments Incorporated | Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance |
| US20050170104A1 (en) * | 2004-01-29 | 2005-08-04 | Applied Materials, Inc. | Stress-tuned, single-layer silicon nitride film |
| US7226834B2 (en) * | 2004-04-19 | 2007-06-05 | Texas Instruments Incorporated | PMD liner nitride films and fabrication methods for improved NMOS performance |
| US7192894B2 (en) * | 2004-04-28 | 2007-03-20 | Texas Instruments Incorporated | High performance CMOS transistors using PMD liner stress |
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| WO2005106940A3 (en) | 2005-12-22 |
| US8809141B2 (en) | 2014-08-19 |
| US20050245012A1 (en) | 2005-11-03 |
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