JP2005524243A5 - - Google Patents

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Publication number
JP2005524243A5
JP2005524243A5 JP2004502363A JP2004502363A JP2005524243A5 JP 2005524243 A5 JP2005524243 A5 JP 2005524243A5 JP 2004502363 A JP2004502363 A JP 2004502363A JP 2004502363 A JP2004502363 A JP 2004502363A JP 2005524243 A5 JP2005524243 A5 JP 2005524243A5
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JP
Japan
Prior art keywords
polysilicon body
providing
insulator
dopant species
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004502363A
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English (en)
Japanese (ja)
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JP2005524243A (ja
Filing date
Publication date
Priority claimed from US10/135,227 external-priority patent/US6599831B1/en
Application filed filed Critical
Publication of JP2005524243A publication Critical patent/JP2005524243A/ja
Publication of JP2005524243A5 publication Critical patent/JP2005524243A5/ja
Pending legal-status Critical Current

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JP2004502363A 2002-04-30 2003-04-28 シリサイドを使用する金属ゲート電極およびこれを形成する方法 Pending JP2005524243A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/135,227 US6599831B1 (en) 2002-04-30 2002-04-30 Metal gate electrode using silicidation and method of formation thereof
PCT/US2003/012958 WO2003094243A1 (en) 2002-04-30 2003-04-28 Metal gate electrode using silicidation and method of formation thereof

Publications (2)

Publication Number Publication Date
JP2005524243A JP2005524243A (ja) 2005-08-11
JP2005524243A5 true JP2005524243A5 (enExample) 2006-06-15

Family

ID=27610948

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004502363A Pending JP2005524243A (ja) 2002-04-30 2003-04-28 シリサイドを使用する金属ゲート電極およびこれを形成する方法

Country Status (8)

Country Link
US (2) US6599831B1 (enExample)
EP (1) EP1502305A1 (enExample)
JP (1) JP2005524243A (enExample)
KR (1) KR20040102187A (enExample)
CN (2) CN102157362B (enExample)
AU (1) AU2003231119A1 (enExample)
TW (1) TWI270935B (enExample)
WO (1) WO2003094243A1 (enExample)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6599831B1 (en) * 2002-04-30 2003-07-29 Advanced Micro Devices, Inc. Metal gate electrode using silicidation and method of formation thereof
US7183182B2 (en) * 2003-09-24 2007-02-27 International Business Machines Corporation Method and apparatus for fabricating CMOS field effect transistors
JP4011024B2 (ja) * 2004-01-30 2007-11-21 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP4521597B2 (ja) * 2004-02-10 2010-08-11 ルネサスエレクトロニクス株式会社 半導体記憶装置およびその製造方法
US7056782B2 (en) * 2004-02-25 2006-06-06 International Business Machines Corporation CMOS silicide metal gate integration
JP3998665B2 (ja) * 2004-06-16 2007-10-31 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP2006013270A (ja) * 2004-06-29 2006-01-12 Renesas Technology Corp 半導体装置およびその製造方法
KR100558011B1 (ko) * 2004-07-12 2006-03-06 삼성전자주식회사 전체실리사이드 금속게이트전극을 갖는 모스 트랜지스터의제조방법
JP2006108355A (ja) * 2004-10-05 2006-04-20 Renesas Technology Corp 半導体装置およびその製造方法
KR100593452B1 (ko) * 2005-02-01 2006-06-28 삼성전자주식회사 전체실리사이드 금속게이트전극을 갖는 모스 트랜지스터의제조방법
JP2006245417A (ja) * 2005-03-04 2006-09-14 Toshiba Corp 半導体装置およびその製造方法
WO2006098369A1 (ja) * 2005-03-15 2006-09-21 Nec Corporation 半導体装置の製造方法及び半導体装置
US20060258074A1 (en) * 2005-05-12 2006-11-16 Texas Instruments Incorporated Methods that mitigate excessive source/drain silicidation in full gate silicidation metal gate flows
JP2006339324A (ja) * 2005-06-01 2006-12-14 Fujitsu Ltd 半導体装置の製造方法
JP2006339441A (ja) * 2005-06-02 2006-12-14 Fujitsu Ltd 半導体装置の製造方法
EP1744351A3 (en) * 2005-07-11 2008-11-26 Interuniversitair Microelektronica Centrum ( Imec) Method for forming a fully silicided gate MOSFET and devices obtained thereof
JP2007027727A (ja) * 2005-07-11 2007-02-01 Interuniv Micro Electronica Centrum Vzw フルシリサイド化ゲートｍｏｓｆｅｔの形成方法及び該方法により得られるデバイス
KR100646937B1 (ko) 2005-08-22 2006-11-23 삼성에스디아이 주식회사 다결정 실리콘 박막트랜지스터 및 그 제조방법
JP2007173347A (ja) * 2005-12-20 2007-07-05 Renesas Technology Corp 半導体装置及びその製造方法
JPWO2007077814A1 (ja) * 2006-01-06 2009-06-11 日本電気株式会社 半導体装置及びその製造方法
JP2007251030A (ja) * 2006-03-17 2007-09-27 Renesas Technology Corp 半導体装置の製造方法および半導体装置
US7491643B2 (en) * 2006-05-24 2009-02-17 International Business Machines Corporation Method and structure for reducing contact resistance between silicide contact and overlying metallization
US7297618B1 (en) 2006-07-28 2007-11-20 International Business Machines Corporation Fully silicided gate electrodes and method of making the same
JPWO2008035490A1 (ja) * 2006-09-20 2010-01-28 日本電気株式会社 半導体装置およびその製造方法
WO2008065908A1 (fr) * 2006-11-29 2008-06-05 Phyzchemix Corporation Procédé de formation d'un film de composé d'élément métallique du groupe iv et procédé de fabrication d'un dispositif semi-conducteur
US7727842B2 (en) * 2007-04-27 2010-06-01 Texas Instruments Incorporated Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device
US8183137B2 (en) * 2007-05-23 2012-05-22 Texas Instruments Incorporated Use of dopants to provide low defect gate full silicidation
JP2009026997A (ja) * 2007-07-20 2009-02-05 Renesas Technology Corp 半導体装置およびその製造方法
US7642153B2 (en) * 2007-10-23 2010-01-05 Texas Instruments Incorporated Methods for forming gate electrodes for integrated circuits
CN101981688B (zh) * 2008-04-02 2014-04-02 Imec公司 制造半导体器件的方法以及半导体器件
CN101562131B (zh) * 2008-04-15 2012-04-18 和舰科技(苏州)有限公司 栅极结构的制造方法
US8012817B2 (en) * 2008-09-26 2011-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor performance improving method with metal gate
US9871035B2 (en) * 2013-12-31 2018-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with metal silicide blocking region and method of manufacturing the same
US9972694B2 (en) * 2015-10-20 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Atomic layer deposition methods and structures thereof
KR102612404B1 (ko) * 2019-03-08 2023-12-13 삼성전자주식회사 반도체 소자 및 그의 제조 방법

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7510903A (nl) * 1975-09-17 1977-03-21 Philips Nv Werkwijze voor het vervaardigen van een halfgelei- derinrichting, en inrichting vervaardigd volgens de werkwijze.
JPS59125650A (ja) * 1983-01-07 1984-07-20 Toshiba Corp 半導体装置の製造方法
US4450620A (en) * 1983-02-18 1984-05-29 Bell Telephone Laboratories, Incorporated Fabrication of MOS integrated circuit devices
JPS616867A (ja) * 1984-06-20 1986-01-13 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
US4755865A (en) * 1986-01-21 1988-07-05 Motorola Inc. Means for stabilizing polycrystalline semiconductor layers
US4746964A (en) * 1986-08-28 1988-05-24 Fairchild Semiconductor Corporation Modification of properties of p-type dopants with other p-type dopants
US5237196A (en) * 1987-04-14 1993-08-17 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JPH01243549A (ja) * 1988-03-25 1989-09-28 Seiko Epson Corp 半導体装置
US5168072A (en) * 1990-10-12 1992-12-01 Texas Instruments Incorporated Method of fabricating an high-performance insulated-gate field-effect transistor
US5767558A (en) * 1996-05-10 1998-06-16 Integrated Device Technology, Inc. Structures for preventing gate oxide degradation
US6335280B1 (en) * 1997-01-13 2002-01-01 Asm America, Inc. Tungsten silicide deposition process
US5851891A (en) * 1997-04-21 1998-12-22 Advanced Micro Devices, Inc. IGFET method of forming with silicide contact on ultra-thin gate
US6117761A (en) * 1997-08-23 2000-09-12 Micron Technology, Inc. Self-aligned silicide strap connection of polysilicon layers
US5937319A (en) * 1997-10-31 1999-08-10 Advanced Micro Devices, Inc. Method of making a metal oxide semiconductor (MOS) transistor polysilicon gate with a size beyond photolithography limitation by using polysilicidation and selective etching
JPH11284179A (ja) * 1998-03-30 1999-10-15 Sony Corp 半導体装置およびその製造方法
US6091123A (en) * 1998-06-08 2000-07-18 Advanced Micro Devices Self-aligned SOI device with body contact and NiSi2 gate
US6100173A (en) * 1998-07-15 2000-08-08 Advanced Micro Devices, Inc. Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process
US6451644B1 (en) * 1998-11-06 2002-09-17 Advanced Micro Devices, Inc. Method of providing a gate conductor with high dopant activation
US6228724B1 (en) * 1999-01-28 2001-05-08 Advanced Mirco Devices Method of making high performance MOSFET with enhanced gate oxide integration and device formed thereby
JP2000252462A (ja) * 1999-03-01 2000-09-14 Toshiba Corp Ｍｉｓ型半導体装置及びその製造方法
US6281559B1 (en) * 1999-03-03 2001-08-28 Advanced Micro Devices, Inc. Gate stack structure for variable threshold voltage
US6245692B1 (en) * 1999-11-23 2001-06-12 Agere Systems Guardian Corp. Method to selectively heat semiconductor wafers
US6365481B1 (en) * 2000-09-13 2002-04-02 Advanced Micro Devices, Inc. Isotropic resistor protect etch to aid in residue removal
US6562718B1 (en) * 2000-12-06 2003-05-13 Advanced Micro Devices, Inc. Process for forming fully silicided gates
US6479383B1 (en) * 2002-02-05 2002-11-12 Chartered Semiconductor Manufacturing Ltd Method for selective removal of unreacted metal after silicidation
US6599831B1 (en) * 2002-04-30 2003-07-29 Advanced Micro Devices, Inc. Metal gate electrode using silicidation and method of formation thereof
US6544829B1 (en) * 2002-09-20 2003-04-08 Lsi Logic Corporation Polysilicon gate salicidation

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