JP2005514768A - 埋め込み金属シリサイド・ビットラインを備えたmonosデバイス - Google Patents
埋め込み金属シリサイド・ビットラインを備えたmonosデバイス Download PDFInfo
- Publication number
- JP2005514768A JP2005514768A JP2003555586A JP2003555586A JP2005514768A JP 2005514768 A JP2005514768 A JP 2005514768A JP 2003555586 A JP2003555586 A JP 2003555586A JP 2003555586 A JP2003555586 A JP 2003555586A JP 2005514768 A JP2005514768 A JP 2005514768A
- Authority
- JP
- Japan
- Prior art keywords
- metal silicide
- recess
- bitline
- monos
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 47
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 41
- 239000002184 metal Substances 0.000 title claims abstract description 41
- LPQOADBMXVRBNX-UHFFFAOYSA-N ac1ldcw0 Chemical compound Cl.C1CN(C)CCN1C1=C(F)C=C2C(=O)C(C(O)=O)=CN3CCSC1=C32 LPQOADBMXVRBNX-UHFFFAOYSA-N 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000000137 annealing Methods 0.000 claims abstract description 11
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 239000003870 refractory metal Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 239000002019 doping agent Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 230000008021 deposition Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- -1 metal oxide nitride Chemical class 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000005549 size reduction Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
(発明の開示)
これとその他の要求は、基板上に電荷捕獲誘電層を形成するステップとビットライン・パターンに従って電荷捕獲誘電層を介してリセス(recess)をエッチングするステップとを含む、MONOS(金属 酸化膜 窒化膜 酸化膜 半導体)デバイスの作製の方法を提供する本発明の実施態様により達成される。そして、金属シリサイドのビットラインはこのリセスの中に形成される。
(発明の詳細な説明)
Claims (13)
- MONOS(金属 酸化膜 窒化膜 酸化膜 半導体)デバイスを作製する方法であって、
基板(30)上に電荷捕獲誘電層(32)を形成し、
ビットライン・パターンに基づいて、前記電荷捕獲誘電層(32)を貫くリセス(44)をエッチングし、
前記リセス(44)内に金属シリサイド・ビットライン(48)を形成する、各ステップを備えている方法。 - 前記金属シリサイド・ビットライン(48)を形成するステップは、
前記リセス(44)内に耐熱性金属(46)を堆積すること、および
前記リセス(44)内に金属シリサイド(48)を形成するために前記リセス(44)内部をレーザ熱アニーリングすること、を含む請求項1の方法。 - 前記金属シリサイド・ビットライン(48)の下にソース/ドレイン領域(52)を形成するための、前記基板(30)内へのドーパント(50)の打ち込みをさらに含む、請求項2の方法。
- 前記リセス内に、前記金属シリサイド・ビットラインを被覆する酸化膜(54)の形成をさらに含む、請求項3の方法。
- 前記レーザ熱アニーリングのステップは、約50mJ/cm2から約1.3J/cm2の範囲のエネルギ・フルエンスのレーザエネルギ供給を含む、請求項2の方法。
- 前記電荷捕獲誘電層(32)は、酸化膜−窒化膜−酸化膜層である、請求項1の方法。
- 基板(30)と、
前記基板(30)上の電荷捕獲誘電層(32)と、
前記電荷捕獲誘電層(32)内のリセス(44)と、
前記リセス(44)内の金属シリサイド・ビットライン(48)と、
を備えている金属 酸化膜 窒化膜 酸化膜 半導体(MONOS)。 - 前記金属シリサイド・ビットライン(48)は、埋め込みビットラインである、請求項7のMONOS。
- 前記リセス内の前記金属シリサイド・ビットラインの上の酸化膜と、前記電荷捕獲誘電層および前記酸化膜を被覆するワードラインと、をさらに備えている請求項8のMONOS。
- 前記金属シリサイド・ビットラインの下に、ソース/ドレイン領域を含む、請求項9のMONOS。
- 前記金属シリサイド・ビットラインは、レーザ熱アニールされた金属シリサイドを含む、請求項10のMONOS。
- 前記電荷捕獲誘電層は酸化膜−窒化膜−酸化膜(ONO)層である、請求項11のMONOS。
- 前記リセスは前記基板内に延在しており、前記金属シリサイド・ビットラインは当該リセス内にある、請求項12のMONOS。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/022,798 US6828199B2 (en) | 2001-12-20 | 2001-12-20 | Monos device having buried metal silicide bit line |
PCT/US2002/039781 WO2003054964A2 (en) | 2001-12-20 | 2002-12-11 | Monos device having buried metal silicide bit line |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005514768A true JP2005514768A (ja) | 2005-05-19 |
JP4681227B2 JP4681227B2 (ja) | 2011-05-11 |
Family
ID=21811503
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003555586A Expired - Fee Related JP4681227B2 (ja) | 2001-12-20 | 2002-12-11 | 半導体デバイスを作製する方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US6828199B2 (ja) |
EP (1) | EP1456885B1 (ja) |
JP (1) | JP4681227B2 (ja) |
KR (1) | KR100948199B1 (ja) |
CN (1) | CN1311557C (ja) |
AU (1) | AU2002357826A1 (ja) |
TW (1) | TWI267942B (ja) |
WO (1) | WO2003054964A2 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005045012A (ja) * | 2003-07-22 | 2005-02-17 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2007329480A (ja) * | 2006-06-09 | 2007-12-20 | Samsung Electronics Co Ltd | 埋め込みビットラインの形成方法 |
JP2012142548A (ja) * | 2010-12-30 | 2012-07-26 | Sk Hynix Inc | 埋め込みビットラインを備えた半導体装置の製造方法 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060084268A1 (en) * | 2004-10-15 | 2006-04-20 | Martin Verhoeven | Method for production of charge-trapping memory cells |
GB2436271B (en) * | 2005-01-24 | 2010-06-16 | Spansion Llc | Semiconductor device and fabrication method thereof |
US8435873B2 (en) * | 2006-06-08 | 2013-05-07 | Texas Instruments Incorporated | Unguarded Schottky barrier diodes with dielectric underetch at silicide interface |
US7678654B2 (en) * | 2006-06-30 | 2010-03-16 | Qimonda Ag | Buried bitline with reduced resistance |
US8642441B1 (en) | 2006-12-15 | 2014-02-04 | Spansion Llc | Self-aligned STI with single poly for manufacturing a flash memory device |
US8486782B2 (en) * | 2006-12-22 | 2013-07-16 | Spansion Llc | Flash memory devices and methods for fabricating the same |
KR101149043B1 (ko) | 2009-10-30 | 2012-05-24 | 에스케이하이닉스 주식회사 | 매립형 비트라인을 구비하는 반도체 장치 및 그 제조방법 |
US8853768B1 (en) | 2013-03-13 | 2014-10-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of fabricating MONOS semiconductor device |
KR102600998B1 (ko) | 2016-09-28 | 2023-11-13 | 삼성전자주식회사 | 반도체 장치 |
CN110021559B (zh) * | 2018-01-09 | 2021-08-24 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04209573A (ja) * | 1990-12-06 | 1992-07-30 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法及び半導体装置 |
JPH10335493A (ja) * | 1997-05-28 | 1998-12-18 | Nec Corp | 半導体記憶装置 |
US6156654A (en) * | 1998-12-07 | 2000-12-05 | Chartered Semiconductor Manufacturing Ltd. | Pulsed laser salicidation for fabrication of ultra-thin silicides in sub-quarter micron devices |
JP2001094076A (ja) * | 1999-09-20 | 2001-04-06 | Fujitsu Ltd | 半導体集積回路装置とその製造方法 |
JP2002539611A (ja) * | 1999-03-09 | 2002-11-19 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 不揮発性メモリを有する半導体装置 |
JP2003163289A (ja) * | 2001-11-27 | 2003-06-06 | Mitsubishi Electric Corp | 半導体メモリの製造方法、及び該半導体メモリを含む半導体装置の製造方法 |
JP2003533884A (ja) * | 2000-05-16 | 2003-11-11 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 不揮発性メモリセルの均一なビット線のストラッピング |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5168334A (en) | 1987-07-31 | 1992-12-01 | Texas Instruments, Incorporated | Non-volatile semiconductor memory |
EP0368097A3 (en) | 1988-11-10 | 1992-04-29 | Texas Instruments Incorporated | A cross-point contact-free floating-gate memory array with silicided buried bitlines |
US5670297A (en) | 1991-12-30 | 1997-09-23 | Sony Corporation | Process for the formation of a metal pattern |
US6350643B1 (en) * | 1997-12-18 | 2002-02-26 | Advanced Technology Materials, Inc. | Reduced degradation of metal oxide ceramic due to diffusion of a mobile specie therefrom |
US6121134A (en) * | 1998-04-21 | 2000-09-19 | Micron Technology, Inc. | High aspect ratio metallization structures and processes for fabricating the same |
TW379417B (en) * | 1998-06-04 | 2000-01-11 | United Semiconductor Corp | Buried bitline structure and the manufacture method |
US6261908B1 (en) | 1998-07-27 | 2001-07-17 | Advanced Micro Devices, Inc. | Buried local interconnect |
US6355543B1 (en) * | 1998-09-29 | 2002-03-12 | Advanced Micro Devices, Inc. | Laser annealing for forming shallow source/drain extension for MOS transistor |
US7157314B2 (en) * | 1998-11-16 | 2007-01-02 | Sandisk Corporation | Vertically stacked field programmable nonvolatile memory and method of fabrication |
KR100325472B1 (ko) * | 1999-04-15 | 2002-03-04 | 박종섭 | 디램 메모리 셀의 제조 방법 |
US6210995B1 (en) * | 1999-09-09 | 2001-04-03 | International Business Machines Corporation | Method for manufacturing fusible links in a semiconductor device |
DE19946435A1 (de) * | 1999-09-28 | 2001-04-05 | Infineon Technologies Ag | Integrierter Halbleiter-Festwertspeicher |
US6177318B1 (en) * | 1999-10-18 | 2001-01-23 | Halo Lsi Design & Device Technology, Inc. | Integration method for sidewall split gate monos transistor |
US6248633B1 (en) * | 1999-10-25 | 2001-06-19 | Halo Lsi Design & Device Technology, Inc. | Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory |
US6248635B1 (en) * | 1999-10-25 | 2001-06-19 | Advanced Micro Devices, Inc. | Process for fabricating a bit-line in a monos device using a dual layer hard mask |
US6326268B1 (en) * | 1999-10-25 | 2001-12-04 | Advanced Micro Devices, Inc. | Method of fabricating a MONOS flash cell using shallow trench isolation |
KR100335498B1 (ko) * | 1999-12-22 | 2002-05-08 | 윤종용 | 반도체 소자의 퓨즈부 구조 및 그 형성방법 |
US6420264B1 (en) * | 2000-04-12 | 2002-07-16 | Ultratech Stepper, Inc. | Method of forming a silicide region in a Si substrate and a device having same |
US6365446B1 (en) * | 2000-07-03 | 2002-04-02 | Chartered Semiconductor Manufacturing Ltd. | Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process |
JP4051175B2 (ja) * | 2000-11-17 | 2008-02-20 | スパンション エルエルシー | 不揮発性半導体メモリ装置および製造方法 |
US6566200B2 (en) | 2001-07-03 | 2003-05-20 | Texas Instruments Incorporated | Flash memory array structure and method of forming |
US6413821B1 (en) * | 2001-09-18 | 2002-07-02 | Seiko Epson Corporation | Method of fabricating semiconductor device including nonvolatile memory and peripheral circuit |
US20050168334A1 (en) * | 2004-01-29 | 2005-08-04 | Junell Clint W. | Method and system for monitoring environmental events |
US20060156654A1 (en) * | 2005-01-20 | 2006-07-20 | Andersen Corporation | Clad window frame with improved sealing |
-
2001
- 2001-12-20 US US10/022,798 patent/US6828199B2/en not_active Expired - Lifetime
-
2002
- 2002-12-11 AU AU2002357826A patent/AU2002357826A1/en not_active Abandoned
- 2002-12-11 KR KR1020047009736A patent/KR100948199B1/ko not_active IP Right Cessation
- 2002-12-11 CN CNB028251733A patent/CN1311557C/zh not_active Expired - Lifetime
- 2002-12-11 EP EP02792367.1A patent/EP1456885B1/en not_active Expired - Lifetime
- 2002-12-11 WO PCT/US2002/039781 patent/WO2003054964A2/en active Application Filing
- 2002-12-11 JP JP2003555586A patent/JP4681227B2/ja not_active Expired - Fee Related
- 2002-12-18 TW TW091136467A patent/TWI267942B/zh not_active IP Right Cessation
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04209573A (ja) * | 1990-12-06 | 1992-07-30 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法及び半導体装置 |
JPH10335493A (ja) * | 1997-05-28 | 1998-12-18 | Nec Corp | 半導体記憶装置 |
US6156654A (en) * | 1998-12-07 | 2000-12-05 | Chartered Semiconductor Manufacturing Ltd. | Pulsed laser salicidation for fabrication of ultra-thin silicides in sub-quarter micron devices |
JP2002539611A (ja) * | 1999-03-09 | 2002-11-19 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 不揮発性メモリを有する半導体装置 |
JP2001094076A (ja) * | 1999-09-20 | 2001-04-06 | Fujitsu Ltd | 半導体集積回路装置とその製造方法 |
JP2003533884A (ja) * | 2000-05-16 | 2003-11-11 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 不揮発性メモリセルの均一なビット線のストラッピング |
JP2003163289A (ja) * | 2001-11-27 | 2003-06-06 | Mitsubishi Electric Corp | 半導体メモリの製造方法、及び該半導体メモリを含む半導体装置の製造方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005045012A (ja) * | 2003-07-22 | 2005-02-17 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP4545401B2 (ja) * | 2003-07-22 | 2010-09-15 | パナソニック株式会社 | 半導体装置の製造方法 |
JP2007329480A (ja) * | 2006-06-09 | 2007-12-20 | Samsung Electronics Co Ltd | 埋め込みビットラインの形成方法 |
JP2012142548A (ja) * | 2010-12-30 | 2012-07-26 | Sk Hynix Inc | 埋め込みビットラインを備えた半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
AU2002357826A1 (en) | 2003-07-09 |
KR100948199B1 (ko) | 2010-04-15 |
TWI267942B (en) | 2006-12-01 |
AU2002357826A8 (en) | 2003-07-09 |
WO2003054964A3 (en) | 2004-03-04 |
KR20040075021A (ko) | 2004-08-26 |
EP1456885A2 (en) | 2004-09-15 |
US6828199B2 (en) | 2004-12-07 |
EP1456885B1 (en) | 2016-10-12 |
WO2003054964A2 (en) | 2003-07-03 |
CN1605128A (zh) | 2005-04-06 |
US20030119314A1 (en) | 2003-06-26 |
TW200400588A (en) | 2004-01-01 |
JP4681227B2 (ja) | 2011-05-11 |
CN1311557C (zh) | 2007-04-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5858843A (en) | Low temperature method of forming gate electrode and gate dielectric | |
US5604367A (en) | Compact EEPROM memory cell having a floating gate transistor with a multilayer gate electrode | |
US7256444B2 (en) | Local SONOS-type nonvolatile memory device and method of manufacturing the same | |
KR100608407B1 (ko) | 비트 라인 생성 방법 및 메모리 셀 어레이 생성 방법 및메모리 셀 어레이 | |
US5852311A (en) | Non-volatile memory devices including capping layer contact holes | |
JP4681227B2 (ja) | 半導体デバイスを作製する方法 | |
US6951785B2 (en) | Methods of forming field effect transistors including raised source/drain regions | |
JP2004530296A5 (ja) | ||
JPH05136269A (ja) | プログラム可能な相互接続装置及びその製造方法 | |
US20060148177A1 (en) | Method for forming split gate flash nonvolatile memory devices | |
CN102969279B (zh) | 用于制造半导体器件的方法 | |
JPH05218075A (ja) | 半導体金属酸化物半導体装置を製作するためのプロセス | |
JPH08264668A (ja) | 不揮発性半導体記憶装置およびその製造方法 | |
JPH07115143A (ja) | 不揮発性メモリの製造方法 | |
TW586191B (en) | Method of forming a system on chip | |
JP4767604B2 (ja) | 不揮発性メモリ素子のトンネリング絶縁膜を形成する方法 | |
TW417255B (en) | Manufacturing method of self-aligned selective gate with a split-gate non-volatile memory structure | |
JP2005191489A (ja) | 半導体記憶装置およびその製造方法 | |
KR100618058B1 (ko) | 전계 효과 트랜지스터를 포함하는 반도체 디바이스의 제조방법 | |
KR100538885B1 (ko) | 플래쉬 메모리 소자의 제조 방법 | |
JPH10261773A (ja) | 不揮発性半導体記憶装置の製造方法 | |
US6500713B1 (en) | Method for repairing damage to charge trapping dielectric layer from bit line implantation | |
US20230402114A1 (en) | Semiconductor device with programmable feature | |
US20230402115A1 (en) | Method of manufacturing semiconductor device with programmable feature | |
JP2605310B2 (ja) | 不揮発性メモリセルの製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A529 | Written submission of copy of amendment under article 34 pct |
Free format text: JAPANESE INTERMEDIATE CODE: A529 Effective date: 20040616 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20040629 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20051207 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20081219 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090908 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20100130 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20100223 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100623 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20100630 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100817 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20101116 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20101124 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101216 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20110118 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20110204 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4681227 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140210 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140210 Year of fee payment: 3 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: R3D02 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |