CN1605128A - 具有埋设金属硅化物位线的金属氧氮氧半导体装置 - Google Patents

具有埋设金属硅化物位线的金属氧氮氧半导体装置 Download PDF

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CN1605128A
CN1605128A CNA028251733A CN02825173A CN1605128A CN 1605128 A CN1605128 A CN 1605128A CN A028251733 A CNA028251733 A CN A028251733A CN 02825173 A CN02825173 A CN 02825173A CN 1605128 A CN1605128 A CN 1605128A
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bit line
oxide
metal
recess
metal silicide
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CN1311557C (zh
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J·奥乌拉
M·T·拉姆斯比
A·哈利亚尔
Z·克里沃卡皮奇
M·V·恩戈
N·H·特里普萨斯
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Cypress Semiconductor Corp
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Abstract

一种金属氧氮氧半导体(MONOS)装置及其制造方法,具有形成于基材(30)上的诸如氧氮氧层(34、36、38)的电荷捕捉介电层(32),一凹部(44)系贯通该氧氮氧层(32)而形成于该基材(30)中,在该凹部(44)中形成金属硅化物位线(48)并在该金属硅化物位线(48)的上方形成位线氧化物(54),而字符线(56)则形成于该氧氮氧层(32)及该位线氧化物(54)之上,并且提供低电阻的硅化物(58)于该字符线(56)的上方,该硅化物(58)系由例如激光热退火所形成者。

Description

具有埋设金属硅化物位线的金属氧氮氧半导体装置
技术领域
本发明有关一种半导体装置制造的领域,尤指一种金属氧氮氧半导体(MONOS)单元的制造。
背景技术
参照第1图,其系显示典型的先前技术金属氧氮氧半导体(MONOS,metal oxide nitride oxide semiconductor)单元。该单元包括一基材10,在该基材10中埋置有源极12及漏极14,而在该基材10的上方则置有氧氮氧(ONO)结构16,该氧氮氧结构16具有夹设于两氧化物层18及20的间的氮化物层17,该氧氮氧结构16的上方置有栅极导体22,而在该氧氮氧结构16之下则形成一信道15于该源极12与该漏极14的间。
氮化物层17提供保留机制(retention mechanism)以编程内存单元,具体而言,当提供编程电压至源极12、漏极14以与门极导体22时,电子将朝漏极14流动。根据热电子注入现象(hot electron injectionphenomenon),部分热电子会穿透氧化硅层18的下层(尤其是该氧化物层18的下层为较薄者),然后这些热电子便聚集于氮化物层17中,如于先前技术中已众所周知者,氮化物层17保留了列于邻近漏极14的集中区域所接收的电荷24,当电荷24比该信道15的其它区域的临界值(threshold)为高时,集中的电荷24即大幅升高该内存单元的信道部份的临界值。
当存在集中的电荷24时(意即内存单元已予编程),在读取内存单元的期间,该内存单元升高的临界值会使内存单元无法进入导电的状态。若不存在集中的电荷24时,则在栅极导体22上的读取电压能克服较的为低的临界值,以转化信道15并使该信道15导电。
可在基材中植入掺杂物以形成埋设位线(buried bit lines),该等位线系受限于半导体装置的尺寸比例(scaling),并且亦受限于位线的电阻,因此亟需金属氧氮氧半导体装置中具有极低电阻的埋设位线,以藉的缩小位线的尺寸比例并且缩小内存单元的大小。
发明内容
本发明的实施例可满足此需求及其它需求,本发明提供一种制造金属氧氮氧半导体(MONOS,metal oxide nitride oxide semiconductor)装置的方法,该方法的步骤包括:于基材上形成电荷捕捉介电层;以及依照位线图案蚀刻出一贯通该电荷捕捉介电层的凹部,然后在该凹部中形成金属硅化物位线。
使用位线中的金属硅化物位线可提供电阻非常低的位线以缩小位线宽度,而缩小位线宽度可减少位线的接触频率并缩小内存单元的大小,此外,亦可提供位线的平面结构(planar architecture)。
在本发明的特定实施例中,激光热退火工艺系用以于基材中的凹部内形成金属硅化物,使用激光热退火可使金属硅化物以可控制的方式形成,其因在于激光热退火具有较低的热消耗,且激光能量能精确地施加于欲硅化的区域。
本发明的实施例提供一种包括基材、在该基材上的电荷捕捉介电层以及在该电荷捕捉介电层中的凹部的金属氧氮氧半导体装置,以符合前述的需求。其中,在该凹部中系设置有金属硅化物位线。
本发明之前述特征与其它特征、实施态样及优点将由本发明的下列详细说明结合所附图式而更为明显易懂。
附图说明
第1图为显示先前技术的金属氧氮氧半导体内存单元的示意图。
第2图为在基材上形成氧氮氧层后的金属氧氮氧半导体装置的部份横断面图。
第3图显示根据本发明的实施例在氧氮氧层上形成位线光罩后的第2图的结构。
第4图说明根据本发明的实施例将凹部蚀刻通过该氧氮氧层并进入该基材中之后的第3图的结构。
第5图显示沉积耐火金属层后的第4图的结构。
第6图说明于根据本发明的实施例进行退火处理以形成金属硅化物后并于其后将未反应的金属从结构中移除的第5图的结构。
第7图显示根据本发明的实施例遮盖并植入源极/漏极区后的第6图的结构。
第8图说明根据本发明的实施例在金属硅化物位线之上形成位线氧化物后的第7图的结构。
第9图说明根据本发明的实施例已将多晶硅字符线沉积于该氧氮氧层以及该位线氧化物之上后的第8图的结构。
第10图说明根据本发明的实施例将低电阻硅化物形成于多晶硅字符线上后的第9图的结构。
第11图显示本发明的另一实施例。
具体实施方式
本发明系用以解决与具有埋设位线的金属氧氮氧半导体装置有关的问题,具体而言,本发明降低在金属氧氮氧半导体装置中的埋设位线的电阻,而这些位线通常是由植入离子所形成,透过这些金属硅化物位线的形成,本发明可产生电阻极低的位线及缩小该些位线的宽度,并且减少这些位线的接触频率。再者,使用金属硅化物位线可缩小内存单元的大小。
第2图为一具有基材30的金属氧氮氧半导体的单元结构的部份的横断面图,在第2图中的基材30为P型基材(P-substrate)。该基材30系覆盖有电荷捕捉介电层32,在下列的实施例中,该电荷捕捉介电层32系称为氧氮氧层32,然而,在本发明的其它实施例中,可应用其它类型的电荷捕捉层,诸如氧化物/氧氮硅化物/氧化物层等为熟习该项技艺者所周知者。作为说明氧氮氧层32的实施例,一底层氧化物层34系于该基材30之上成长出所欲的厚度,之后于该底层氧化物层34之上沉积氮化物层36,再藉由氮化物的氧化、或沉积或两者的结合而产生上层氧化物层38。该氧氮氧层32的形成乃为熟习该项技艺者已周知者,并且可应用任何习知的方法技术来产生该氧氮氧层32。
接下来的步骤包括沉积位线光罩40(通常以习知方式将光阻42图案化),用以在芯片的记忆数组部份内的布线(layout)形成出位线,以及形成源极线以及漏极线。第3图的侧视图显示记忆数组部份内的金属氧氮氧半导体的部份具有图案化的光阻42,位线光罩40的光阻42纵列定义出未设置位线的区域,这些区域即为该装置的信道的形成位置。
参阅第4图,该氧氮氧层32系依照该位线光盖40而蚀刻贯穿,持续该蚀刻处理以穿透该氧氮氧层32并且进入该基材30至一特定深度,该蚀刻步骤可应用反应离子蚀刻的非等向蚀刻(anisotropic etch)。在进行蚀刻步骤之后,藉由习知的光阻移除技术将该位线光罩40予以移除。
在完成蚀刻工艺以于基材30中形成凹部44之后,于该基材30及该氧氮氧层32之上沉积耐火金属层46,该耐火金属层46可为一些诸如钨、钴、镍、钛、铂、钯等的任何不同的材料,已知这些金属可与硅反应以形成金属硅化物,而该耐火金属层46的沉积则可以习知的方式进行。
第6图显示第5图的结构在进行退火步骤后于该凹部44内形成金属硅化物位线48的结构。该金属硅化物位线48宜为以低电阻态(lowresistance phase)的特定金属硅化物所形成者,可应用快速热退火(RTA,rapid thermal annealing)工艺,使该耐火金属层46在该基材30中与硅反应以形成金属硅化物。然而,在本发明的特定实施例中,亦可使用激光热退火(LTA,laser thermal annealing)工艺以使金属与硅反应,在第7图中的箭头50即指出此工艺。使用激光热退火形成金属硅化物的部份优点在于激光热退火的热消耗较低,并且以激光热退火可精确控制施加激光能量的区域,换言的,激光能量可直接而精确地施加于该凹部44以退火金属硅化物。
激光的能量密度(energy fluence)乃熟习该项技艺者可轻易地决定者,并将视所欲形成的金属硅化物的类型、所欲的金属硅化物的厚度等而定,激光热退火的参数举例而言,包括提供在约50mJ/cm2至约1.3J/cm2的间的能量密度。
第6图亦显示在已完成退火工艺且已形成金属硅化物之后将任何未反应的金属从结构中移除后的结构,该等未反应物的移除技术乃熟习该项技艺者已周知者,而可视已形成的金属硅化物的特定类型而定。
在第7图中,进行离子植入工艺以于该基材30中形成源极/漏极区52,该源极/漏极区52系经由该金属硅化物位线48植入砷而形成者,使得该源极/漏极区52位于该金属硅化物位线48的下。习用的光罩及植入工艺可用来形成该源极/漏极区52,熟习该项技艺者可选择适当的使用量(dosage)与植入能量,然而,应了解的是当使用自我对准的植入物,以由该植入物自行对准至氧氮氧结构时,则不一定须要该光罩步骤。
虽然在本实施例中所说明的离子植入工艺系于进行硅化(silicidation)工艺之后实施,但在本发明的其它实施例中,可在硅化工艺之前进行离子植入,举例来说,在形成位线光罩40之后,施予适当选定的植入能量,能植入该掺杂物。然而,较佳实施例系于蚀刻后立刻植入掺杂物,藉此避免移除已植入的不欲移除的掺杂物。
如第8图所示,位线氧化物54系形成该金属硅化物位线48的上方的凹部44中,该位线氧化物54可在氧化操作中热成长于该金属硅化物位线48之上,而氧化工艺可为约800℃的低温氧化。另外,亦可沉积该位线氧化物54,在形成该位线氧化物54之后,可在该位线氧化物54及该氧氮氧层32之上沉积多晶硅或金属的字符线56,多晶硅的字符线56系依字符线光罩(显示于第9图)而形成,而该位线氧化物54则可包含该氧氮氧层32的上层氧化物层38的部份或全部。
接着提供低电阻的硅化物58于该多晶硅的字符线56的上方,此硅化物58的形成可藉由沉积耐火金属在该多晶硅的字符线56上及退火(例如快速热退火或激光热退火)所完成,不在多晶硅上的金属则将覆盖该氧氮氧层32的氧化物或该位线氧化物54,因此不会与氧化物反应而形成金属硅化物,而未反应的金属可由习知技术移除。
如在第10图中的所得结构所说明者,本发明的方法技术系提供具有埋设金属硅化物位线48的金属氧氮氧半导体装置,所创造出的金属氧氮氧半导体装置具有极低电阻的位线、可提高装置效能以及允许位线宽度的缩小并且亦可缩小内存单元的尺寸,再者,亦可降低该位线的接触频率,而本结构的另一个优点则为金属硅化物位线的使用系提供了平面结构。
在另一个实施例中,如第11图所说明者,并未蚀刻该基材30,而仅将该氧氮氧层32形成于该基材30上,而该金属硅化物位线48系形成于该基材30上。
虽然已详细说明及显示本发明,但应清楚了解的是这些详细说明与显示仅为图式说明及范例,而且并非以此为限,本发明的范畴系以所附的申请专利范围所界定。

Claims (13)

1.一种形成金属氧氮氧半导体(MONOS,metal oxide nitride oxidesemiconductor)装置的方法,该方法包括下列步骤:
在基材(30)上形成电荷捕捉介电层(32);
依照位线图案蚀刻出一贯穿该电荷捕捉介电层(32)的凹部(44);以及
在该凹部(44)中形成金属硅化物位线(48)。
2.如权利要求1所述的形成金属氧氮氧半导体装置的方法,其中,该形成金属硅化物位线(48)的步骤包括:
在该凹部(44)中沉积耐火金属层(46);以及
在该凹部(44)内进行激光热退火以在该凹部(44)中形成金属硅物化位线(48)。
3.如权利要求2所述的形成金属氧氮氧半导体装置的方法,还包括在该基材(30)中植入掺杂物以在该金属硅化物位线(48)之下形成源极/漏极区52。
4.如权利要求3所述的形成金属氧氮氧半导体装置的方法,还包括在该凹部中形成在该金属硅化物位线之上的氧化物层(54)。
5.如权利要求2所述的形成金属氧氮氧半导体装置的方法,其中,该激光热退火的步骤包括施加具有在约50mJ/cm2至约1.3J/cm2的间的能量密度的激光能量。
6.如权利要求1所述的形成金属氧氮氧半导体装置的方法,其中,该电荷捕捉介电层(32)为氧氮氧层。
7.一种金属氧氮氧半导体(MONOS),包括:
基材(30);
在该基材(30)上的电荷捕捉介电层(32);
在该电荷捕捉介电层(32)中的凹部(44);以及
在该凹部中(44)的金属硅化物位线(48)。
8.如权利要求7所述的金属氧氮氧半导体,其中,该金属硅化物位线(48)为埋设位线。
9.如权利要求8所述的金属氧氮氧半导体,还包括在该凹部中的金属硅化物位线上的氧化物以及在该电荷捕捉介电层与氧化物之上的字符线。
10.如权利要求9所述的金属氧氮氧半导体,还包括在该金属硅化物位线下的源极/漏极区。
11.如权利要求10所述的金属氧氮氧半导体,其中,该金属硅化物位线包括激光热退火的金属硅化物。
12.如权利要求11所述的金属氧氮氧半导体,其中,该电荷捕捉介电层为氧氮氧(ONO)层。
13.如权利要求12所述的金属氧氮氧半导体,其中,该凹部延伸入该基材中且该金属硅化物位线系在该凹部中。
CNB028251733A 2001-12-20 2002-12-11 具有埋设金属硅化物位线的金属氧氮氧半导体装置 Expired - Lifetime CN1311557C (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102569201A (zh) * 2010-12-30 2012-07-11 海力士半导体有限公司 制造具有掩埋位线的半导体器件的方法

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4545401B2 (ja) * 2003-07-22 2010-09-15 パナソニック株式会社 半導体装置の製造方法
US20060084268A1 (en) * 2004-10-15 2006-04-20 Martin Verhoeven Method for production of charge-trapping memory cells
DE112005003421T5 (de) * 2005-01-24 2008-01-17 Spansion Llc, Sunnyvale Halbleiterbauelement und Verfahren zu dessen Herstellung
US8435873B2 (en) * 2006-06-08 2013-05-07 Texas Instruments Incorporated Unguarded Schottky barrier diodes with dielectric underetch at silicide interface
KR100739532B1 (ko) * 2006-06-09 2007-07-13 삼성전자주식회사 매몰 비트라인 형성 방법
US7678654B2 (en) * 2006-06-30 2010-03-16 Qimonda Ag Buried bitline with reduced resistance
US8642441B1 (en) 2006-12-15 2014-02-04 Spansion Llc Self-aligned STI with single poly for manufacturing a flash memory device
US8486782B2 (en) 2006-12-22 2013-07-16 Spansion Llc Flash memory devices and methods for fabricating the same
KR101149043B1 (ko) * 2009-10-30 2012-05-24 에스케이하이닉스 주식회사 매립형 비트라인을 구비하는 반도체 장치 및 그 제조방법
US8853768B1 (en) 2013-03-13 2014-10-07 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating MONOS semiconductor device
KR102600998B1 (ko) 2016-09-28 2023-11-13 삼성전자주식회사 반도체 장치
CN110021559B (zh) * 2018-01-09 2021-08-24 联华电子股份有限公司 半导体元件及其制作方法

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5168334A (en) 1987-07-31 1992-12-01 Texas Instruments, Incorporated Non-volatile semiconductor memory
EP0368097A3 (en) 1988-11-10 1992-04-29 Texas Instruments Incorporated A cross-point contact-free floating-gate memory array with silicided buried bitlines
JP2957283B2 (ja) * 1990-12-06 1999-10-04 株式会社東芝 不揮発性半導体記憶装置及びその製造方法及び半導体装置
US5670297A (en) 1991-12-30 1997-09-23 Sony Corporation Process for the formation of a metal pattern
JP2964993B2 (ja) * 1997-05-28 1999-10-18 日本電気株式会社 半導体記憶装置
US6350643B1 (en) * 1997-12-18 2002-02-26 Advanced Technology Materials, Inc. Reduced degradation of metal oxide ceramic due to diffusion of a mobile specie therefrom
US6121134A (en) * 1998-04-21 2000-09-19 Micron Technology, Inc. High aspect ratio metallization structures and processes for fabricating the same
TW379417B (en) * 1998-06-04 2000-01-11 United Semiconductor Corp Buried bitline structure and the manufacture method
US6261908B1 (en) 1998-07-27 2001-07-17 Advanced Micro Devices, Inc. Buried local interconnect
US6355543B1 (en) * 1998-09-29 2002-03-12 Advanced Micro Devices, Inc. Laser annealing for forming shallow source/drain extension for MOS transistor
US6483736B2 (en) * 1998-11-16 2002-11-19 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
US6156654A (en) 1998-12-07 2000-12-05 Chartered Semiconductor Manufacturing Ltd. Pulsed laser salicidation for fabrication of ultra-thin silicides in sub-quarter micron devices
EP1080499A1 (en) * 1999-03-09 2001-03-07 Koninklijke Philips Electronics N.V. Semiconductor device comprising a non-volatile memory
KR100325472B1 (ko) * 1999-04-15 2002-03-04 박종섭 디램 메모리 셀의 제조 방법
US6210995B1 (en) * 1999-09-09 2001-04-03 International Business Machines Corporation Method for manufacturing fusible links in a semiconductor device
JP3762584B2 (ja) * 1999-09-20 2006-04-05 富士通株式会社 半導体集積回路装置
DE19946435A1 (de) * 1999-09-28 2001-04-05 Infineon Technologies Ag Integrierter Halbleiter-Festwertspeicher
US6177318B1 (en) * 1999-10-18 2001-01-23 Halo Lsi Design & Device Technology, Inc. Integration method for sidewall split gate monos transistor
US6248635B1 (en) * 1999-10-25 2001-06-19 Advanced Micro Devices, Inc. Process for fabricating a bit-line in a monos device using a dual layer hard mask
US6326268B1 (en) * 1999-10-25 2001-12-04 Advanced Micro Devices, Inc. Method of fabricating a MONOS flash cell using shallow trench isolation
US6248633B1 (en) * 1999-10-25 2001-06-19 Halo Lsi Design & Device Technology, Inc. Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory
KR100335498B1 (ko) * 1999-12-22 2002-05-08 윤종용 반도체 소자의 퓨즈부 구조 및 그 형성방법
US6420264B1 (en) * 2000-04-12 2002-07-16 Ultratech Stepper, Inc. Method of forming a silicide region in a Si substrate and a device having same
US6275414B1 (en) * 2000-05-16 2001-08-14 Advanced Micro Devices, Inc. Uniform bitline strapping of a non-volatile memory cell
US6365446B1 (en) * 2000-07-03 2002-04-02 Chartered Semiconductor Manufacturing Ltd. Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process
JP4051175B2 (ja) * 2000-11-17 2008-02-20 スパンション エルエルシー 不揮発性半導体メモリ装置および製造方法
US6566200B2 (en) 2001-07-03 2003-05-20 Texas Instruments Incorporated Flash memory array structure and method of forming
US6413821B1 (en) * 2001-09-18 2002-07-02 Seiko Epson Corporation Method of fabricating semiconductor device including nonvolatile memory and peripheral circuit
JP2003163289A (ja) * 2001-11-27 2003-06-06 Mitsubishi Electric Corp 半導体メモリの製造方法、及び該半導体メモリを含む半導体装置の製造方法
US20050168334A1 (en) * 2004-01-29 2005-08-04 Junell Clint W. Method and system for monitoring environmental events
US20060156654A1 (en) * 2005-01-20 2006-07-20 Andersen Corporation Clad window frame with improved sealing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102569201A (zh) * 2010-12-30 2012-07-11 海力士半导体有限公司 制造具有掩埋位线的半导体器件的方法

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