TW569396B - Flash memory and fabricating method thereof - Google Patents
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- TW569396B TW569396B TW091134414A TW91134414A TW569396B TW 569396 B TW569396 B TW 569396B TW 091134414 A TW091134414 A TW 091134414A TW 91134414 A TW91134414 A TW 91134414A TW 569396 B TW569396 B TW 569396B
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000010410 layer Substances 0.000 claims description 130
- 239000004020 conductor Substances 0.000 claims description 37
- 238000007667 floating Methods 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 239000011229 interlayer Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 239000004575 stone Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 230000005641 tunneling Effects 0.000 claims description 4
- 150000002739 metals Chemical class 0.000 claims 2
- 229910052790 beryllium Inorganic materials 0.000 claims 1
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 1
- 239000002019 doping agent Substances 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000005530 etching Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- 238000005496 tempering Methods 0.000 description 2
- 101100136092 Drosophila melanogaster peng gene Proteins 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007670 refining Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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Abstract
Description
569396569396
所屬之技術 ,本發明疋有關於一種快閃(f 1 a s h)記憶體的結構及其 製造方法,且特別是有關於一種具有埋入式浮置閘極極的 快閃記憶體的結構及其製造方法。 先前拮術 非揮發性記憶體(n 0 n v 0 1 a t i 1 e memory)中的快閃記憶 體由於具有可進行多次資料之存入、讀取、抹除等動作, 且存入之資料在斷電後也不會消失之優點,所以已成為個 人電腦和電子設備所廣泛採用的一種記憶體元件。 典型的快閃記憶體係在基底(即基底表面)上形成浮 置問極(Floating Gate)與控制閘極(Control Gate)。其 中浮置閘極位於控制閘極和基底之間,且處於浮置狀態', 沒有任何偏壓。而控制閘極則與字元線(w〇rd Une)相 接。此外,還包括位於基底和浮置閘極之間的穿隧氧化層 (Tunneling Oxide)和位於浮置閘極和控制閘極之間的多 曰日石夕間介電層(inter-poly dielectric layer) 〇 由習知之快閃記憶體結構可知,由於習知的快閃記憶 體之閘極結構的各元件皆位於基底表面上,因此,閘極結 構之厚度係為各元件之厚度總和(亦即,穿隧氧化層、浮 置閘極、多晶矽間介電層、控制閘極等厚度的總和)。 因而,在形成層間絕緣層等的後續製程中,此層間絕 緣層會因習知快閃記憶體所具有之厚度而具有較大之厚 度’因而具有較大的深寬比(high aspect ratio),進而 導致後續製程之與源極/汲極區相接觸的接觸窗等不易於According to the related technology, the present invention relates to a structure of a flash memory (f 1 ash) and a manufacturing method thereof, and more particularly, to a structure of a flash memory with an embedded floating gate electrode and manufacturing method thereof. method. The flash memory in the previously non-volatile non-volatile memory (n 0 nv 0 1 ati 1 e memory) can perform multiple operations such as storing, reading, and erasing data, and the stored data is stored in The advantage that it will not disappear even after power off, so it has become a kind of memory element widely used in personal computers and electronic devices. A typical flash memory system forms a floating gate and a control gate on a substrate (ie, the substrate surface). The floating gate is located between the control gate and the substrate and is in a floating state 'without any bias. The control gate is connected to the word line Unor. In addition, it also includes a tunneling oxide layer between the substrate and the floating gate, and an inter-poly dielectric layer between the floating gate and the control gate. ) 〇 From the conventional flash memory structure, it can be known that since the components of the gate structure of the conventional flash memory are located on the substrate surface, the thickness of the gate structure is the sum of the thicknesses of the components (ie , The thickness of the tunnel oxide layer, the floating gate, the polycrystalline silicon interlayer dielectric layer, the control gate, etc.). Therefore, in the subsequent processes of forming an interlayer insulating layer, etc., the interlayer insulating layer will have a larger thickness due to the thickness of the conventional flash memory, and thus has a higher aspect ratio, and thus It is not easy to make the contact window etc. contacting the source / drain region in subsequent processes
9871twfl.ptd 第6頁 569396 、發明說明(2) 此層間絕緣層中形成。 發明内交 因此本發明的目的就是在提供一種快閃記憶體,以降 低問極結構之突出基底的高度,而使後續製程可輕易進 行。 本發明的再一目的是提供一種快閃記憶體,以減少製 程步驟及時間。9871twfl.ptd Page 6 569396, Description of Invention (2) This interlayer insulation layer is formed. Inventing the invention Therefore, the object of the present invention is to provide a flash memory to reduce the height of the protruding substrate of the interrogation structure, so that subsequent processes can be easily performed. Another object of the present invention is to provide a flash memory to reduce the process steps and time.
本發明提出一種快閃記憶體之製造方法,係於一基底 上形成開口,再於基底上形成第一介電層。之後,於第一 介電層上形成第一導體層,且此第一導體層填滿開口。接 著’於第一導體層兩侧基底中形成源極/汲極區,此源極/ 沒極區之深度係比開口之深度還深。之後,於基底上形成 第二介電層,再於第二介電層上形成第二導體層。接著, 圖案化第二導體層,以使圖案化後的第二導體層位於第一 導體層上方。The invention provides a method for manufacturing a flash memory, which comprises forming an opening on a substrate and forming a first dielectric layer on the substrate. After that, a first conductor layer is formed on the first dielectric layer, and the first conductor layer fills the opening. Next, a source / drain region is formed in the substrate on both sides of the first conductor layer, and the depth of the source / dead region is deeper than the depth of the opening. After that, a second dielectric layer is formed on the substrate, and then a second conductor layer is formed on the second dielectric layer. Next, the second conductor layer is patterned so that the patterned second conductor layer is positioned above the first conductor layer.
在上述製程步驟中,由於本發明之浮置閘(即第一導 體層)係直接形成於基底中而不需額外的微影蝕刻步驟, 因此’本發明之製程可減少製程步驟(至少減少一道微影 蚀刻的步驟),進而大幅縮短製程時間。 本發明另提出一種快閃記憶體,係由具有開口的基 底、位於開口内的浮堇閘極、位於浮置閘極上的控制閘 極、位於浮置閘極兩侧基底中的源極/沒極區、位於浮置 閘極與基底之間的穿隧氧化層、以及位於浮置閘極與控制 閘極之間的多晶矽間介電層所構成。另外,在前述結構In the above process steps, since the floating gate (ie, the first conductor layer) of the present invention is directly formed in the substrate without an additional lithography etching step, the process of the present invention can reduce the number of process steps (at least one Lithography etching step), which further shortens the process time. The invention further provides a flash memory, which is composed of a substrate with an opening, a floating gate located in the opening, a control gate located on the floating gate, and a source / injection located in the substrate on both sides of the floating gate. A polar region, a tunneling oxide layer between the floating gate and the substrate, and a polycrystalline silicon interlayer dielectric layer between the floating gate and the control gate. In addition, in the aforementioned structure
569396 五、發明說明(3) 中:汲極區之深度係比開 本發明因採用將浮極於木度還^, 閘極埋入基底中)的沾閘椏办成於開口内(亦即,浮置 基底的高度僅為控制;f:因此,記憶體之閘極結構突出 可大幅降低整體閘=椹多曰:曰:間介電層的厚度總和,故 結構之層間絕緣層的;;’並可降低後續覆蓋閘極 之元件。 、卜’進而可以輕易形成後續製程 為讓本發明之上述 顯易懂,下文特舉一較#.二的特徵、和優點能更明 細說明如下: 車乂佳實施例,並配合所附圖式,作詳 實施方式 第1Α圖至第1G圖係繪示依照本發明之一 圖。第2A圖至第%圖係分別繪示第 1 A圖至第1 G圖之I — I線的剖面圖。 請同時參照第1A圖及第“圖,提供一已 ^的基底100,並於基底100上形成塾氧化層 墊氧化層102上形成圖案化光阻層1〇4。基底1〇〇例如是由 的ί材。隔離結構101例如是場氧化層 隔離〜構。墊氡化層丨02之形成方法例如是以熱氧化法氧 化基底100而得。圖案化光阻層104的形成方法例如是先於 墊氧化層1 02上形成一層光阻材料,再以微影法圖此 光阻材料而成。 μ 接著’請同時參照第1Β圖與第2Β圖,以光阻層1〇4為 罩幕’移除未被覆蓋的墊氧化層102及部分基底1〇〇,以於 569396 五、發明說明(4)569396 V. Description of the invention (3): The depth of the drain region is higher than that of the present invention. Because the floating electrode is used to restore the woodness, and the gate is buried in the substrate, the gate is built into the opening (ie , The height of the floating substrate is only for control; f: Therefore, the protruding gate structure of the memory can greatly reduce the overall gate = 椹 多: said: the sum of the thickness of the dielectric layer, so the structure of the interlayer insulation layer; 'It can reduce the components that cover the gate in the future. Then, the subsequent process can be easily formed. In order to make the above description of the present invention easier to understand, the features and advantages of the first one compared with #. 二 can be explained in more detail as follows: The best embodiment and the accompanying drawings make detailed implementation. Figures 1A to 1G are drawings according to the present invention. Figures 2A to %% are drawings 1A to 1 1 G, Section I—I. Please refer to Figures 1A and "" at the same time, provide a substrate 100, and form a hafnium oxide layer on the substrate 100 to form a patterned photoresist on the oxide layer 102. Layer 104. The substrate 100 is, for example, made of aluminum. The isolation structure 101 is, for example, a field oxide layer. The method for forming the padding layer 02 is, for example, obtained by oxidizing the substrate 100 by a thermal oxidation method. The method for forming the patterned photoresist layer 104 is, for example, forming a photoresist material before the pad oxide layer 102. Then use photolithography to map this photoresist material. Μ Then 'Please refer to Figure 1B and Figure 2B at the same time, using the photoresist layer 104 as the cover' to remove the uncovered pad oxide layer 102 and part Base 100, with 569396 V. Description of the invention (4)
基底1 0 0中形成多個開σ 1 n R IB BI拼1达開口106之開口形狀如同第 丄β圖所不係為矩形,然並 指眘W制你 I不以此為限,其開口形狀也可以 現實際製程之需要而變更為久 η ^ ^ 2 ^更為各種形狀。之後,移除殘留之 尤阻層104及墊氧化層1〇2。 赤人睛同時參照第Κ圖及第2C圖,於基底100上形 J )丨電層108,此介電層108未填滿開口1〇6。,於介 形成導體層11G,且此導體層110填滿開口⑽。 體層110之材質例如是摻雜多晶矽。導體層11〇之形成方 去例如是化學氣相沈積法(chemical vapQr (^POSI tion),具體而言,係以化學氣相沈積法沈積多晶 並於沈積之過程中將摻質摻入多晶矽中,以形成摻雜 多晶矽。介電層108係用以作為穿隧氧化層。介電層1〇8之 形成方法例如是熱氧化法。 接著,請同時參照第1D圖與第2D圖,移除開口 1〇6之 外的導體層1 1 0,而形成作為浮置閘極的導體層丨丨〇A。移 除開口106之外的導體層110的方法例如是化學機械研磨法 (chemical mechanical polishing)、回蝕刻法等。具體 而言,例如是以化學機械研磨法移除導體層丨丨〇,直到暴 路出介電層108或基底100為止,即形成導體層11〇A。 之後’請同時參照第1E圖與第2E圖,將摻質植入導體 層110A兩侧的基底1〇〇中,以於基底1〇〇中形成源極/汲極 區1 1 2。其中’源極/没極區1 1 2的深度係比開口 1 〇 6之深戶 還深。用以形成源極/汲極區Π 2的摻質離子包括N型或p型 摻質離子,N型或P型摻質離子例如是磷離子、砷離子、石朋 _ 9871twfl.ptd 第9頁 569396A plurality of openings σ 1 n R IB BI are formed in the base 1 0 0 to reach the opening 106. The shape of the opening 106 is not rectangular as shown in the figure 丄 β. However, it is pointed out that you are not limited to this, and its opening is not limited. The shape can also be changed to various shapes depending on the needs of the actual manufacturing process. After that, the remaining resist layer 104 and the pad oxide layer 102 are removed. With naked eyes, referring to FIG. K and FIG. 2C, a dielectric layer 108 is formed on the substrate 100, and the dielectric layer 108 does not fill the opening 106. A conductive layer 11G is formed in the dielectric, and the conductive layer 110 fills the opening ⑽. The material of the bulk layer 110 is, for example, doped polycrystalline silicon. The formation method of the conductive layer 11 is, for example, a chemical vapour deposition method (chemical vapQr (^ POSItion)). Specifically, the chemical vapor deposition method is used to deposit polycrystals and dopants are doped into the polycrystalline silicon during the deposition In order to form doped polycrystalline silicon, the dielectric layer 108 is used as a tunneling oxide layer. The method for forming the dielectric layer 108 is, for example, a thermal oxidation method. Next, please refer to FIG. 1D and FIG. 2D at the same time. A conductor layer 1 10 other than the opening 10 is formed as a conductor layer serving as a floating gate. A method of removing the conductor layer 110 outside the opening 106 is, for example, a chemical mechanical polishing method. polishing), etch-back method, etc. Specifically, for example, the conductive layer is removed by chemical mechanical polishing until the dielectric layer 108 or the substrate 100 is blown out, that is, the conductive layer 11A is formed. Please refer to FIG. 1E and FIG. 2E at the same time, implanting dopants into the substrate 100 on both sides of the conductor layer 110A to form a source / drain region 1 12 in the substrate 100. Among them, the source / The depth of the pole area 1 12 is deeper than the depth of the opening 106. Used to shape The source / drain regions 2 Π dopant ions include N-type or p-type dopant ions, an N-type or P-type dopant ions such as phosphorus ions, arsenic ions, stone Peng _ 9871twfl.ptd page 9 569 396
離子等1前述摻質植入的方法例如是以圖案化的光阻層 (未圖不)為罩幕,將摻質植入導體層11 0A兩侧的基底 100 中。 - 接著’進行熱回火步驟,以使源極/汲極區丨丨2的摻質 活性化。其熱回火的方法例如是快速熱製程(Rap i d Thermal ProCessing , RTP)法。 之後,請同時參照第IF圖與第2F圖,於基底100上形 成介電層114,且此介電層114至少覆蓋導體層11〇人。介電 層11 4係用以作為多晶矽間介電層,具體而言介電層1 1 & 例如是氧化物層、氮化物層、氮化物—氧化物(N〇)層、 氧化物—氮化物-氧化物(0N0 )層等。 田 接著,於介電層114上形成導體層116。此導體層U6 ΠL例如是摻雜多晶石夕、金屬石夕化物、或導電金屬等。 導體層116之形成方法例如是化學氣相沈積法,且體而 化!氣相沈積法沈積多晶石夕以形成多晶石夕層,再 將4貪摻入多晶矽層中,以形成摻雜多晶矽層。 之後,言青同時參照第1G圖及第%圖,圖;化 ,而於導體層U0A上方形成作為控制閉極的 曰 116A。圖案化導體層116的方法例如 曰 圖案化光阻層(未圖示),再以此光^= 分導體層116,而暴露出介電層114。 移除4 在上述本發明之快閃記憶體之製造方法中, 微影蝕刻步驟,即可完成浮置閘極之定義,因旅次 快閃記憶體之製造方法所需之步驟係少於習知技::, V J/The aforementioned dopant implantation method of ions, etc. 1 uses, for example, a patterned photoresist layer (not shown) as a mask to implant dopants into the substrate 100 on both sides of the conductor layer 110A. -Next, a thermal tempering step is performed to activate the dopant of the source / drain region 2. The thermal tempering method is, for example, a rapid thermal process (Rap d Thermal ProCessing, RTP) method. After that, please refer to FIG. IF and FIG. 2F at the same time to form a dielectric layer 114 on the substrate 100, and this dielectric layer 114 covers at least the conductor layer 110. The dielectric layer 11 4 is used as a polycrystalline silicon interlayer dielectric layer. Specifically, the dielectric layer 1 1 is, for example, an oxide layer, a nitride layer, a nitride-oxide (N0) layer, and an oxide-nitrogen layer. Compound-oxide (0N0) layer and the like. Next, a conductor layer 116 is formed on the dielectric layer 114. The conductor layer U6 ΠL is, for example, doped polycrystalline stone, metal stone compound, or conductive metal. The method for forming the conductive layer 116 is, for example, a chemical vapor deposition method, and it is physical! The polycrystalline silicon layer is deposited by a vapor deposition method to form a polycrystalline silicon layer, and then the polycrystalline silicon layer is doped into a polycrystalline silicon layer to form a doped polycrystalline silicon layer. After that, Yan Qing referred to both the 1G diagram and the% diagram at the same time, and 116A was formed as a control closed pole above the conductor layer U0A. A method of patterning the conductive layer 116 is, for example, patterning a photoresist layer (not shown), and then dividing the conductive layer 116 with the light ^ = to expose the dielectric layer 114. Removal 4 In the flash memory manufacturing method of the present invention described above, the lithography etching step can complete the definition of the floating gate, because the steps required for the flash memory manufacturing method are less than the conventional method. Knowledge ::, VJ /
569396569396
因而 需要二次微影蝕刻步驟才可完成浮置閘極之定義 可以大幅縮短製程時間。Therefore, a secondary lithography etching step is required to complete the definition of the floating gate, which can greatly reduce the process time.
請同時參照第1G圖及第2G圖,本發明之快閃記憶體係 由具有開口 106的基底100、位於開口 106内的導體層丨1〇A (、子置閘極)、位於浮置閘極丨丨0 A上的導體層丨丨6 A (控制 閘極)、位於導體層11 ο A兩側基底丨〇 〇中的源極/汲極區 1^12、位於導體層11〇A與基底1〇〇之間的介電層(穿隧 氧化層)、以及位於導體層11(^與導體層116八之間的介電 層1 1 4 (多晶矽間介電層)所構成。Please refer to FIG. 1G and FIG. 2G at the same time. The flash memory system of the present invention is composed of a substrate 100 having an opening 106, a conductor layer located in the opening 106, 10A (and a sub-gate), and a floating gate.丨 丨 0 A conductor layer 丨 丨 6 A (control gate), source / drain region 1 ^ 12 in the substrate on both sides of the conductor layer 11 ο A, located in the conductor layer 11A and the substrate A dielectric layer (tunneled oxide layer) between 100 and a dielectric layer 11 (polycrystalline silicon interlayer dielectric layer) between the conductive layer 11 (the conductive layer 116 and the conductive layer 116).
另外,在前述結構中,源極/汲極區丨丨2之深度係比開 口 106之深度還深。再者,於圖式中雖以介電層1〇8覆蓋基 底1 00為例,然並不以此為限,也可以視製程之需要而改 以介電層114覆蓋基底1〇〇。 由前述可 層110A )係形 )’因此,整 體層1 16A )與 整體閘極結構 絕緣層的深寬 雖然本發 以限定本發明 神和範圍内, 護範圍當視後 田 成於基 個閘極 多晶矽 之高度 比,進 明已以 ’任何 當可作 附之中 於本發明 底中(亦 結構突出 間介電層 ,並可降 而可以輕 一較佳實 熟習此技 些許之更 請專利範 之介電層 即,將浮 基底的南 的厚度總 低後續覆 易形成後 施例揭露 藝者,在 動與潤飾 圍所界定 置閘極 度僅為 和,故 盍閘極 續製程 如上, 不脫離 ’因此 者為準 閘極(導選 埋入基底中 控制閘(導 可大幅降伯 結構之層間 之元件。 然其並非用 本發明之賴 本發明之‘僻In addition, in the foregoing structure, the depth of the source / drain region 2 is deeper than the depth of the opening 106. Furthermore, although the dielectric layer 108 is used to cover the substrate 100 as an example in the drawings, it is not limited to this. The dielectric layer 114 may be used to cover the substrate 100 as needed in the process. From the aforementioned layer 110A) system) 'Therefore, the depth of the overall layer 116A) and the insulation structure of the overall gate structure Although the present invention is to limit the scope of the invention, the protection range is considered to be after the field is formed on the base gate The height ratio of polycrystalline silicon has been added to the bottom of the present invention as 'anything can be attached' (also the structure highlights the interlayer dielectric layer, and can be lowered so that you can learn this technology a little better and more patent-pending. The dielectric layer is that the thickness of the south of the floating base is always low and the subsequent overlay is easy to form. The example reveals that the artist has only set the gate limit as defined by the moving and refining fence. Therefore, the gate gate continues the process as above and does not leave. Therefore, it is the quasi-gate (guide buried in the substrate to control the gate), which can greatly reduce the interlayer components of the structure. However, it is not used by the invention.
569396 圖式簡單說明 第1 A圖至第1 G圖是本發明之一較佳實施例之快閃記憶 體製造流程的上視圖。 第2A圖至第2G圖分別是第1 A圖至第1 G圖之I - Γ線的剖 面圖。 圖式標示說明 100 :基底 1 0 1 :隔離結構 1 0 2 :墊氧化層 104 :圖案化光阻層 106 :開口 © 108 :介電層 1 10 :導體層 1 10A :浮置閘極 1 1 2 :源極/汲極區 1 1 4 :介電層 116 :導體層 116A :控制閘極569396 Brief Description of Drawings Figures 1A to 1G are top views of a flash memory manufacturing process according to a preferred embodiment of the present invention. Figures 2A to 2G are cross-sectional views taken along lines I-Γ in Figures 1 A to 1 G, respectively. Description of drawings: 100: substrate 1 0: isolation structure 102: pad oxide layer 104: patterned photoresist layer 106: opening © 108: dielectric layer 1 10: conductor layer 1 10A: floating gate electrode 1 1 2: source / drain region 1 1 4: dielectric layer 116: conductor layer 116A: control gate
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