TW569396B - Flash memory and fabricating method thereof - Google Patents

Abstract

A method for fabricating a flash memory comprises: an opening is formed in a substrate; a first dielectric layer is formed on the substrate; a first conductive layer is formed on the first dielectric layer, and the first conductive layer fills the opening; a source/drain region is formed in the substrate between the first conductive layer, and the depth of the source/drain region is more than the depth of the opening; a second dielectric layer is formed on the substrate; a second conductive layer is formed on the second dielectric layer; the second conductive layer is patterned, and the patterned second conductive layer is above the first conductive layer. Using the method, the process steps and process time can be reduced, and the followed process will become easier.

Description

569396

According to the related technology, the present invention relates to a structure of a flash memory (f 1 ash) and a manufacturing method thereof, and more particularly, to a structure of a flash memory with an embedded floating gate electrode and manufacturing method thereof. method. The flash memory in the previously non-volatile non-volatile memory (n 0 nv 0 1 ati 1 e memory) can perform multiple operations such as storing, reading, and erasing data, and the stored data is stored in The advantage that it will not disappear even after power off, so it has become a kind of memory element widely used in personal computers and electronic devices. A typical flash memory system forms a floating gate and a control gate on a substrate (ie, the substrate surface). The floating gate is located between the control gate and the substrate and is in a floating state 'without any bias. The control gate is connected to the word line Unor. In addition, it also includes a tunneling oxide layer between the substrate and the floating gate, and an inter-poly dielectric layer between the floating gate and the control gate. ) 〇 From the conventional flash memory structure, it can be known that since the components of the gate structure of the conventional flash memory are located on the substrate surface, the thickness of the gate structure is the sum of the thicknesses of the components (ie , The thickness of the tunnel oxide layer, the floating gate, the polycrystalline silicon interlayer dielectric layer, the control gate, etc.). Therefore, in the subsequent processes of forming an interlayer insulating layer, etc., the interlayer insulating layer will have a larger thickness due to the thickness of the conventional flash memory, and thus has a higher aspect ratio, and thus It is not easy to make the contact window etc. contacting the source / drain region in subsequent processes

9871twfl.ptd Page 6 569396, Description of Invention (2) This interlayer insulation layer is formed. Inventing the invention Therefore, the object of the present invention is to provide a flash memory to reduce the height of the protruding substrate of the interrogation structure, so that subsequent processes can be easily performed. Another object of the present invention is to provide a flash memory to reduce the process steps and time.

The invention provides a method for manufacturing a flash memory, which comprises forming an opening on a substrate and forming a first dielectric layer on the substrate. After that, a first conductor layer is formed on the first dielectric layer, and the first conductor layer fills the opening. Next, a source / drain region is formed in the substrate on both sides of the first conductor layer, and the depth of the source / dead region is deeper than the depth of the opening. After that, a second dielectric layer is formed on the substrate, and then a second conductor layer is formed on the second dielectric layer. Next, the second conductor layer is patterned so that the patterned second conductor layer is positioned above the first conductor layer.

In the above process steps, since the floating gate (ie, the first conductor layer) of the present invention is directly formed in the substrate without an additional lithography etching step, the process of the present invention can reduce the number of process steps (at least one Lithography etching step), which further shortens the process time. The invention further provides a flash memory, which is composed of a substrate with an opening, a floating gate located in the opening, a control gate located on the floating gate, and a source / injection located in the substrate on both sides of the floating gate. A polar region, a tunneling oxide layer between the floating gate and the substrate, and a polycrystalline silicon interlayer dielectric layer between the floating gate and the control gate. In addition, in the aforementioned structure

569396 V. Description of the invention (3): The depth of the drain region is higher than that of the present invention. Because the floating electrode is used to restore the woodness, and the gate is buried in the substrate, the gate is built into the opening (ie , The height of the floating substrate is only for control; f: Therefore, the protruding gate structure of the memory can greatly reduce the overall gate = 椹 多: said: the sum of the thickness of the dielectric layer, so the structure of the interlayer insulation layer; 'It can reduce the components that cover the gate in the future. Then, the subsequent process can be easily formed. In order to make the above description of the present invention easier to understand, the features and advantages of the first one compared with #. 二 can be explained in more detail as follows: The best embodiment and the accompanying drawings make detailed implementation. Figures 1A to 1G are drawings according to the present invention. Figures 2A to %% are drawings 1A to 1 1 G, Section I—I. Please refer to Figures 1A and "" at the same time, provide a substrate 100, and form a hafnium oxide layer on the substrate 100 to form a patterned photoresist on the oxide layer 102. Layer 104. The substrate 100 is, for example, made of aluminum. The isolation structure 101 is, for example, a field oxide layer. The method for forming the padding layer 02 is, for example, obtained by oxidizing the substrate 100 by a thermal oxidation method. The method for forming the patterned photoresist layer 104 is, for example, forming a photoresist material before the pad oxide layer 102. Then use photolithography to map this photoresist material. Μ Then 'Please refer to Figure 1B and Figure 2B at the same time, using the photoresist layer 104 as the cover' to remove the uncovered pad oxide layer 102 and part Base 100, with 569396 V. Description of the invention (4)

A plurality of openings σ 1 n R IB BI are formed in the base 1 0 0 to reach the opening 106. The shape of the opening 106 is not rectangular as shown in the figure 丄 β. However, it is pointed out that you are not limited to this, and its opening is not limited. The shape can also be changed to various shapes depending on the needs of the actual manufacturing process. After that, the remaining resist layer 104 and the pad oxide layer 102 are removed. With naked eyes, referring to FIG. K and FIG. 2C, a dielectric layer 108 is formed on the substrate 100, and the dielectric layer 108 does not fill the opening 106. A conductive layer 11G is formed in the dielectric, and the conductive layer 110 fills the opening ⑽. The material of the bulk layer 110 is, for example, doped polycrystalline silicon. The formation method of the conductive layer 11 is, for example, a chemical vapour deposition method (chemical vapQr (^ POSItion)). Specifically, the chemical vapor deposition method is used to deposit polycrystals and dopants are doped into the polycrystalline silicon during the deposition In order to form doped polycrystalline silicon, the dielectric layer 108 is used as a tunneling oxide layer. The method for forming the dielectric layer 108 is, for example, a thermal oxidation method. Next, please refer to FIG. 1D and FIG. 2D at the same time. A conductor layer 1 10 other than the opening 10 is formed as a conductor layer serving as a floating gate. A method of removing the conductor layer 110 outside the opening 106 is, for example, a chemical mechanical polishing method. polishing), etch-back method, etc. Specifically, for example, the conductive layer is removed by chemical mechanical polishing until the dielectric layer 108 or the substrate 100 is blown out, that is, the conductive layer 11A is formed. Please refer to FIG. 1E and FIG. 2E at the same time, implanting dopants into the substrate 100 on both sides of the conductor layer 110A to form a source / drain region 1 12 in the substrate 100. Among them, the source / The depth of the pole area 1 12 is deeper than the depth of the opening 106. Used to shape The source / drain regions 2 Π dopant ions include N-type or p-type dopant ions, an N-type or P-type dopant ions such as phosphorus ions, arsenic ions, stone Peng _ 9871twfl.ptd page 9 569 396

The aforementioned dopant implantation method of ions, etc. 1 uses, for example, a patterned photoresist layer (not shown) as a mask to implant dopants into the substrate 100 on both sides of the conductor layer 110A. -Next, a thermal tempering step is performed to activate the dopant of the source / drain region 2. The thermal tempering method is, for example, a rapid thermal process (Rap d Thermal ProCessing, RTP) method. After that, please refer to FIG. IF and FIG. 2F at the same time to form a dielectric layer 114 on the substrate 100, and this dielectric layer 114 covers at least the conductor layer 110. The dielectric layer 11 4 is used as a polycrystalline silicon interlayer dielectric layer. Specifically, the dielectric layer 1 1 is, for example, an oxide layer, a nitride layer, a nitride-oxide (N0) layer, and an oxide-nitrogen layer. Compound-oxide (0N0) layer and the like. Next, a conductor layer 116 is formed on the dielectric layer 114. The conductor layer U6 ΠL is, for example, doped polycrystalline stone, metal stone compound, or conductive metal. The method for forming the conductive layer 116 is, for example, a chemical vapor deposition method, and it is physical! The polycrystalline silicon layer is deposited by a vapor deposition method to form a polycrystalline silicon layer, and then the polycrystalline silicon layer is doped into a polycrystalline silicon layer to form a doped polycrystalline silicon layer. After that, Yan Qing referred to both the 1G diagram and the% diagram at the same time, and 116A was formed as a control closed pole above the conductor layer U0A. A method of patterning the conductive layer 116 is, for example, patterning a photoresist layer (not shown), and then dividing the conductive layer 116 with the light ^ = to expose the dielectric layer 114. Removal 4 In the flash memory manufacturing method of the present invention described above, the lithography etching step can complete the definition of the floating gate, because the steps required for the flash memory manufacturing method are less than the conventional method. Knowledge ::, VJ /

569396

Therefore, a secondary lithography etching step is required to complete the definition of the floating gate, which can greatly reduce the process time.

Please refer to FIG. 1G and FIG. 2G at the same time. The flash memory system of the present invention is composed of a substrate 100 having an opening 106, a conductor layer located in the opening 106, 10A (and a sub-gate), and a floating gate.丨 丨 0 A conductor layer 丨 丨 6 A (control gate), source / drain region 1 ^ 12 in the substrate on both sides of the conductor layer 11 ο A, located in the conductor layer 11A and the substrate A dielectric layer (tunneled oxide layer) between 100 and a dielectric layer 11 (polycrystalline silicon interlayer dielectric layer) between the conductive layer 11 (the conductive layer 116 and the conductive layer 116).

In addition, in the foregoing structure, the depth of the source / drain region 2 is deeper than the depth of the opening 106. Furthermore, although the dielectric layer 108 is used to cover the substrate 100 as an example in the drawings, it is not limited to this. The dielectric layer 114 may be used to cover the substrate 100 as needed in the process. From the aforementioned layer 110A) system) 'Therefore, the depth of the overall layer 116A) and the insulation structure of the overall gate structure Although the present invention is to limit the scope of the invention, the protection range is considered to be after the field is formed on the base gate The height ratio of polycrystalline silicon has been added to the bottom of the present invention as 'anything can be attached' (also the structure highlights the interlayer dielectric layer, and can be lowered so that you can learn this technology a little better and more patent-pending. The dielectric layer is that the thickness of the south of the floating base is always low and the subsequent overlay is easy to form. The example reveals that the artist has only set the gate limit as defined by the moving and refining fence. Therefore, the gate gate continues the process as above and does not leave. Therefore, it is the quasi-gate (guide buried in the substrate to control the gate), which can greatly reduce the interlayer components of the structure. However, it is not used by the invention.

569396 Brief Description of Drawings Figures 1A to 1G are top views of a flash memory manufacturing process according to a preferred embodiment of the present invention. Figures 2A to 2G are cross-sectional views taken along lines I-Γ in Figures 1 A to 1 G, respectively. Description of drawings: 100: substrate 1 0: isolation structure 102: pad oxide layer 104: patterned photoresist layer 106: opening © 108: dielectric layer 1 10: conductor layer 1 10A: floating gate electrode 1 1 2: source / drain region 1 1 4: dielectric layer 116: conductor layer 116A: control gate

9871twfl.ptd Page 12

Claims (1)

569396 VI. Application Patent Scope 1. A method for manufacturing a flash δ memory device, including providing a substrate; forming an opening in the substrate; a dielectric layer, the first dielectric layer is along the conductor layer, and the A first conductor layer is filled on the substrate to form a first_. The opening is formed on the surface; the open area is formed in the substrate on both sides of the first conductor layer-a source / drain is formed on the substrate A second dielectric layer; forming a patterned second conductor layer on the second dielectric layer, which is located above the first conductor layer. A second conductor layer; and the patterned second conductor layer system 2. The method of manufacturing a flash memory as described in item 1 of the patent scope, wherein the depth of the source / drain region is deeper than the depth of the opening. 3. The method for manufacturing a flash memory as described in item 1 of the scope of patent application, wherein the step of forming the first conductor layer in the opening includes: Forming a conductive material layer on the base; and removing the conductive material layer outside the opening. 4. The method for manufacturing a flash memory according to item 3 of the scope of the patent application, wherein the method for removing the conductive material layer includes a chemical mechanical polishing method. 5. The method for manufacturing a flash memory according to item 3 of the scope of the patent application, wherein the method for removing the conductive material layer includes an etch-back method. 6 · Manufacture of flash memory as described in item 1 of the scope of patent application 569396 -----— French patent application scope — where the material of the first conductor layer includes doped polycrystalline silicon. 7. The flash V production method described in item 1 of the scope of the patent application, I ^ ^ 5 of the memory; Sheng Shi A, ^ the second dielectric layer is selected from the oxide layer, nitride horse ^ Oxide layer, oxide-nitride-oxide layer ㈢, nitride one. ~ It belongs to the group it belongs to. ^ The material of the second conductor layer in the flash memory described in item 1 of the scope of patent application is selected from the group consisting of doped polycrystalline stones, conductive metals, and One of the ethnic groups. 9 · A flash memory, including: A base with an opening in the base; a floating gate located in the opening; a control gate located on the floating gate; a source / drain region located on both sides of the floating gate In the substrate; a through oxide layer is located between the floating gate and the substrate; and a polycrystalline silicon dielectric layer is located between 10 and 10 of the floating gate and the control gate. The flash memory of item 9, wherein the tunneling oxide layer further includes covering the substrate. 11. The flash memory according to item 9 of the patent application scope, wherein the polycrystalline interlayer dielectric layer further includes covering the substrate. • The flash memory as described in item 9 of the scope of patent application, the source / non-polar area, beam sore, and ice are deeper than the ice of the opening. The main flash memory as described in item 9 of the scope of patent application, the material of the sequence gate includes beryllium doped polycrystalline silicon. 569396 6. Application for patent scope 1 4. The flash memory as described in item 9 of the scope of patent application, wherein the polycrystalline silicon interlayer dielectric layer is selected from the group consisting of an oxide layer, a nitride layer, a nitride-oxide layer, and an oxide. One of the groups consisting of an oxide-nitride-oxide layer 5. The flash memory according to item 9 of the scope of the patent application, wherein the material of the control gate is selected from doped polycrystalline silicon and metal silicide One of the groups of conductive metals. 9871twfl.ptd Page 15