JPH10507319A - 3次元不揮発性メモリ - Google Patents
3次元不揮発性メモリInfo
- Publication number
- JPH10507319A JPH10507319A JP9507871A JP50787197A JPH10507319A JP H10507319 A JPH10507319 A JP H10507319A JP 9507871 A JP9507871 A JP 9507871A JP 50787197 A JP50787197 A JP 50787197A JP H10507319 A JPH10507319 A JP H10507319A
- Authority
- JP
- Japan
- Prior art keywords
- strips
- layer
- floating gate
- memory structure
- semiconductor material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims description 47
- 239000000463 material Substances 0.000 claims abstract description 37
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 238000010849 ion bombardment Methods 0.000 claims abstract description 6
- 238000001020 plasma etching Methods 0.000 claims abstract description 4
- 150000004767 nitrides Chemical class 0.000 claims description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 20
- 239000012212 insulator Substances 0.000 claims description 15
- 125000006850 spacer group Chemical group 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 241001279686 Allium moly Species 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 abstract description 17
- 239000010703 silicon Substances 0.000 abstract description 17
- 230000003647 oxidation Effects 0.000 abstract description 10
- 238000007254 oxidation reaction Methods 0.000 abstract description 10
- 238000001459 lithography Methods 0.000 abstract description 3
- 239000007943 implant Substances 0.000 description 19
- 238000005530 etching Methods 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 238000002513 implantation Methods 0.000 description 10
- 229910052785 arsenic Inorganic materials 0.000 description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 8
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000002784 hot electron Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- LZIAMMQBHJIZAG-UHFFFAOYSA-N 2-[di(propan-2-yl)amino]ethyl carbamimidothioate Chemical compound CC(C)N(C(C)C)CCSC(N)=N LZIAMMQBHJIZAG-UHFFFAOYSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000001802 infusion Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.上表面を有する半導体材料を備え、前記上表面は第1の実質的に横方向であ りかつ平坦な表面と、側壁表面と、第2の実質的に横方向でありかつ平坦な表面 とを含み、前記第1の表面は前記第2の表面に関して横方向および縦方向に変位 されており、前記側壁表面における半導体材料はイオン衝撃による損傷から実質 的に免れており、さらに 前記第1の表面から前記半導体材料の中へ延びるソース領域と、 前記第2の表面から前記半導体材料内に延びるドレイン領域と、 前記側壁表面上に配設される絶縁体材料の第1の層と、 絶縁体材料の前記第1の層上に配設されるフローティングゲートと、 前記フローティングゲート上に配設される絶縁体材料の第2の層と、 絶縁体材料の前記第2の層上に配設される導電層とを備え、絶縁体材料の前記 第2の層は前記フローティングゲートと前記導電層とを分離する、メモリ構造。 2.前記導電層は第1の次元において前記側壁表面に沿って延びるワード線であ り、前記メモリ構造はさらに 前記第1の次元に実質的に垂直である第2の次元において延びるビット線を備 え、前記ビット線は前記ドレイン領域に結合される、請求項1に記載のメモリ構 造。 3.前記フローティングゲートは多結晶シリコンの層である、請求項2に記載の メモリ構造。 4.前記ワード線は、多結晶シリコンを含む、請求項3に記載のメモリ構造。 5.絶縁体材料の前記第2の層は、酸化物の第1の層と、窒化物の層と、酸化物 の第2の層とを含む、請求項3に記載のメモリ構造。 6.上表面を有する第1導電型の半導体材料を備え、前記上表面は第1の次元に おいて延びる第1および第2の長手の窪みを有し、前記長手の窪みの各々は対向 する急勾配の側壁および底部表面を有し、前記急勾配の側壁における半導体材料 は、イオン衝撃による損傷を実質的に免れており、さらに 前記第1および第2の窪みの前記側壁上に配設される第1の絶縁体層と、 導電層の第1の複数のストリップとを備え、前記第1の複数のストリップの 各々は、前記側壁のそれぞれの上で前記第1の次元において延び、かつ前記側壁 から絶縁されており、さらに 導電層の第2の複数のストリップを備え、前記第2の複数のストリップの各々 は前記第2の複数のストリップの他のものに対して実質的に平行に延びかつ前記 第1の次元に実質的に垂直な第2の次元において延び、前記第2の複数のストリ ップの各々は前記第1の複数のストリップの上を交差し、かつ前記第1および第 2の窪みの上を交差し、さらに 複数個のフローティングゲートを備え、前記フローティングゲートのそれぞれ は前記第2の複数のストリップの1つが前記第1の複数のストリップの1つと交 差するそれぞれの位置の付近に配設され、各フローティングゲートは前記第1の 複数のストリップの1つと前記ストリップがその上に配設される側壁との間に配 設され、さらに 第2の絶縁体層を備え、各フローティングゲートは前記各フローティングゲー ト上を交差する前記第2の複数のストリップの1つから絶縁され、さらに 前記第1導電型と反対の第2導電型である第1および第2の長手の導電領域を 備え、前記第1の長手の導電領域は前記第1の窪みの前記底部表面内に延び、前 記第2の導電領域は前記第2の窪みの前記底部表面内に延び、さらに 前記第1および第2の窪みの間の前記半導体材料内に延びる前記第2導電型の 複数個の第3の導電領域を備え、前記第3の導電領域のそれぞれ1つは前記第2 の複数のストリップのそれぞれ1つの下に配設され、かつそれに結合される、メ モリ構造。 7.前記複数のフローティングゲートは多結晶シリコンゲートであり、前記第1 の複数のストリップは多結晶シリコンを含み、前記第2の複数のストリップは金 属ストリップである、請求項6に記載のメモリ構造。 8.前記第1の複数のストリップはワード線であり、前記第2の複数のストリッ プはビット線である、請求項7に記載のメモリ構造。 9.前記長手の窪みは、前記急勾配の側壁に加えて、対向する徐々に傾斜した側 壁を有する、請求項6に記載のメモリ構造。 10.複数個の酸化物スペーサをさらに備え、前記酸化物スペーサは部分的に前 記フローティングゲートの側部端縁上、および前記第1の複数のストリップの側 部端縁上に配設される、請求項6に記載のメモリ構造。 11.前記第1および第2の長手の導電領域の各々は、 窪みの側壁上に配設された前記第1の複数のストリップの1つの下に配設され る、第1の比較的浅い領域と、 前記窪みの対向する側壁上に配設された前記第1の複数のストリップの別のも のの下に配設される、第2の比較的浅い領域と、 前記第1および第2の比較的浅い領域の間に配設され、前記第1および第2の 比較的浅い領域に接触する、比較的深い領域とを備える、請求項6に記載のメモ リ構造。 12.フローティングゲートを有する不揮発性メモリ構造を形成する方法であっ て、 半導体材料の表面における選択された部分を酸化させることにより半導体材料 の中に窪みを形成し、次に前記窪みから酸化物を除去するステップを備え、前記 窪みは側壁を有し、さらに 前記側壁上に前記不揮発性メモリ構造の前記フローティングゲートを形成する ステップを備え、前記フローティングゲートは前記側壁から絶縁されている、フ ローティングゲートを有する不揮発性メモリ構造を形成する方法。 13.前記窪みを形成する前記ステップは、前記側壁が露出されるように前記窪 みから実質的にすべての酸化物を除去するステップに関わる、請求項12に記載 の方法。 14.窪みを形成する前記ステップの後、前記フローティングゲートを形成する 前記ステップの前に、前記側壁を酸化させて、前記側壁上に直接的に薄い酸化層 を形成するステップをさらに備える、請求項12に記載の方法。 15.前記窪みから除去された前記酸化物は、1500から6000Åの範囲の 厚みを有する、請求項12に記載の方法。 16.前記側壁は実質的にイオン衝撃による損傷は免れている、請求項12に記 載の方法。 17.前記窪みは半導体材料の反応性イオンエッチングなしで形成される、請求 項12に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/510,118 US5945705A (en) | 1995-08-01 | 1995-08-01 | Three-dimensional non-volatile memory |
US08/510,118 | 1995-08-01 | ||
PCT/US1996/012527 WO1997005655A1 (en) | 1995-08-01 | 1996-07-31 | Three-dimensional non-volatile memory |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005273676A Division JP3968107B2 (ja) | 1995-08-01 | 2005-09-21 | フローティングゲートを有する不揮発性メモリ構造を形成する方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH10507319A true JPH10507319A (ja) | 1998-07-14 |
JP3821848B2 JP3821848B2 (ja) | 2006-09-13 |
Family
ID=24029441
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50787197A Expired - Fee Related JP3821848B2 (ja) | 1995-08-01 | 1996-07-31 | 3次元不揮発性メモリ |
JP2005273676A Expired - Fee Related JP3968107B2 (ja) | 1995-08-01 | 2005-09-21 | フローティングゲートを有する不揮発性メモリ構造を形成する方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005273676A Expired - Fee Related JP3968107B2 (ja) | 1995-08-01 | 2005-09-21 | フローティングゲートを有する不揮発性メモリ構造を形成する方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US5945705A (ja) |
EP (1) | EP0784867B1 (ja) |
JP (2) | JP3821848B2 (ja) |
KR (1) | KR970706609A (ja) |
DE (1) | DE69637352T2 (ja) |
WO (1) | WO1997005655A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023144656A1 (ja) * | 2022-01-31 | 2023-08-03 | 株式会社半導体エネルギー研究所 | 表示装置 |
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US6765257B1 (en) * | 1997-07-23 | 2004-07-20 | Texas Instruments Incorporated | Implanted vertical source-line under straight stack for flash eprom |
US6093606A (en) * | 1998-03-05 | 2000-07-25 | Taiwan Semiconductor Manufacturing Company | Method of manufacture of vertical stacked gate flash memory device |
US6333228B1 (en) * | 2000-03-24 | 2001-12-25 | Taiwan Semiconductor Manufacturing Company | Method to improve the control of bird's beak profile of poly in split gate flash |
US6300199B1 (en) * | 2000-05-24 | 2001-10-09 | Micron Technology, Inc. | Method of defining at least two different field effect transistor channel lengths using differently angled sidewall segments of a channel defining layer |
DE10158564C1 (de) * | 2001-11-29 | 2003-07-17 | Infineon Technologies Ag | Leiterbahnstruktur für eine integrierte Schaltung und entsprechendes Herstellungsverfahren |
DE10220922B4 (de) * | 2002-05-10 | 2006-09-28 | Infineon Technologies Ag | Flash-Speicherzelle, Anordnung von Flash-Speicherzellen und Verfahren zur Herstellung von Flash-Speicherzellen |
TW536797B (en) * | 2002-06-24 | 2003-06-11 | Macronix Int Co Ltd | Multi-bit memory cell and its manufacturing method |
DE10231202A1 (de) * | 2002-07-10 | 2004-02-05 | Infineon Technologies Ag | Vertikaltransistor-Speicherzelle, Speicherzellen-Anordnung, Verfahren zum Herstellen einer Vertikaltransistor-Speicherzelle und Verfahren zum Betreiben einer Vertikaltransistor-Speicherzelle |
US6790752B1 (en) * | 2003-02-05 | 2004-09-14 | Advanced Micro Devices, Inc. | Methods of controlling VSS implants on memory devices, and system for performing same |
US6853031B2 (en) * | 2003-04-17 | 2005-02-08 | United Microelectronics Corp. | Structure of a trapezoid-triple-gate FET |
KR100755058B1 (ko) * | 2005-04-04 | 2007-09-06 | 주식회사 하이닉스반도체 | 스텝게이트를 갖는 반도체소자 및 그 제조방법 |
US20060255412A1 (en) * | 2005-05-13 | 2006-11-16 | Nirmal Ramaswamy | Enhanced access devices using selective epitaxial silicon over the channel region during the formation of a semiconductor device and systems including same |
KR100855992B1 (ko) | 2007-04-02 | 2008-09-02 | 삼성전자주식회사 | 경사진 측벽을 갖는 활성 필라를 구비하는 비휘발성 메모리트랜지스터, 이를 구비하는 비휘발성 메모리 어레이 및상기 비휘발성 메모리 트랜지스터의 제조방법 |
US7933136B2 (en) * | 2008-11-07 | 2011-04-26 | Seagate Technology Llc | Non-volatile memory cell with multiple resistive sense elements sharing a common switching device |
CN102456745B (zh) * | 2010-10-22 | 2013-09-04 | 北京大学 | 一种快闪存储器及其制备方法和操作方法 |
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1995
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- 1996-07-31 DE DE69637352T patent/DE69637352T2/de not_active Expired - Lifetime
- 1996-07-31 KR KR1019970702104A patent/KR970706609A/ko not_active Application Discontinuation
- 1996-07-31 WO PCT/US1996/012527 patent/WO1997005655A1/en active IP Right Grant
- 1996-07-31 JP JP50787197A patent/JP3821848B2/ja not_active Expired - Fee Related
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2023144656A1 (ja) * | 2022-01-31 | 2023-08-03 | 株式会社半導体エネルギー研究所 | 表示装置 |
Also Published As
Publication number | Publication date |
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JP3821848B2 (ja) | 2006-09-13 |
US6043122A (en) | 2000-03-28 |
WO1997005655A1 (en) | 1997-02-13 |
KR970706609A (ko) | 1997-11-03 |
EP0784867A1 (en) | 1997-07-23 |
US5945705A (en) | 1999-08-31 |
JP3968107B2 (ja) | 2007-08-29 |
DE69637352T2 (de) | 2008-11-13 |
DE69637352D1 (de) | 2008-01-17 |
EP0784867B1 (en) | 2007-12-05 |
JP2006049926A (ja) | 2006-02-16 |
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