JP3968107B2 - フローティングゲートを有する不揮発性メモリ構造を形成する方法 - Google Patents
フローティングゲートを有する不揮発性メモリ構造を形成する方法 Download PDFInfo
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- JP3968107B2 JP3968107B2 JP2005273676A JP2005273676A JP3968107B2 JP 3968107 B2 JP3968107 B2 JP 3968107B2 JP 2005273676 A JP2005273676 A JP 2005273676A JP 2005273676 A JP2005273676 A JP 2005273676A JP 3968107 B2 JP3968107 B2 JP 3968107B2
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- 230000015654 memory Effects 0.000 title claims description 73
- 238000000034 method Methods 0.000 title claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 23
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 238000001020 plasma etching Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 description 40
- 238000004519 manufacturing process Methods 0.000 description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 28
- 238000002513 implantation Methods 0.000 description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 238000005530 etching Methods 0.000 description 11
- 239000012212 insulator Substances 0.000 description 9
- 229910052785 arsenic Inorganic materials 0.000 description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 8
- 239000007943 implant Substances 0.000 description 8
- 125000006850 spacer group Chemical group 0.000 description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000002784 hot electron Substances 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- LZIAMMQBHJIZAG-UHFFFAOYSA-N 2-[di(propan-2-yl)amino]ethyl carbamimidothioate Chemical compound CC(C)N(C(C)C)CCSC(N)=N LZIAMMQBHJIZAG-UHFFFAOYSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 238000010849 ion bombardment Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Description
83年)、S.Kobayashiらによる「3Vのみのセクタ消去可能DINORフラッシュメモリのためのメモリアレイアーキテクチャおよびデコード方式(Memory Array Architecture and Decoding Scheme for 3V Only Sector Erasable DINOR Flash Memory)」IEEE Journal of Solid-State Circuits第29巻第4号454〜460頁(1994年)、およびS.Aritomeらによる「フラッシュメモリセルにおける信頼性の問題(Reliability Issues
of Flash Memory Cells)」Proceedings of the IEEE第81巻5号776〜788頁(1993年)。これらの文献の主題はここに引用により援用される。
る大きな損傷はない。その結果、側壁表面上に高品質の薄いトンネル酸化物を成長させることができるので、フローティングゲートは下にある側壁表面から良好に絶縁される。
が用いられる。典型的な、3:1の酸化物対窒化物選択比が用いられる。これは酸化物が窒化物よりも3倍速くエッチングされることを意味している。厚い酸化物108のおよそ1000Åが除去され、エッチングの窪みの底部で半導体材料101を覆っている厚い酸化物のうち約300Åが残される。
3−x3′、y2−y2′およびy1−y1′に沿ってとられた断面図である。領域113からのP型ドーパントは、拡散によって膨張していることに注目されたい。
ッチングしてスペーサにすることによって形成することができる。
116および117の底部におけるN+型領域143および144は、金属(図示せず)および関連のコンタクト(図示せず)によってともに結合される。
フラッシュメモリにおけるすべてのフローティングゲートは、ファウラ−ノルドハイム・トンネルによって同時に放電される。たとえばフローティングゲート127、128、130および131が放電されるべきである場合、次の表1における電圧条件がメモリ構造に与えられるだろう。
フラッシュメモリをプログラミングするには、選択されたワードの選択されたビットトランジスタにおけるフローティングゲートが熱い電子注入により充電される(すなわち「プログラミング」される)。たとえば、ビットトランジスタ157のフローティングゲート127が充電されるべきであるが、他のビットトランジスタ158、130および131はすべて放電されたままであるべき場合、次の表2における電圧条件がメモリ構造に与えられるだろう。
図39は、本発明の別の実施例に従う代替的構造の単純化された断面図である。P−ウェル200が深いN−ウェル206の内部に配設されて、N+埋込層201を基板207から分離する。ファウラ−ノルドハイム・トンネルが、フローティングゲートの充電およびフローティングゲートの放電の双方に用いられる。
代替的構造におけるビットトランジスタはすべて、同時に充電される(すなわち「消去」される)。図39におけるビットトランジスタのフローティングゲート202を充電するには、次の表3の電圧条件が与えられる。
図39のビットトランジスタを放電するには、次の表4における電圧条件が与えられる。
ンとしてソース/ドレイン注入ステップ(図16参照)を行なうことにより、上述の製造方法に従って製造される。N+埋込層201が、砒素またはリンを約400〜800KeVの範囲の注入エネルギ、そして好ましくは約600KeVの注入エネルギで注入することによって形成される。二重にイオン化されたドーパントでは、約300KeVが用いられる。N+埋込層注入の注入エネルギは約60KeVまで低減される。
第3のソース/ドレインマスク、108 酸化物、109 領域、110 ビーム。
Claims (6)
- フローティングゲートを有する不揮発性メモリ構造を形成する方法であって、
半導体材料の表面における選択された部分を酸化させることにより半導体材料の中に窪みを形成し、次に前記窪みから酸化物を除去するステップを備え、前記窪みは2つの対向する第1側壁表面および2つの対向する第2側壁表面を有し、前記第1側壁表面は前記第2側壁表面より急勾配であり、さらに
前記第1側壁表面上に前記不揮発性メモリ構造の前記フローティングゲートを形成するステップを備え、前記フローティングゲートは前記第1側壁表面から絶縁されている、フローティングゲートを有する不揮発性メモリ構造を形成する方法。 - 前記窪みを形成する前記ステップは、前記第1と第2側壁表面が露出されるように前記窪みから実質的にすべての酸化物を除去するステップに関わる、請求項1に記載の方法。
- 窪みを形成する前記ステップの後、前記フローティングゲートを形成する前記ステップの前に、前記第1と第2側壁表面を酸化させて、前記第1と第2側壁表面上に直接的に酸化層を形成するステップをさらに備える、請求項1に記載の方法。
- 前記窪みから除去された前記酸化物は、1500から6000Åの範囲の厚みを有する、請求項1に記載の方法。
- 前記第1と第2側壁表面はイオン衝撃による損傷を免れている、請求項1に記載の方法。
- 前記窪みは半導体材料の反応性イオンエッチングなしで形成される、請求項1に記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/510,118 US5945705A (en) | 1995-08-01 | 1995-08-01 | Three-dimensional non-volatile memory |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50787197A Division JP3821848B2 (ja) | 1995-08-01 | 1996-07-31 | 3次元不揮発性メモリ |
Publications (2)
Publication Number | Publication Date |
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JP2006049926A JP2006049926A (ja) | 2006-02-16 |
JP3968107B2 true JP3968107B2 (ja) | 2007-08-29 |
Family
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Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50787197A Expired - Fee Related JP3821848B2 (ja) | 1995-08-01 | 1996-07-31 | 3次元不揮発性メモリ |
JP2005273676A Expired - Fee Related JP3968107B2 (ja) | 1995-08-01 | 2005-09-21 | フローティングゲートを有する不揮発性メモリ構造を形成する方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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JP50787197A Expired - Fee Related JP3821848B2 (ja) | 1995-08-01 | 1996-07-31 | 3次元不揮発性メモリ |
Country Status (6)
Country | Link |
---|---|
US (2) | US5945705A (ja) |
EP (1) | EP0784867B1 (ja) |
JP (2) | JP3821848B2 (ja) |
KR (1) | KR970706609A (ja) |
DE (1) | DE69637352T2 (ja) |
WO (1) | WO1997005655A1 (ja) |
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-
1995
- 1995-08-01 US US08/510,118 patent/US5945705A/en not_active Expired - Lifetime
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1996
- 1996-07-31 DE DE69637352T patent/DE69637352T2/de not_active Expired - Lifetime
- 1996-07-31 KR KR1019970702104A patent/KR970706609A/ko not_active Application Discontinuation
- 1996-07-31 EP EP96926200A patent/EP0784867B1/en not_active Expired - Lifetime
- 1996-07-31 JP JP50787197A patent/JP3821848B2/ja not_active Expired - Fee Related
- 1996-07-31 WO PCT/US1996/012527 patent/WO1997005655A1/en active IP Right Grant
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1999
- 1999-06-16 US US09/334,393 patent/US6043122A/en not_active Expired - Lifetime
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Also Published As
Publication number | Publication date |
---|---|
US5945705A (en) | 1999-08-31 |
JP3821848B2 (ja) | 2006-09-13 |
EP0784867B1 (en) | 2007-12-05 |
DE69637352T2 (de) | 2008-11-13 |
DE69637352D1 (de) | 2008-01-17 |
JP2006049926A (ja) | 2006-02-16 |
EP0784867A1 (en) | 1997-07-23 |
KR970706609A (ko) | 1997-11-03 |
JPH10507319A (ja) | 1998-07-14 |
US6043122A (en) | 2000-03-28 |
WO1997005655A1 (en) | 1997-02-13 |
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