JP2005303044A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP2005303044A JP2005303044A JP2004117798A JP2004117798A JP2005303044A JP 2005303044 A JP2005303044 A JP 2005303044A JP 2004117798 A JP2004117798 A JP 2004117798A JP 2004117798 A JP2004117798 A JP 2004117798A JP 2005303044 A JP2005303044 A JP 2005303044A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- semiconductor device
- shoulder
- manufacturing
- annealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28238—Making the insulator with sacrificial oxide
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Abstract
【解決手段】 STIの肩部における角張った箇所を丸める熱処理を、1000℃以上の高温で長時間、希ガス雰囲気中で行う。肩部を丸くし、希ガスの採用により窒素によるシリコン界面への影響をなくすことでゲート酸化膜の局所的な膜厚のバラツキをなくし、ゲート酸化膜の信頼性を向上させることができる半導体装置の製造方法が得られる。
【選択図】 図1
Description
2 パッド酸化膜
3 窒化膜
4 トレンチ
5 内壁酸化膜
6 埋設酸化膜
7 犠牲酸化膜
8 ゲート酸化膜
9 ディポッド
Claims (8)
- トレンチにより分離された半導体装置の製造方法において、埋設酸化膜成長後からゲートポリシリ成長前までのいずれかの工程において希ガスを含む雰囲気中でアニール処理することを特徴とする半導体装置の製造方法。
- 前記希ガスは、アルゴン、ネオン、ヘリウムであることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記アニール処理は、温度は1000℃以上、1200℃以下であり、時間は10分以上、5時間以下であることを特徴とする請求項1または2記載の半導体装置の製造方法。
- 前記アニール処理は、シリコン基板を露出させないで、絶縁膜で覆った状態で行うことを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置の製造方法。
- 前記アニール処理は、チャンネル注入直前に行うことを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置の製造方法。
- 前記アニール処理は、ゲートポリシリ成長直前に行うことを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置の製造方法。
- 前記アニール処理は、CMP直前に行うことを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置の製造方法。
- 前記アニール処理は、パッド酸化膜除去直前に行うことを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004117798A JP4577680B2 (ja) | 2004-04-13 | 2004-04-13 | 半導体装置の製造方法 |
US11/103,613 US20050227452A1 (en) | 2004-04-13 | 2005-04-12 | Method for producing semiconductor device |
CN200510064979.XA CN1684242A (zh) | 2004-04-13 | 2005-04-13 | 半导体器件的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004117798A JP4577680B2 (ja) | 2004-04-13 | 2004-04-13 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005303044A true JP2005303044A (ja) | 2005-10-27 |
JP4577680B2 JP4577680B2 (ja) | 2010-11-10 |
Family
ID=35061100
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004117798A Expired - Fee Related JP4577680B2 (ja) | 2004-04-13 | 2004-04-13 | 半導体装置の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20050227452A1 (ja) |
JP (1) | JP4577680B2 (ja) |
CN (1) | CN1684242A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102332400A (zh) * | 2011-07-28 | 2012-01-25 | 上海宏力半导体制造有限公司 | 半导体器件的形成方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7432148B2 (en) * | 2005-08-31 | 2008-10-07 | Micron Technology, Inc. | Shallow trench isolation by atomic-level silicon reconstruction |
US7838353B2 (en) * | 2008-08-12 | 2010-11-23 | International Business Machines Corporation | Field effect transistor with suppressed corner leakage through channel material band-edge modulation, design structure and method |
US8125037B2 (en) | 2008-08-12 | 2012-02-28 | International Business Machines Corporation | Field effect transistor with channel region edge and center portions having different band structures for suppressed corner leakage |
CN102446762B (zh) * | 2010-10-13 | 2014-02-05 | 中芯国际集成电路制造(上海)有限公司 | Mos晶体管及其制作方法 |
US9945048B2 (en) * | 2012-06-15 | 2018-04-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and method |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09205140A (ja) * | 1995-11-21 | 1997-08-05 | Toshiba Corp | 素子分離半導体基板およびその製造方法 |
JPH1079421A (ja) * | 1996-09-05 | 1998-03-24 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JPH1197523A (ja) * | 1997-07-31 | 1999-04-09 | Lucent Technol Inc | デバイス作製プロセス |
JP2000012674A (ja) * | 1998-06-19 | 2000-01-14 | Toshiba Corp | 半導体装置の製造方法および素子分離方法 |
JP2001144170A (ja) * | 1999-11-11 | 2001-05-25 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2002057211A (ja) * | 2000-08-15 | 2002-02-22 | Seiko Epson Corp | トレンチ素子分離領域を有する半導体装置の製造方法 |
JP2004006660A (ja) * | 2002-03-26 | 2004-01-08 | Fuji Electric Holdings Co Ltd | 半導体装置の製造方法 |
JP2004273971A (ja) * | 2003-03-12 | 2004-09-30 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69211329T2 (de) * | 1992-03-27 | 1996-11-28 | Ibm | Verfahren zum Herstellen von pseudo-planaren Dünnschicht PFET-Anordnungen und hierdurch erzeugte Struktur |
US5834358A (en) * | 1996-11-12 | 1998-11-10 | Micron Technology, Inc. | Isolation regions and methods of forming isolation regions |
US6322634B1 (en) * | 1997-01-27 | 2001-11-27 | Micron Technology, Inc. | Shallow trench isolation structure without corner exposure |
US6097076A (en) * | 1997-03-25 | 2000-08-01 | Micron Technology, Inc. | Self-aligned isolation trench |
US5849643A (en) * | 1997-05-23 | 1998-12-15 | Advanced Micro Devices, Inc. | Gate oxidation technique for deep sub quarter micron transistors |
KR100261018B1 (ko) * | 1997-09-25 | 2000-08-01 | 윤종용 | 반도체장치의트렌치격리형성방법 |
US6087243A (en) * | 1997-10-21 | 2000-07-11 | Advanced Micro Devices, Inc. | Method of forming trench isolation with high integrity, ultra thin gate oxide |
TW389982B (en) * | 1998-01-26 | 2000-05-11 | United Microelectronics Corp | Method of manufacturing shallow trench isolation |
KR100275908B1 (ko) * | 1998-03-02 | 2000-12-15 | 윤종용 | 집적 회로에 트렌치 아이솔레이션을 형성하는방법 |
US5989978A (en) * | 1998-07-16 | 1999-11-23 | Chartered Semiconductor Manufacturing, Ltd. | Shallow trench isolation of MOSFETS with reduced corner parasitic currents |
KR100292616B1 (ko) * | 1998-10-09 | 2001-07-12 | 윤종용 | 트렌치격리의제조방법 |
KR100338767B1 (ko) * | 1999-10-12 | 2002-05-30 | 윤종용 | 트렌치 소자분리 구조와 이를 갖는 반도체 소자 및 트렌치 소자분리 방법 |
US6277697B1 (en) * | 1999-11-12 | 2001-08-21 | United Microelectronics Corp. | Method to reduce inverse-narrow-width effect |
US6413828B1 (en) * | 2000-03-08 | 2002-07-02 | International Business Machines Corporation | Process using poly-buffered STI |
US6455382B1 (en) * | 2001-05-03 | 2002-09-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-step method for forming sacrificial silicon oxide layer |
JP3597495B2 (ja) * | 2001-08-31 | 2004-12-08 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
US6713335B2 (en) * | 2002-08-22 | 2004-03-30 | Chartered Semiconductor Manufacturing Ltd. | Method of self-aligning a damascene gate structure to isolation regions |
US7091105B2 (en) * | 2002-10-28 | 2006-08-15 | Hynix Semiconductor Inc. | Method of forming isolation films in semiconductor devices |
KR100728173B1 (ko) * | 2003-03-07 | 2007-06-13 | 앰버웨이브 시스템즈 코포레이션 | 쉘로우 트렌치 분리법 |
KR100505068B1 (ko) * | 2003-07-05 | 2005-07-29 | 삼성전자주식회사 | 반도체 소자의 다중 게이트 산화막 및 이를 포함하는게이트 전극 형성방법 |
US7018873B2 (en) * | 2003-08-13 | 2006-03-28 | International Business Machines Corporation | Method of making a device threshold control of front-gate silicon-on-insulator MOSFET using a self-aligned back-gate |
JP4550453B2 (ja) * | 2004-03-23 | 2010-09-22 | 株式会社東芝 | 工程管理システム、及び工程管理方法 |
-
2004
- 2004-04-13 JP JP2004117798A patent/JP4577680B2/ja not_active Expired - Fee Related
-
2005
- 2005-04-12 US US11/103,613 patent/US20050227452A1/en not_active Abandoned
- 2005-04-13 CN CN200510064979.XA patent/CN1684242A/zh active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09205140A (ja) * | 1995-11-21 | 1997-08-05 | Toshiba Corp | 素子分離半導体基板およびその製造方法 |
JPH1079421A (ja) * | 1996-09-05 | 1998-03-24 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JPH1197523A (ja) * | 1997-07-31 | 1999-04-09 | Lucent Technol Inc | デバイス作製プロセス |
JP2000012674A (ja) * | 1998-06-19 | 2000-01-14 | Toshiba Corp | 半導体装置の製造方法および素子分離方法 |
JP2001144170A (ja) * | 1999-11-11 | 2001-05-25 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2002057211A (ja) * | 2000-08-15 | 2002-02-22 | Seiko Epson Corp | トレンチ素子分離領域を有する半導体装置の製造方法 |
JP2004006660A (ja) * | 2002-03-26 | 2004-01-08 | Fuji Electric Holdings Co Ltd | 半導体装置の製造方法 |
JP2004273971A (ja) * | 2003-03-12 | 2004-09-30 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102332400A (zh) * | 2011-07-28 | 2012-01-25 | 上海宏力半导体制造有限公司 | 半导体器件的形成方法 |
CN102332400B (zh) * | 2011-07-28 | 2016-06-01 | 上海华虹宏力半导体制造有限公司 | 半导体器件的形成方法 |
Also Published As
Publication number | Publication date |
---|---|
JP4577680B2 (ja) | 2010-11-10 |
US20050227452A1 (en) | 2005-10-13 |
CN1684242A (zh) | 2005-10-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3974547B2 (ja) | 半導体装置および半導体装置の製造方法 | |
US6953727B2 (en) | Manufacture method of semiconductor device with gate insulating films of different thickness | |
USRE41696E1 (en) | Semiconductor device and manufacturing method thereof | |
JP4825402B2 (ja) | 半導体装置の製造方法 | |
JP2006253717A (ja) | 高選択性cmpを用いた集積回路装置のトレンチ素子分離方法 | |
JP2001332614A (ja) | トレンチ型素子分離構造の製造方法 | |
JP2005197475A (ja) | 半導体装置のドライエッチング方法 | |
JP5121102B2 (ja) | 半導体装置の製造方法 | |
US20050227452A1 (en) | Method for producing semiconductor device | |
JP2001044273A (ja) | 半導体装置の製造方法 | |
US6825128B2 (en) | Method for manufacturing semiconductor device | |
JPWO2007086111A1 (ja) | 半導体装置の製造方法 | |
JP4843205B2 (ja) | 半導体素子の製造方法 | |
JP2003517729A (ja) | ホットキャリア性能を向上させるための窒化再酸化ポリシリコンゲート | |
JP2006210463A (ja) | 半導体装置及びその製造方法 | |
JP3644682B2 (ja) | 半導体装置の製造方法 | |
JP2005142319A (ja) | 半導体装置の製造方法 | |
JPWO2012120857A1 (ja) | 半導体装置の製造方法 | |
JP2005072358A (ja) | 半導体装置の製造方法 | |
CN101314852B (zh) | 蚀刻溶液、基板的表面处理方法及形成浅沟槽隔离的方法 | |
JP2003204060A (ja) | 半導体装置の製造方法 | |
KR20010014793A (ko) | 반도체 장치의 제조 방법 | |
JP2001007217A (ja) | 半導体装置の製造方法 | |
JP2004064037A (ja) | 半導体装置の製造方法 | |
TWI304630B (ja) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20070731 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090520 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090721 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100428 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100621 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100728 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100817 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130903 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |