JP4550453B2 - 工程管理システム、及び工程管理方法 - Google Patents
工程管理システム、及び工程管理方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 194
- 230000008569 process Effects 0.000 title claims description 190
- 238000007726 management method Methods 0.000 title claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 123
- 238000004519 manufacturing process Methods 0.000 claims description 70
- 238000004458 analytical method Methods 0.000 claims description 67
- 238000007689 inspection Methods 0.000 claims description 56
- 239000000758 substrate Substances 0.000 claims description 52
- 230000007547 defect Effects 0.000 claims description 18
- 238000013461 design Methods 0.000 description 21
- 238000004088 simulation Methods 0.000 description 18
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- 238000007254 oxidation reaction Methods 0.000 description 12
- 238000005229 chemical vapour deposition Methods 0.000 description 8
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- 238000012360 testing method Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000011960 computer-aided design Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000011156 evaluation Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005401 electroluminescence Methods 0.000 description 2
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- 238000000206 photolithography Methods 0.000 description 2
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- 230000003449 preventive effect Effects 0.000 description 2
- 238000004886 process control Methods 0.000 description 2
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- 238000012916 structural analysis Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
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- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
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- 231100001261 hazardous Toxicity 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
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- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
ケイ・ダブリュ・シュワルツ(K. W. Schwarz)、ジャーナル・オブ・アプライド・フィジックス(J. Appl. Phys.)、1999年1月、第85巻、第1号、pp.108−119
f = σ・b×t (1)
ここで、fは素片に働く力のベクトル、σは応力テンソル、bは滑り面に存在するバーガーズベクトル、tは転位線の素片の方向ベクトルである。式(1)は、バーガーズベクトルb及び転位線の素片の方向ベクトルtの外積であるから、転位に働く力の向きは必ず転位線に垂直である。
上記のように、本発明の実施の形態を記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものであると理解すべきではない。この開示から当業者にはさまざまな代替実施の形態、実施例及び運用技術が明らかとなろう。
4 工程条件取得部
8 構造取得部
10 応力解析部
12 起点設定部
14 転位動力学解析部
16 転位形態比較部
18 構造パラメータ設定部
20 工程条件判定部
32 製造情報データベース
34 検査情報データベース
Claims (5)
- 半導体基板に製造された半導体装置中の検査転位像を取得する検査情報取得部と、
前記半導体装置を製造した複数の工程のそれぞれの工程条件を取得する工程条件取得部と、
取得した前記工程条件に基づいて前記複数の工程の中から転位発生原因となる危険工程の候補を対象工程として設定する工程設定部と、
前記複数の工程の中から設定された前記対象工程で処理される前記半導体基板の構造を取得する構造取得部と、
前記工程条件及び前記構造に基づいて、前記構造の内部に設定された複数の節点で応力を計算する応力解析部と、
基準値以上の前記応力の集中が予測される位置に複数の起点を設定する起点設定部と、
前記複数の起点の位置のそれぞれに対して、前記応力による応力場で転位の成長過程を計算し解析転位線の形態を予測する転位動力学解析部と、
前記解析転位線の形態を前記検査転位像と比較して、前記対象工程が転位発生原因の危険工程であるか判定する転位形態比較部
とを備えることを特徴とする工程管理システム。 - 前記危険工程で処理される前記構造を規定する複数の構造パラメータの中から対象構造パラメータを設定する構造パラメータ設定部と、
前記対象構造パラメータの値を変化させて得られた新たな解析転位線の形態に基づいて、不良原因構造パラメータを予測し、前記不良原因構造パラメータに対応する前記工程条件を修正する工程条件判定部
とを更に備えることを特徴とする請求項1に記載の工程管理システム。 - 前記検査転位像を含む検査情報を保管する検査情報データベースと、
前記工程条件、及び前記構造パラメータを含む製造情報を保管する製造情報データベース
とを更に備えることを特徴とする請求項2に記載の工程管理システム。 - 半導体基板に製造された半導体装置中の検査転位像を検査情報取得部で取得し、
前記半導体装置を製造した複数の工程のそれぞれの工程条件を工程条件取得部で取得し、
取得した前記工程条件に基づいて前記複数の工程の中から転位発生原因となる危険工程の候補を対象工程として工程設定部で設定し、
前記複数の工程の中から設定された前記対象工程で処理される前記半導体基板の構造を構造取得部で取得し、
前記工程条件及び前記構造に基づいて、前記構造の内部に設定された複数の節点で応力を応力解析部で計算し、
基準値以上の前記応力の集中が予測される位置に複数の起点を起点設定部で設定し、
前記複数の起点の位置のそれぞれに対して、前記応力による応力場で転位の成長過程を計算し解析転位線の形態を転位動力学解析部で予測し、
前記解析転位線の形態を前記検査転位像と比較して、前記対象工程が転位発生原因の危険工程であるか転位形態比較部で判定する
ことを含むことを特徴とする工程管理方法。 - 前記危険工程で処理される前記構造を規定する複数の構造パラメータの中から対象構造パラメータを構造パラメータ設定部で指定し、
前記対象構造パラメータの値を変化させて得られた新たな解析転位線の形態に基づいて、不良原因構造パラメータを予測し、前記不良原因構造パラメータに対応する工程条件を工程条件判定部で修正する
ことを更に含むことを特徴とする請求項4に記載の工程管理方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2004084682A JP4550453B2 (ja) | 2004-03-23 | 2004-03-23 | 工程管理システム、及び工程管理方法 |
TW094108491A TWI249803B (en) | 2004-03-23 | 2005-03-18 | System for controlling manufacturing process, method for controlling manufacturing process and method for manufacturing a semiconductor device |
US11/086,220 US7188049B2 (en) | 2004-03-23 | 2005-03-23 | System and method for controlling manufacturing processes, and method for manufacturing a semiconductor device |
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JP2004084682A JP4550453B2 (ja) | 2004-03-23 | 2004-03-23 | 工程管理システム、及び工程管理方法 |
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JP2005276915A JP2005276915A (ja) | 2005-10-06 |
JP4550453B2 true JP4550453B2 (ja) | 2010-09-22 |
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US (1) | US7188049B2 (ja) |
JP (1) | JP4550453B2 (ja) |
TW (1) | TWI249803B (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4056412B2 (ja) * | 2003-03-10 | 2008-03-05 | 株式会社東京精密 | パターン検査方法及び装置 |
JP4577680B2 (ja) * | 2004-04-13 | 2010-11-10 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
US7713889B2 (en) * | 2005-11-16 | 2010-05-11 | Nikon Corporation | Substrate processing method, photomask manufacturing method, photomask, and device manufacturing method |
US8515724B2 (en) * | 2010-06-22 | 2013-08-20 | International Business Machines Corporation | Technology computer-aided design (TCAD)-based virtual fabrication |
KR101866448B1 (ko) * | 2011-02-10 | 2018-06-11 | 삼성전자주식회사 | 포토마스크 형성 방법, 이를 수행하는 프로그래밍된 명령을 저장하는 컴퓨터에서 판독 가능한 저장 매체 및 마스크 이미징 시스템 |
JP6124287B2 (ja) * | 2013-03-04 | 2017-05-10 | 一般財団法人電力中央研究所 | 炭化珪素基板又は炭化珪素半導体素子の検査方法及び炭化珪素基板又は炭化珪素半導体素子の製造方法 |
US20190155971A1 (en) * | 2017-11-20 | 2019-05-23 | Samsung Electronics Co., Ltd. | Device dislocation stress simulation |
CN111625918B (zh) * | 2019-02-27 | 2023-05-09 | 阿里巴巴集团控股有限公司 | 一种工艺参数推荐方法、装置及电子设备 |
KR20230048952A (ko) * | 2021-10-05 | 2023-04-12 | 삼성전자주식회사 | 풀-칩 레이아웃을 이용한 레이아웃 검증 시스템 및 이를 이용한 레이아웃 검증 방법 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0774164A (ja) * | 1993-07-02 | 1995-03-17 | Hitachi Ltd | 半導体メモリ装置及びその製造方法 |
JPH1145922A (ja) * | 1997-07-25 | 1999-02-16 | Toshiba Corp | 材料強度シミュレーション方法 |
JP2003092237A (ja) * | 2001-07-12 | 2003-03-28 | Toshiba Corp | 危険プロセス/パターン検出システム、危険プロセス/パターン検出方法、危険検出プログラム、及び半導体装置の製造方法 |
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JP4274649B2 (ja) * | 1999-10-07 | 2009-06-10 | 株式会社日立製作所 | 微細パターン検査方法及び装置 |
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2004
- 2004-03-23 JP JP2004084682A patent/JP4550453B2/ja not_active Expired - Fee Related
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2005
- 2005-03-18 TW TW094108491A patent/TWI249803B/zh not_active IP Right Cessation
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0774164A (ja) * | 1993-07-02 | 1995-03-17 | Hitachi Ltd | 半導体メモリ装置及びその製造方法 |
JPH1145922A (ja) * | 1997-07-25 | 1999-02-16 | Toshiba Corp | 材料強度シミュレーション方法 |
JP2003092237A (ja) * | 2001-07-12 | 2003-03-28 | Toshiba Corp | 危険プロセス/パターン検出システム、危険プロセス/パターン検出方法、危険検出プログラム、及び半導体装置の製造方法 |
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Publication number | Publication date |
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US20050233601A1 (en) | 2005-10-20 |
TWI249803B (en) | 2006-02-21 |
TW200536036A (en) | 2005-11-01 |
US7188049B2 (en) | 2007-03-06 |
JP2005276915A (ja) | 2005-10-06 |
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