JP2005197632A - 半導体素子の製造方法 - Google Patents
半導体素子の製造方法 Download PDFInfo
- Publication number
- JP2005197632A JP2005197632A JP2004182198A JP2004182198A JP2005197632A JP 2005197632 A JP2005197632 A JP 2005197632A JP 2004182198 A JP2004182198 A JP 2004182198A JP 2004182198 A JP2004182198 A JP 2004182198A JP 2005197632 A JP2005197632 A JP 2005197632A
- Authority
- JP
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- Prior art keywords
- insulating film
- manufacturing
- semiconductor device
- film spacer
- forming
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 125000006850 spacer group Chemical group 0.000 claims abstract description 47
- 238000005530 etching Methods 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000011229 interlayer Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims 2
- 230000001747 exhibiting effect Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 7
- 238000009413 insulation Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000007865 diluting Methods 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
【解決手段】ゲートライン102とゲートライン102の周辺に接合領域が形成された半導体基板101を提供する段階と、ゲートラインの側壁に目標の厚さより厚く絶縁膜スペーサ104を形成する段階と、絶縁膜スペーサをエッチングして接合領域の露出幅を増加させる段階と、ゲートラインを含んだ全体構造上に層間絶縁膜106を形成する段階とを含む。
【選択図】図2
Description
102 ゲートライン
102a ゲート酸化膜
102b ポリシリコン層
102c シリサイド層
102d ハードマスク
103 接合領域
104 絶縁膜スペーサ
105 窒化膜
106 層間絶縁膜
106a ボイド
Claims (11)
- ゲートラインと前記ゲートラインの周辺に接合領域が形成された半導体基板を提供する段階と、
前記ゲートラインの側壁に目標の厚さより厚く絶縁膜スペーサを形成する段階と、
前記絶縁膜スペーサをエッチングして前記接合領域の露出幅を増加させる段階と、
前記ゲートラインを含んだ全体構造上に層間絶縁膜を形成する段階とを含む半導体素子の製造方法。 - 前記絶縁膜スペーサがシリコン酸化膜で形成される請求項1記載の半導体素子の製造方法。
- 前記エッチング工程がウェットエッチング工程で行われる請求項1記載の半導体素子の製造方法。
- 前記ウェットエッチング工程の際に、希釈されたフッ酸溶液又はBOEが使用される請求項3記載の半導体素子の製造方法。
- 前記エッチング工程の進行時間は、前記絶縁膜スペーサのエッチング率を考慮して前記絶縁膜スペーサの厚さが目標の厚さとなるように調節する請求項1記載の半導体素子の製造方法。
- 前記エッチング工程は、前記絶縁膜スペーサとしての機能を発揮しながら前記接合領域の露出幅が最大となれるように、前記絶縁膜スペーサをエッチングする請求項1記載の半導体素子の製造方法。
- 前記エッチング工程は、前記接合領域の露出幅が10nm〜1000nm程度増加するように、前記絶縁膜スペーサをエッチングする請求項1記載の半導体素子の製造方法。
- 前記層間絶縁膜を形成する前に、
前記ゲートラインを含んだ全体構造上にボーダレスコンタクトを形成するための窒化膜を形成する段階をさらに含む請求項1記載の半導体素子の製造方法。 - 前記層間絶縁膜がBPSGで形成される請求項1記載の半導体素子の製造方法。
- 前記BPSGに含まれたボロンとリンの割合が4.5wt%と4.0wt%以下である請求項9記載の半導体素子の製造方法。
- 前記層間絶縁膜を形成した後に、
前記層間絶縁膜の流動性を増加させるために急速熱処理を行う段階をさらに含む請求項1記載の半導体素子の製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030100171A KR100567529B1 (ko) | 2003-12-30 | 2003-12-30 | 반도체 소자의 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005197632A true JP2005197632A (ja) | 2005-07-21 |
JP4642388B2 JP4642388B2 (ja) | 2011-03-02 |
Family
ID=34698744
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004182198A Expired - Fee Related JP4642388B2 (ja) | 2003-12-30 | 2004-06-21 | 半導体素子の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US6967151B2 (ja) |
JP (1) | JP4642388B2 (ja) |
KR (1) | KR100567529B1 (ja) |
TW (1) | TWI257143B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012174910A (ja) * | 2011-02-22 | 2012-09-10 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100500448B1 (ko) * | 2003-02-06 | 2005-07-14 | 삼성전자주식회사 | 선택적 디스포저블 스페이서 기술을 사용하는 반도체집적회로의 제조방법 및 그에 의해 제조된 반도체 집적회로 |
KR100695487B1 (ko) * | 2006-03-20 | 2007-03-16 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
FI126449B (fi) | 2014-06-11 | 2016-12-15 | Janesko Oy | Menetelmä ja sovitelma prosessinesteestä otetun erillisnäytteen mittauksen yhteydessä |
CN108091562B (zh) * | 2017-12-21 | 2020-06-16 | 上海华力微电子有限公司 | Sonos存储器的ono刻蚀方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08236473A (ja) * | 1995-02-28 | 1996-09-13 | Nec Corp | 半導体装置の製造方法 |
JPH09232427A (ja) * | 1996-02-23 | 1997-09-05 | Nec Corp | 半導体装置の製造方法 |
JPH10214795A (ja) * | 1997-01-28 | 1998-08-11 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2000188378A (ja) * | 1998-12-21 | 2000-07-04 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2002217128A (ja) * | 2000-12-07 | 2002-08-02 | Samsung Electronics Co Ltd | 半導体素子の製造方法 |
JP2003282706A (ja) * | 2002-03-27 | 2003-10-03 | Semiconductor Leading Edge Technologies Inc | 半導体装置の製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0456318B1 (en) * | 1990-05-11 | 2001-08-22 | Koninklijke Philips Electronics N.V. | CMOS process utilizing disposable silicon nitride spacers for making lightly doped drain transistors |
US5238872A (en) * | 1990-12-11 | 1993-08-24 | Samsung Semiconductor, Inc. | Barrier metal contact architecture |
TW227628B (ja) * | 1992-12-10 | 1994-08-01 | Samsung Electronics Co Ltd | |
US6350665B1 (en) * | 2000-04-28 | 2002-02-26 | Cypress Semiconductor Corporation | Semiconductor structure and method of making contacts and source and/or drain junctions in a semiconductor device |
-
2003
- 2003-12-30 KR KR1020030100171A patent/KR100567529B1/ko active IP Right Grant
-
2004
- 2004-06-21 JP JP2004182198A patent/JP4642388B2/ja not_active Expired - Fee Related
- 2004-06-21 US US10/872,883 patent/US6967151B2/en active Active
- 2004-06-30 TW TW093119309A patent/TWI257143B/zh not_active IP Right Cessation
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08236473A (ja) * | 1995-02-28 | 1996-09-13 | Nec Corp | 半導体装置の製造方法 |
JPH09232427A (ja) * | 1996-02-23 | 1997-09-05 | Nec Corp | 半導体装置の製造方法 |
JPH10214795A (ja) * | 1997-01-28 | 1998-08-11 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2000188378A (ja) * | 1998-12-21 | 2000-07-04 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2002217128A (ja) * | 2000-12-07 | 2002-08-02 | Samsung Electronics Co Ltd | 半導体素子の製造方法 |
JP2003282706A (ja) * | 2002-03-27 | 2003-10-03 | Semiconductor Leading Edge Technologies Inc | 半導体装置の製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012174910A (ja) * | 2011-02-22 | 2012-09-10 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20050068583A (ko) | 2005-07-05 |
KR100567529B1 (ko) | 2006-04-03 |
TW200522254A (en) | 2005-07-01 |
JP4642388B2 (ja) | 2011-03-02 |
US20050142711A1 (en) | 2005-06-30 |
TWI257143B (en) | 2006-06-21 |
US6967151B2 (en) | 2005-11-22 |
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