TWI257143B - Method of manufacturing a semiconductor device - Google Patents

Method of manufacturing a semiconductor device

Info

Publication number
TWI257143B
TWI257143B TW093119309A TW93119309A TWI257143B TW I257143 B TWI257143 B TW I257143B TW 093119309 A TW093119309 A TW 093119309A TW 93119309 A TW93119309 A TW 93119309A TW I257143 B TWI257143 B TW I257143B
Authority
TW
Taiwan
Prior art keywords
manufacturing
semiconductor device
gate lines
opening widths
junction areas
Prior art date
Application number
TW093119309A
Other languages
English (en)
Other versions
TW200522254A (en
Inventor
Pil-Geun Song
Sang-Wook Park
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200522254A publication Critical patent/TW200522254A/zh
Application granted granted Critical
Publication of TWI257143B publication Critical patent/TWI257143B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
TW093119309A 2003-12-30 2004-06-30 Method of manufacturing a semiconductor device TWI257143B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020030100171A KR100567529B1 (ko) 2003-12-30 2003-12-30 반도체 소자의 제조 방법

Publications (2)

Publication Number Publication Date
TW200522254A TW200522254A (en) 2005-07-01
TWI257143B true TWI257143B (en) 2006-06-21

Family

ID=34698744

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093119309A TWI257143B (en) 2003-12-30 2004-06-30 Method of manufacturing a semiconductor device

Country Status (4)

Country Link
US (1) US6967151B2 (zh)
JP (1) JP4642388B2 (zh)
KR (1) KR100567529B1 (zh)
TW (1) TWI257143B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100500448B1 (ko) * 2003-02-06 2005-07-14 삼성전자주식회사 선택적 디스포저블 스페이서 기술을 사용하는 반도체집적회로의 제조방법 및 그에 의해 제조된 반도체 집적회로
KR100695487B1 (ko) * 2006-03-20 2007-03-16 주식회사 하이닉스반도체 반도체 소자 및 그 제조 방법
JP5746881B2 (ja) * 2011-02-22 2015-07-08 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
FI126449B (fi) 2014-06-11 2016-12-15 Janesko Oy Menetelmä ja sovitelma prosessinesteestä otetun erillisnäytteen mittauksen yhteydessä
CN108091562B (zh) * 2017-12-21 2020-06-16 上海华力微电子有限公司 Sonos存储器的ono刻蚀方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0456318B1 (en) * 1990-05-11 2001-08-22 Koninklijke Philips Electronics N.V. CMOS process utilizing disposable silicon nitride spacers for making lightly doped drain transistors
US5238872A (en) * 1990-12-11 1993-08-24 Samsung Semiconductor, Inc. Barrier metal contact architecture
TW227628B (zh) * 1992-12-10 1994-08-01 Samsung Electronics Co Ltd
JP2663900B2 (ja) * 1995-02-28 1997-10-15 日本電気株式会社 半導体装置の製造方法
JP2850833B2 (ja) * 1996-02-23 1999-01-27 日本電気株式会社 半導体装置の製造方法
JPH10214795A (ja) * 1997-01-28 1998-08-11 Fujitsu Ltd 半導体装置及びその製造方法
JP2000188378A (ja) * 1998-12-21 2000-07-04 Toshiba Corp 半導体装置及びその製造方法
US6350665B1 (en) * 2000-04-28 2002-02-26 Cypress Semiconductor Corporation Semiconductor structure and method of making contacts and source and/or drain junctions in a semiconductor device
KR100382727B1 (ko) * 2000-12-07 2003-05-09 삼성전자주식회사 셀프 얼라인 콘택 식각 공정을 채용할 경우 보이드 없이패드를 형성할 수 있는 반도체 소자의 제조방법
JP3722772B2 (ja) * 2002-03-27 2005-11-30 三星電子株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
KR20050068583A (ko) 2005-07-05
KR100567529B1 (ko) 2006-04-03
TW200522254A (en) 2005-07-01
JP4642388B2 (ja) 2011-03-02
US20050142711A1 (en) 2005-06-30
JP2005197632A (ja) 2005-07-21
US6967151B2 (en) 2005-11-22

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees