JP2004253816A - 集積回路を非導電的に相互接続する方法及び装置 - Google Patents
集積回路を非導電的に相互接続する方法及び装置 Download PDFInfo
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Abstract
【解決手段】 モジュラー電子システムを構成し、修理しそして動作する方法及び装置は、当接するモジュール間を非導電的に連通するために、周囲の半キャパシタ(14、15)(即ち、モジュールの外側の導電性プレート)を使用する。このようなシステムは、プリント回路板(10)及びマルチチップモジュールのような従来のモジュラーパッケージング技術よりも低コストの改良されたテスト/修理性能、及び大きな密度を与える。本発明の非導電性相互接続技術は、裸の半導体ダイから完成した機能的サブユニットに至るまでのパッケージハイアラーキの全てのレベルに適用できる。多数の例示的なシステム及び用途について説明する。
【選択図】 図1
Description
本出願は 1993年6月24日付本願発明者らによる米国特許出願 S/N 08/082,328 号“集積回路を非導電的に相互接続する方法及び装置”の部分継続である。上記'328 号出願は本明細書に参照されている。
エレクトロニックシステムは通常、成分の階層的なパッケージとして実現されている。抵抗器及びトランジスタのような受動的な、もしくは能動的な電子素子及びそれらの配線は、典型的にはメモリもしくは論理ユニットに組合わされ、それらが回路及びデバイスに組合わされ、それらがより大きい機能ユニットに組合わされる等々によってシステムにレベルまで組合わされて行く。
MCMは、裸であろうとカプセル封じされていようと、それに取付けられ導電的に結合されている2もしくはそれ以上のダイを含む。MCMは電力及びダイ間信号配線を提供する。若干のMCM技術では、ダイはサブストレートに物理的に結合され、周辺に位置決めされている接点(例えばピン)にワイヤボンドされたリードがダイとマルチチップサブストレートとの間の導電性接続を供給する。他の技術は、ダイのリードが周辺に、またはダイ領域の殆どにわたっての何れかに位置決めされ(ピン格子アレイ(PGA)または半田の盛り上がりのように)、マルチチップサブストレート上のそれぞれの接点に半田付けその他によって結合されている“フリップチップ”構成を使用している。
現在の技術では、オンダイ(on-die)に留まるよりは、オフダイ(off-die)を信号することの方が(電力、待ち時間、性能、及び回路リアルエステートに関して)遥かに費用がかさむ。オフダイを信号することは、同一のダイもしくは異なるダイ上の2点間でオフダイ配線を使用して通信することを意味している。従って、現在の技術における主たる設計の目的は、各ダイ上の回路の数を増加させて高価なオフダイ相互接続に対する比を増加させることである。しかしながら、ダイのサイズがある経済的に、そして技術的に実行可能な限界に接近すると、ランダムに発生する製造欠陥が受容できないダイを発生する確率がポアソン分布で指数的に上昇するようになる。ダイが僅かに大きくなると歩留りはかなり低い率になるから、このいわゆる“表面対体積”(通信対計算)比が製造歩留りを、従って正常ダイ当たりの費用を大幅に制約する。
過去数年にわたる種々の研究努力にも拘わらず、今日のMCM技術は未だに費用、性能、設計、製造可能性、信頼性及び修復性、並びに上述した要望に対する欠点に関する重大な問題を抱えている。
本発明の目的は、上述した従来技術の欠点の1もしくはそれ以上を軽減する、モジュールを相互接続する方法及び装置に関する。
本発明の別の目的は、相互接続配線を破壊することなくサブモジュールを修復し、交換する方法に関する。
本発明の別の目的は、モジュラーエレクトロニックシステム内の望ましくないモジュールを識別し、交換する方法及び装置に関する。
この波形は、特定のクロック周期29の間の波形のレベルによって定義される一連の状態からなる。例えば、周期21の間の波形は、デジタル「1」をあらわす。周期22では、波形はデジタル「0」をあらわす。3−状態システムの場合、周期23の間の波形は、「−1」で示される状態をあらわす。波形は、ダイ11上の素子12からつくられるデジタル回路によって生成される。
第8図において、ダイ11は、基板10に容量性結合されている。チップ11を(誘電体17xおよび17yの中にモノリシックにつくられたものとして例示してある導体14yを介して)基板10に結合する容量性信号通路の複数階構造は、「実質的に重ねられて」いない板である半コンデンサー14xおよび15xの間に「効果的な重なり」を生成するものである。94aおよび15のような実質的に重ねられた半コンデンサーは、事実上、効果的に重ね合わされている。
あるいは、401bのような電力供給手段は、チップ400b、基板404、またはシステムの他の場所に配設されたバッテリーに接続できるようにして、外部電力接続部の必要性をなくすこともできる。電子装置に電力を供給するための手段は、多くのものが当業者には知られており、本発明のねらい添って好適に使用することができる。
この特許は、参考のため本出願文書に添付してある。
・有効回路が各5mm2の200個のダイから構成されたシステム内では、各ダイは1対の電源・アース(0.5mm2)および7.1mm2(=0.5×2001/2)の通信回路を必要とし、従って実際は12.6mm2のダイになる。12.6mm2のダイの歩留まりは95パーセントであり、従って、全システムの「コスト」は約(200×12.6/0.95)=26.5cm2のウェーハ、つまり、上記の10.2cm2のシステムの2.6倍になる。非常に小さなダイはその電源パッドの「表面積対体積」サイズおよびダイ間通信用回路によって支配され、従って、たとえ歩留まりが高くても不十分である。
・有効回路が各20mm2の50個のダイから構成されたシステム内では、各ダイはやはり1対の電源・アースおよび3.6mm2(=0.5×501/2)の通信回路を必要とし、従って実際は24.1mm2のダイになる。24.1mm2のダイの歩留まりは82パーセントであり、従って、全システムの「コスト」は約14.7cm2のウェーハ、つまり、上記の10.2cm2システムの1.4倍になる。電源パッド、信号回路および有効回路のシミュレーション用に選択した特定のモデルの場合は、約20mm2のダイが最もコスト有効性の高いビルディングブロックを提供する。
・有効回路が各1.0mm2の10個のダイから構成されたシステム内では、各ダイは4対の電源・アース(2.0mm2)および1.6mm2(=0.5×101/2)の通信回路を必要とし、従って実際は103.6mm2のダイになる。103.6mm2のダイの歩留まりは37パーセントであり、従って、全システムの「コスト」は約28.0cm2のウェーハ、つまり、上記の10.2cm2のシステムの約11/4倍になる。大きなダイの場合は、設計効率の点での利益よりも製造歩留まりの点での損失の方が大きく、非常に大きなダイの場合は、有効回路とオーバーヘッド回路の割合の点で魅力が大きいとはいえ、歩留まりはゼロに近い。
10 基板
11 ダイ
Claims (35)
- 基板上に設置されるチップにおいて、
複数のデジタルゲートが具現化された半導体ダイと、
上記チップに信号を容量性結合するために上記ダイに具現化された複数の半キャパシタとを備えたことを特徴とするチップ。 - 上記チップ上に電力を導電性結合するために上記ダイ上に具現化された端子を更に備えた請求項1に記載のチップ。
- 複数のチップを収容し、電力を供給しそしてそれらの間を信号結合する基板において、
上記基板への及び基板からの信号を容量性結合するために上記基板上に具現化された複数の半キャパシタと、
上記基板から上記チップへ電力を導電性結合するために上記基板上に具現化された複数の端子とを備えたことを特徴とする基板。 - 上記基板及び上記複数のチップはモジュールを備え、上記基板は、上記モジュールと上記モジュールの外部の複数の端子との間で信号を導電性結合するために上記基板に具現化された複数の端子を更に備えた請求項3に記載の基板。
- 容量性結合されたデジタル信号を受け取るためのチップにおいて、
ダイと、
上記第1及び第2の半キャパシタを経て差動信号を受け取ると共に、この差動信号から、上記チップにより受け取られたデジタル情報を表す出力信号を発生するために上記ダイ上に具現化された手段とを備えたことを特徴とするチップ。 - モジュラーデジタルシステムにおいて第1集積回路チップから第2集積回路チップへデータを送信する方法であって、
データを表す信号を上記第1集積回路チップに関連した第1の半キャパシタへ付与し、
上記第1の半キャパシタから上記第2集積回路チップに関連した第2の半キャパシタへ上記信号を容量性結合し、そして、
上記第2集積回路チップにおいて上記第2の半キャパシタを経て、上記第1の半キャパシタに付与された信号に関連した信号を受信する、
という段階を備えたことを特徴とする方法。 - モジュラー電子システムにおいて電子デバイス間に信号を結合する方法において、
上記電子デバイスの第1サブセットを第1チップ上に配置し、
上記電子デバイスの第2サブセットを第2チップ上に配置し、そして
上記第1及び第2のチップを整列及び固定して、上記第1と第2のチップ間で少なくとも1つの信号を容量性結合する、
という段階を備えたことを特徴とする方法。 - 上記第1及び第2チップは、上記基板を経てこれら第1及び第2チップを容量性結合するようにベース基板に固定される請求項7に記載のモジュラー電子システムにおいて電子デバイス間に信号を結合する方法。
- マルチチップモジュールを組み立てる方法において、
既知のチップを識別し、そして
上記既知のチップを上記マルチチップモジュールに設置して、上記モジュールが電力を与え、上記チップに少なくとも1つの信号を容量性結合することを特徴とする方法。 - 上記設置されたチップの選択されたチップを置き換えて全システム性能を改善するという段階を更に備えた請求項9に記載の方法。
- マルチチップ又はウェハスケールモジュールの組み立て方法において、
(a)複数のチップを第1基板上に形成し、
(b)複数のチップを検査し、
(c)上記段階(b)に応答して、第2基板上の選択された電力接続を選択的にイネーブル又は非ディスエイブルし、上記選択された接続は、上記段階(b)の検査に合格したチップに関連したものであり、そして
(d)上記第1基板を上記第2基板に嵌合して、上記段階(b)の検査に合格したチップを給電する、
という段階を備えたことを特徴とする方法。 - 上記段階(d)は、上記第2基板を上記第1基板に固定して、上記第2基板の上記イネーブルされた又は非ディスエイブルされた電力接続部が上記チップ上の各パッドに導電的に接触するようにすることを含む請求項11に記載の方法。
- 上記チップの各々は、半キャパシタを更に備え、そして上記段階(d)は、上記半キャパシタを上記第2基板上の半キャパシタに容量性結合することを含む請求項12に記載の方法。
- 第1及び第2チップ間で信号を容量性結合する方法において、各々の上記チップは複数の半キャパシタを有し、上記方法は、
上記第1チップを基板に固定し、そして
上記第2チップを上記第1チップに整列し、そして
上記第2チップを上記基板に固定し、これにより、上記第1及び第2チップの対応する半キャパシタ間にキャパシタを形成し、そして上記第1及び第2チップ間に直接容量性結合信号を与える、
という段階を備えたことを特徴とする方法。 - 第1の複数のモノリシック集積回路と半キャパシタのアレイを含む第1モジュールと、
第2の複数のモノリシック集積回路と半キャパシタのアレイを含む第2モジュールとを備え、
各モノリシック集積回路は、給電手段とデジタル電子デバイスが埋め込まれた能動表面を含み、
上記第1及び第2のモジュールは、上記第1モジュール上のアレイと上記第2モジュール上のアレイとが容量性結合して両モジュールの間に信号路のアレイを形成するように、配置されることを特徴とするモジュラー電子システム。 - 上記システムは、上記第1モジュールに給電する手段を含む請求項15に記載のモジュラー電子システム。
- 上記第2モジュールに挿入面を備え、この挿入面は特性形状を有していて上記第2端子及び上記第2の半キャパシタを露出し、そして
上記第1モジュールにリセプタクル面を備え、このリセプタクル面は、上記第1端子及び上記第1の半キャパシタを露出し、上記リセプタクル面は、上記挿入面及びリセプタクル面が当接して整列されたときに、上記第1及び第2の半キャパシタが容量性結合しそして上記第1及び第2の端子が導電性結合するように構成される請求項15に記載のモジュラー電子システム。 - 上記リセプタクル面のガイド部分は、上記挿入面の対応するガイド部分に一致する形状とされ、これらガイド部分は上記挿入面及びリセプタクル面を整列する手段を形成する請求項17に記載のモジュラー電子システム。
- 上記第1モジュールは、上記容量性信号路を上記第1及び第2のモジュール間で横方向に移動させることにより上記第2モジュールに対して配置される請求項18に記載のモジュラー電子システム。
- 上記第2のモジュールは、バックプレーンを含む請求項15に記載のモジュラー電子システム。
- 上記第1のモジュールは、更に、上記バックプレーンから電力を受け取る手段を備えている請求項20に記載のモジュラー電子システム。
- 上記第1のモジュールは、更に、
複数のモジュールと、
上記サブモジュールへ電力を配電する手段とを備えた請求項16に記載のモジュラー電子システム。 - 上記半キャパシタの一方の形状は、上記半キャパシタの他方の形状と異なる請求項15に記載のモジュラー電子システム。
- 上記第1モジュールは、更に、上記第1の半キャパシタに接続されたデジタル送信器を備え、そして上記第2モジュールは、更に、上記第2の半キャパシタに接続されたデジタル受信器を備え、これにより、上記第1モジュールから第2モジュールへのデジタル信号路が形成される請求項15に記載のモジュラー電子システム。
- 上記デジタル送信器は、更に、上記第1半キャパシタの電圧を少なくとも2つの個別の電圧レベル間で迅速に切り換える手段を備えた請求項24に記載のモジュラー電子システム。
- 第1及び第2のモジュールを安価に接続する方法であって、各モジュールは多数の信号端子を有しており、上記方法は、
相互接続基板を次のように整列し、即ち
(i)上記相互接続基板の第1の複数の半キャパシタが信号を上記第1モジュール上の複数の信号端子に容量性結合し、そして
(ii)上記相互接続基板の第2の複数の半キャパシタが信号を上記第2モジュール上の複数の信号端子に容量性結合するようにし、そして
上記相互接続基板を上記第1及び第2のモジュールに固定する、
という段階を備えたことを特徴とする方法。 - 上記整列段階は、容量性整列プロセスを使用する請求項26に記載の接続方法。
- 上記整列段階は、光学整列プロセスを使用する請求項26に記載の接続方法。
- 上記固定段階は接合を含む請求項26に記載の接続方法。
- 上記固定段階は機械的な取付を含む請求項26に記載の接続方法。
- 第1アレイを含む第1モジュールと、
第2アレイを含む第2モジュールと、
第3アレイ及び第4アレイを含む第3モジュールとを備え、
上記第3アレイは上記第1アレイと容量性結合し、上記第4アレイは上記第2アレイと容量性結合し、
各アレイは複数の半キャパシタから成ることを特徴とするモジュラー電子システム。 - 更に、第5アレイを含む第4モジュールを備え、
上記第2モジュールは更に第6アレイを含み、
上記第5アレイは上記第6アレイと容量性結合している請求項31に記載のモジュラー電子システム。 - 上記モジュールは、規則的な幾何学パターンで傾斜している請求項31に記載のモジュラー電子システム。
- 上記モジュールは、モノリシック集積回路を含む請求項31に記載のモジュラー電子システム。
- 更に、機械的なアライメントを促進する構造を含む請求項31に記載のモジュラー電子システム。
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Also Published As
Publication number | Publication date |
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US7869221B2 (en) | 2011-01-11 |
US20050002448A1 (en) | 2005-01-06 |
JP4083704B2 (ja) | 2008-04-30 |
JP4017186B2 (ja) | 2007-12-05 |
JPH09504908A (ja) | 1997-05-13 |
US6916719B1 (en) | 2005-07-12 |
US20080315978A1 (en) | 2008-12-25 |
EP0705529A4 (en) | 1998-06-24 |
EP0705529A1 (en) | 1996-04-10 |
WO1995001087A1 (en) | 1995-01-05 |
US5629838A (en) | 1997-05-13 |
US6728113B1 (en) | 2004-04-27 |
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