TW547773U - Contactless interconnection apparatus - Google Patents

Contactless interconnection apparatus

Info

Publication number
TW547773U
TW547773U TW090205708U TW90205708U TW547773U TW 547773 U TW547773 U TW 547773U TW 090205708 U TW090205708 U TW 090205708U TW 90205708 U TW90205708 U TW 90205708U TW 547773 U TW547773 U TW 547773U
Authority
TW
Taiwan
Prior art keywords
terminal lands
discrete
chip package
aligned
pattern
Prior art date
Application number
TW090205708U
Other languages
Chinese (zh)
Inventor
Augusto P Panella
Original Assignee
Molex Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/548,940 external-priority patent/US6612852B1/en
Priority claimed from US09/548,636 external-priority patent/US6362972B1/en
Application filed by Molex Inc filed Critical Molex Inc
Publication of TW547773U publication Critical patent/TW547773U/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)
  • Connecting Device With Holders (AREA)

Abstract

A contactless interconnecting system is provided between a computer chip package and a circuit board. The chip package has a substantially planar lower surface with a pattern of discrete terminal lands. The circuit board has a substantially planar upper surface spaced from and generally parallel to the lower surface of the chip package. A pattern of discrete circuit pads on the upper surface are aligned with the terminal lands. A plurality of discrete interposer members are disposed between the terminal lands and the circuit pads and are in a pattern corresponding to and aligned with the aligned patterns of the terminal lands and circuit pads. The interposer members are preferably of a material having a higher dielectric constant that of the material filling the gaps between interposer members.
TW090205708U 2000-04-13 2001-04-12 Contactless interconnection apparatus TW547773U (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/548,940 US6612852B1 (en) 2000-04-13 2000-04-13 Contactless interconnection system
US09/548,636 US6362972B1 (en) 2000-04-13 2000-04-13 Contactless interconnection system

Publications (1)

Publication Number Publication Date
TW547773U true TW547773U (en) 2003-08-11

Family

ID=27068917

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090205708U TW547773U (en) 2000-04-13 2001-04-12 Contactless interconnection apparatus

Country Status (7)

Country Link
EP (1) EP1273040A2 (en)
JP (1) JP3701242B2 (en)
KR (1) KR20020090233A (en)
CN (1) CN1237612C (en)
AU (1) AU2001251588A1 (en)
TW (1) TW547773U (en)
WO (1) WO2001080316A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100336218C (en) * 2003-08-25 2007-09-05 威盛电子股份有限公司 High-frequency IC multi-bus knot tying structure and method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2902002A1 (en) * 1979-01-19 1980-07-31 Gerhard Krause Three=dimensional integrated circuits - mfd. by joining wafer stack with contacts through conductive adhesive
JPH0583011A (en) * 1991-09-25 1993-04-02 Sumitomo Electric Ind Ltd Input/output coupling device for package for semiconductor device
US6728113B1 (en) * 1993-06-24 2004-04-27 Polychip, Inc. Method and apparatus for non-conductively interconnecting integrated circuits
JPH0998005A (en) * 1995-09-29 1997-04-08 Nec Corp Printed circuit board
US6396712B1 (en) * 1998-02-12 2002-05-28 Rose Research, L.L.C. Method and apparatus for coupling circuit components

Also Published As

Publication number Publication date
KR20020090233A (en) 2002-11-30
JP2003531496A (en) 2003-10-21
WO2001080316A3 (en) 2002-03-21
AU2001251588A1 (en) 2001-10-30
EP1273040A2 (en) 2003-01-08
CN1237612C (en) 2006-01-18
CN1422440A (en) 2003-06-04
JP3701242B2 (en) 2005-09-28
WO2001080316A2 (en) 2001-10-25

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Legal Events

Date Code Title Description
GD4K Issue of patent certificate for granted utility model filed before june 30, 2004
MK4K Expiration of patent term of a granted utility model