NO20022792D0 - Integrated circuit package formed at a silicon wafer level - Google Patents
Integrated circuit package formed at a silicon wafer levelInfo
- Publication number
- NO20022792D0 NO20022792D0 NO20022792A NO20022792A NO20022792D0 NO 20022792 D0 NO20022792 D0 NO 20022792D0 NO 20022792 A NO20022792 A NO 20022792A NO 20022792 A NO20022792 A NO 20022792A NO 20022792 D0 NO20022792 D0 NO 20022792D0
- Authority
- NO
- Norway
- Prior art keywords
- wafer
- integrated circuit
- circuit package
- circuitry
- silicon wafer
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
An integrated circuit package that is formed at the wafer level. The integrated circuit package occupies a minimum amount of space on an end-use printed circuit board. A pre-fabricated interposer substrate, made of metal circuitry and a dielectric base, has a plurality of metallized openings which are aligned with metallized wirebond pads on the top surface of a silicon wafer. Solder, or conductive adhesive, is deposited through the metallized openings to form the electrical connection between the circuitry on the interposer layer and the circuitry on the wafer. Solder balls are then placed on the metal pad openings on the interposer substrate and are reflowed to form a wafer-level BGA structure. The wafer-level BGA structure is then cut into individual BGA chip packages.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/460,902 US6388335B1 (en) | 1999-12-14 | 1999-12-14 | Integrated circuit package formed at a wafer level |
PCT/US2000/042765 WO2001045167A2 (en) | 1999-12-14 | 2000-12-11 | Integrated circuit package formed at a wafer level |
Publications (2)
Publication Number | Publication Date |
---|---|
NO20022792D0 true NO20022792D0 (en) | 2002-06-12 |
NO20022792L NO20022792L (en) | 2002-06-12 |
Family
ID=23830502
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NO20022792A NO20022792L (en) | 1999-12-14 | 2002-06-12 | Integrated circuit package formed at a silicon wafer level |
Country Status (10)
Country | Link |
---|---|
US (2) | US6388335B1 (en) |
EP (1) | EP1238427A2 (en) |
JP (1) | JP2004537841A (en) |
KR (1) | KR20020059851A (en) |
CN (1) | CN1217410C (en) |
CA (1) | CA2392837A1 (en) |
MY (1) | MY135942A (en) |
NO (1) | NO20022792L (en) |
TW (1) | TW490822B (en) |
WO (1) | WO2001045167A2 (en) |
Families Citing this family (35)
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US7102892B2 (en) * | 2000-03-13 | 2006-09-05 | Legacy Electronics, Inc. | Modular integrated circuit chip carrier |
US6713854B1 (en) | 2000-10-16 | 2004-03-30 | Legacy Electronics, Inc | Electronic circuit module with a carrier having a mounting pad array |
US6487078B2 (en) * | 2000-03-13 | 2002-11-26 | Legacy Electronics, Inc. | Electronic module having a three dimensional array of carrier-mounted integrated circuit packages |
TW515064B (en) * | 2000-03-23 | 2002-12-21 | Seiko Epson Corp | Semiconductor device and its manufacturing method, circuit board and electronic machine |
US6281046B1 (en) * | 2000-04-25 | 2001-08-28 | Atmel Corporation | Method of forming an integrated circuit package at a wafer level |
US7337522B2 (en) * | 2000-10-16 | 2008-03-04 | Legacy Electronics, Inc. | Method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips |
US6524885B2 (en) * | 2000-12-15 | 2003-02-25 | Eaglestone Partners I, Llc | Method, apparatus and system for building an interposer onto a semiconductor wafer using laser techniques |
KR100897314B1 (en) * | 2001-03-14 | 2009-05-14 | 레가시 일렉트로닉스, 인크. | A method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips |
TW523857B (en) * | 2001-12-06 | 2003-03-11 | Siliconware Precision Industries Co Ltd | Chip carrier configurable with passive components |
US6492196B1 (en) * | 2002-01-07 | 2002-12-10 | Picta Technology Inc. | Packaging process for wafer level IC device |
US6800948B1 (en) * | 2002-07-19 | 2004-10-05 | Asat Ltd. | Ball grid array package |
US6979594B1 (en) | 2002-07-19 | 2005-12-27 | Asat Ltd. | Process for manufacturing ball grid array package |
US6987032B1 (en) * | 2002-07-19 | 2006-01-17 | Asat Ltd. | Ball grid array package and process for manufacturing same |
JP2004134648A (en) * | 2002-10-11 | 2004-04-30 | Seiko Epson Corp | Circuit board, mounting structure of ball grid array, electro-optical device, and electronic apparatus |
KR100512971B1 (en) * | 2003-02-24 | 2005-09-07 | 삼성전자주식회사 | Manufacturing method of micro electro mechanical system using solder ball |
JP2004335915A (en) * | 2003-05-12 | 2004-11-25 | Shinko Electric Ind Co Ltd | Method for manufacturing semiconductor device |
JP4130158B2 (en) * | 2003-06-09 | 2008-08-06 | 三洋電機株式会社 | Semiconductor device manufacturing method, semiconductor device |
US6974776B2 (en) * | 2003-07-01 | 2005-12-13 | Freescale Semiconductor, Inc. | Activation plate for electroless and immersion plating of integrated circuits |
KR100541394B1 (en) | 2003-08-23 | 2006-01-10 | 삼성전자주식회사 | NSMD type substrate for ball grid array package and manufacturing method thereof |
US7372151B1 (en) | 2003-09-12 | 2008-05-13 | Asat Ltd. | Ball grid array package and process for manufacturing same |
US7073702B2 (en) * | 2003-10-17 | 2006-07-11 | International Business Machines Corporation | Self-locking wire bond structure and method of making the same |
TWI273682B (en) * | 2004-10-08 | 2007-02-11 | Epworks Co Ltd | Method for manufacturing wafer level chip scale package using redistribution substrate |
WO2006076381A2 (en) * | 2005-01-12 | 2006-07-20 | Legacy Electronics, Inc. | Radial circuit board, system, and methods |
US8610262B1 (en) | 2005-02-18 | 2013-12-17 | Utac Hong Kong Limited | Ball grid array package with improved thermal characteristics |
US7245013B2 (en) * | 2005-07-26 | 2007-07-17 | Infineon Technologies Ag | Substrate based IC-package |
AT9551U1 (en) * | 2006-05-16 | 2007-11-15 | Austria Tech & System Tech | METHOD FOR FIXING AN ELECTRONIC COMPONENT ON A PCB AND A SYSTEM CONSISTING OF A PCB AND AT LEAST ONE ELECTRONIC COMPONENT |
US7824965B2 (en) * | 2007-08-07 | 2010-11-02 | Skyworks Solutions, Inc. | Near chip scale package integration process |
WO2009096216A1 (en) * | 2008-01-30 | 2009-08-06 | Nec Corporation | Electronic part mounting structure, electronic part mounting method, and electronic part mounting substrate |
CN101572257B (en) * | 2008-04-30 | 2011-02-16 | 南茂科技股份有限公司 | Chip packaging tape and chip packaging structure containing same |
TWI387067B (en) * | 2009-03-17 | 2013-02-21 | Chipmos Technologies Inc | Substrateless chip package and fabricating method |
US8367475B2 (en) * | 2011-03-25 | 2013-02-05 | Broadcom Corporation | Chip scale package assembly in reconstitution panel process format |
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JP3176307B2 (en) * | 1997-03-03 | 2001-06-18 | 日本電気株式会社 | Mounting structure of integrated circuit device and method of manufacturing the same |
US5790384A (en) * | 1997-06-26 | 1998-08-04 | International Business Machines Corporation | Bare die multiple dies for direct attach |
US5972734A (en) * | 1997-09-17 | 1999-10-26 | Lsi Logic Corporation | Interposer for ball grid array (BGA) package |
JPH11214421A (en) * | 1997-10-13 | 1999-08-06 | Matsushita Electric Ind Co Ltd | Method for forming electrode of semiconductor element |
JP2000036518A (en) * | 1998-07-16 | 2000-02-02 | Nitto Denko Corp | Wafer scale package structure and circuit board used for the same |
US6081026A (en) * | 1998-11-13 | 2000-06-27 | Fujitsu Limited | High density signal interposer with power and ground wrap |
US6081429A (en) * | 1999-01-20 | 2000-06-27 | Micron Technology, Inc. | Test interposer for use with ball grid array packages assemblies and ball grid array packages including same and methods |
US6281046B1 (en) * | 2000-04-25 | 2001-08-28 | Atmel Corporation | Method of forming an integrated circuit package at a wafer level |
-
1999
- 1999-12-14 US US09/460,902 patent/US6388335B1/en not_active Expired - Fee Related
-
2000
- 2000-07-25 US US09/625,072 patent/US6413799B1/en not_active Expired - Fee Related
- 2000-12-01 MY MYPI20005649A patent/MY135942A/en unknown
- 2000-12-11 CN CN008172021A patent/CN1217410C/en not_active Expired - Fee Related
- 2000-12-11 CA CA002392837A patent/CA2392837A1/en not_active Abandoned
- 2000-12-11 JP JP2001545366A patent/JP2004537841A/en not_active Withdrawn
- 2000-12-11 EP EP00992704A patent/EP1238427A2/en not_active Withdrawn
- 2000-12-11 KR KR1020027007432A patent/KR20020059851A/en not_active Application Discontinuation
- 2000-12-11 WO PCT/US2000/042765 patent/WO2001045167A2/en active Application Filing
- 2000-12-13 TW TW089126574A patent/TW490822B/en not_active IP Right Cessation
-
2002
- 2002-06-12 NO NO20022792A patent/NO20022792L/en not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
CA2392837A1 (en) | 2001-06-21 |
EP1238427A2 (en) | 2002-09-11 |
CN1217410C (en) | 2005-08-31 |
MY135942A (en) | 2008-07-31 |
TW490822B (en) | 2002-06-11 |
WO2001045167A2 (en) | 2001-06-21 |
CN1409872A (en) | 2003-04-09 |
JP2004537841A (en) | 2004-12-16 |
NO20022792L (en) | 2002-06-12 |
US6388335B1 (en) | 2002-05-14 |
WO2001045167A3 (en) | 2002-05-23 |
US6413799B1 (en) | 2002-07-02 |
KR20020059851A (en) | 2002-07-13 |
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