EP1273040A2 - Contactless interconnection system - Google Patents

Contactless interconnection system

Info

Publication number
EP1273040A2
EP1273040A2 EP01924985A EP01924985A EP1273040A2 EP 1273040 A2 EP1273040 A2 EP 1273040A2 EP 01924985 A EP01924985 A EP 01924985A EP 01924985 A EP01924985 A EP 01924985A EP 1273040 A2 EP1273040 A2 EP 1273040A2
Authority
EP
European Patent Office
Prior art keywords
contactless
circuit board
chip package
terminal lands
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01924985A
Other languages
German (de)
French (fr)
Inventor
Augusto P. Panella
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Molex LLC
Original Assignee
Molex LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/548,940 external-priority patent/US6612852B1/en
Priority claimed from US09/548,636 external-priority patent/US6362972B1/en
Application filed by Molex LLC filed Critical Molex LLC
Publication of EP1273040A2 publication Critical patent/EP1273040A2/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Definitions

  • the present invention relates generally interconnections that are obtained 5between computer chip packages and circuit boards without using contacts.
  • semiconductor devices become more complex, the interconnections between the silicon wafer or "die” and appropriate circuit hardware continue to evolve and become more complex because of the difficulty of mechanical interconnections. This is due, in part, to the miniaturization and high density of electronic circuitry. Signals in electronic components are transmitted at faster speeds lOfor high frequency applications and semi-conductor packages are becoming thinner and more compact. In some high-frequency applications, it may be hard to use conventional interconnections that rely upon metal contacts or terminals.
  • the present invention is directed to a connector that does not rely on mechanical contact, but rather uses electrical, or magnetic, field coupling to transmit signals between two terminals or contacts.
  • Another object of the present invention is to provide an interconnection structure that does not use metal-to-metal contact to provide a connection, but uses capacitive coupling
  • a computer chip package is provided that is mounted to a planar support.
  • the support has a plurality of contact pads or traces formed on it and leads or other connections are also provided to connect the chip outputs to the contact pads.
  • the contact pads are mounted on one surface of the support and the support is then positioned 5over a circuit board so that the contact pads of the support are aligned with and in opposition to corresponding opposing contact pads or traces on the circuit board. Capacitive coupling is used to transmit signals between the two opposing contact pads.
  • the compute chip package is mounted to a planar support which also has a plurality of contacts arranged in patterns on both sides of the support. These contacts lOare interconnected with each other by vias so that the package has a series of discrete terminal lands on its lower surface.
  • a circuit board is also provided with an upper surface with a pattern of discrete circuit pads aligned with the terminal lands on the lower surface of the computer chip package.
  • One or more discrete dielectric interposer members are provided between the terminal lands of the chip package and the circuit pads on the circuit board. The interposer members are
  • the interposer members are of a material having a relatively high dielectric constant, preferably greater than 200
  • the interposer members may be adhered to either the terminal lands or the circuit pads,
  • the interposer members may be supported by a planar carrier disposed between the lower surface of the chip package and the upper surface of the circuit board.
  • the planar carrier may be fabricated of dielectric elastomeric material, and the interposer members may be overmolded in the planar carrier member.
  • FIG. 1 is a sectional view taken through one embodiment of a contactless interconnecting system according to the invention
  • FIG. 2 is a sectional view taken through a computer chip package illustrating a second embodiment of the invention.
  • FIG. 3 is a sectional view taken through a computer chip package illustrating a a third embodiment of the invention.
  • FIG. 1 illustrates a first embodiment of a contactless interconnecting system, generally designated 10, that is shown in place with a computer chip package 12 and which provides a lOconnection between the computer chip package 12, and an underlying substrate 14, such as a printed circuit board.
  • FIG. 2 illustrates a second embodiment of a contactless interconnecting system, generally designated 10 A, also between chip package 12 and circuit board 14.
  • Computer chip package 12 in both embodiments 10 and 10A may include a silicon wafer 16 mounted on an upper surface 18 of a wall 20 of a housing 22 within which the silicon wafer
  • a pattern of discrete, conductive terminal lands 24 are deposited on the upper surface 18 of the wall 20.
  • the silicon wafer 16 is connected to these conductive lands 24 by a plurality of leads 26.
  • the terminal lands 24 are connected through the lower support wall 18 by way of individual respective vias 28 to a matching pattern of discrete, conductive terminal lands, or contact pads 30 that are disposed on the lower surface 32 of the
  • the circuit board 14 of either interconnecting system 10 or 10A also has a substantially planar upper surface 34 that is arranged parallel to the lower surface 32 of chip package 12.
  • a pattern of discrete circuit pads 36 may be disposed on upper surface 34 in a pattern such that each one of the pads 36 is aligned with a single one of the terminal lands 30 on the lower surface
  • circuit pads 28 are electrically connected to respective circuitry on the circuit board 14 in a conventional manner.
  • a plurality of discrete interposer members 38 are located between the terminal lands 30 on the bottom of the support wall 20 and the circuit pads 36 disposed on the top, opposing surface of the circuit board 14.
  • the interposer members 38, 38' of the embodiments are spaced
  • the interposer members are preferably fabricated of a material having a high dielectric constant relative to the dielectric constant of the material in the gaps 40 to prevent coupling between catercornered, or adjacent terminal lands 30 and circuit pads 36.
  • the dielectric constant of the interposer members 38, 38' 5 is at least an order of magnitude greater than that of the material in the gaps 40, 40', typically air and the dielectric constant of the interposer members 38, 38' is preferably at least 200.
  • the terminal lands are preferably of similar or the same dimensions as the circuit board pads 36 and aligned therewith in order to lOensure capacitive coupling between desired pairs of lands and pads, rather than undesired coupling between angled, adjacent lands and pads.
  • the interposer members 38 in FIG. 1 are supported by a carrier member 42 that is preferably planar and which is disposed between the lower surface 32 of the chip package and the upper surface 34 of the circuit board.
  • This carrier member 42 may, as shown, extend for the
  • the interposer members may be ove ⁇ nolded to the carrier member 42 and the carrier member 42 may include a series of holes formed therein that will accommodate the
  • the dielectric constant of the interposer members 38 preferably is an
  • FIG. 2 shows a second embodiment of the contactless interconnecting system 10A wherein the carrier member 42 used in the first embodiment of FIG. 1 has been eliminated.
  • the interposer members 38' are adhered to either or both of terminal lands 30
  • interposer members may be deposited onto either terminal lands 30 or circuit pads 36 by a suitable printing method.
  • gaps 40' again are provided between the interposer members.
  • the dielectric constant of the interposer members 38' should be an order of magnitude greater than any material (i.e., air) filling the gaps 40' to prevent catercornered coupling.
  • the interposer members 38, 38' are discrete members and are separated, as at gaps 40, 40' and described above.
  • the interposer members are of sizes substantially the same as the sizes of aligned terminal lands 30 and circuit pads 36. Electrical signals are capacitively transferred from terminal lands 30 through the interposer members 38, 38' to the circuit pads 36.
  • Gaps 40, 40' between the interposer members with a lower dielectric constant than that of the interposer members provide a dielectric break between catercornered terminal lands 30 and 5circuit pads 36. Since electrical signals prefer to be coupled through high dielectric constant materials, the signals will tend to not cross the gaps 40, 40' between the interposer members of relatively higher dielectric constant materials. Therefore, the discrete or separated interposer members considerably reduce cross-coupling and cross-talk between catercornered sets of terminal lands 30 and circuit pads 36.
  • FIG. 15 A third embodiment of the invention is illustrated in FIG. 3, wherein a contactless interconnecting system 110, is illustrated between a computer chip package 112 and a substrate 114, such as a circuit board .
  • the chip package 112 includes a housing 115 having a bottom support wall 116, and a silicon wafer 118 is mounted on the substantially planar upper surface 120 of the support wall
  • the support wall 116 supports a pattern of discrete terminal lands 122 are provided on upper surface 120 of wall 116 and that are interconnected to the silicon wafer 118 by respective leads 124.
  • the pattern of terminal lands 122 define a plurality of gaps 123 therebetween.
  • the support wall 116 in this embodiment provides the same function as the interposer members utilized in the embodiments of FIGS. 1 and 2.
  • the circuit board 114 of the system 110 is disposed in a generally parallel relationship below the support wall 116 of the chip package 112.
  • the circuit board 114 has a planar upper surface 126 with a pattern of discrete circuit pads 128 aligned with terminal lands 122.
  • the pattern of discrete circuit pads 128 also define spaces 129 therebetween similar to the gaps 123 defined by the pattern of discrete terminal lands 122.
  • the circuit pads 128 are electrically
  • the support wall 116 of the computer chip package 112 is disposed directly between terminal lands 122 of the chip package and circuit pads 128 of circuit board 114.
  • the lower surface 121 of the wall 16 mounts directly on the circuit pads 128.
  • the wall may be fabricated of a material having a high dielectric constant relative to the material (e.g., air) filling the gaps 123 and spaces 129 to prevent cross coupling between adjacent terminal lands 122 and prevent cross coupling between 5adjacent circuit pads 128.
  • the wall is fabricated of a material that has a dielectric constant of at least 200. Of course, a variety of materials or compositions could provide such a desired dielectric constant.
  • the thickness of the wall 116 should be thin relative to the width of gaps 123 lObetween terminal lands 122 and spaces 129 between circuit pads 128 to promote coupling between aligned terminal lands 122 and circuit pads 128 and to prohibit cross coupling between adjacent terminal lands 122 or adjacent circuit pads 128.
  • the wall 16 provides both a support structure as well as an interposing dielectric medium in a plurality of capacitors where terminal lands 122 and the circuit pads 128 act as half-capacitors on opposite sides of the interposing dielectric medium provided by wall 116. Signals are capacitively transferred between the terminal lands 122 of the chip package and the circuit pads 128 of the circuit board 114. Therefore, all other extraneous interconnecting
  • circuit board 114 along with circuit pads 128, can be interconnectingly mounted immediately adjacent the bottom surface of the support wall 116 of the chip package.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Combinations Of Printed Boards (AREA)
  • Connecting Device With Holders (AREA)

Abstract

A contactless interconnecting system is provided between a computer chip package and a circuit board. The chip package has a substantially planar lower surface with a pattern of discrete terminal lands. The circuit board has a substantially planar upper surface spaced from and generally parallel to the lower surface of the chip package. A pattern of discrete circuit pads on the upper surface are aligned with the terminal lands. A plurality of discrete interposer members are disposed between the terminal lands and the circuit pads and are in a pattern corresponding to and aligned with the aligned patterns of the terminal lands and circuit pads. The interposer members are preferably of a material having a higher dielectric constant that of the material filling the gaps between interposer members.

Description

CONTACTLESS INTERCONNECTION SYSTEM
Background of the Invention
The present invention relates generally interconnections that are obtained 5between computer chip packages and circuit boards without using contacts. As semiconductor devices become more complex, the interconnections between the silicon wafer or "die" and appropriate circuit hardware continue to evolve and become more complex because of the difficulty of mechanical interconnections. This is due, in part, to the miniaturization and high density of electronic circuitry. Signals in electronic components are transmitted at faster speeds lOfor high frequency applications and semi-conductor packages are becoming thinner and more compact. In some high-frequency applications, it may be hard to use conventional interconnections that rely upon metal contacts or terminals.
Known mechanical interconnections use conventional terminal pins and sockets or other male and female configurations or interengaging spring connections. With these metal-to-metal
^interconnections, it is essential to provide a wiping action between the terminals to remove contaminants or oxidants. In miniature semi-conductor interconnections, the terminals are so small that it is hard to provide this needed wiping and attain a reliable contact force between opposing terminals, or contacts. Traditional solder connections are difficult if at all possible because of the extremely complex hard tooling required for use with miniaturized or closely
20spaced components of a semi-conductor interconnecting system.
Accordingly, the present invention is directed to a connector that does not rely on mechanical contact, but rather uses electrical, or magnetic, field coupling to transmit signals between two terminals or contacts.
Summary of the Invention
25 It is therefore a general object of the present invention to provide a new and improved contactless interconnecting system that is particularly suitable for providing connections between computer chip packages and circuit boards.
Another object of the present invention is to provide an interconnection structure that does not use metal-to-metal contact to provide a connection, but uses capacitive coupling
30between first and second arrays of terminals which are separated by a dielectric material. In one embodiment of the invention, a computer chip package is provided that is mounted to a planar support. The support has a plurality of contact pads or traces formed on it and leads or other connections are also provided to connect the chip outputs to the contact pads. The contact pads are mounted on one surface of the support and the support is then positioned 5over a circuit board so that the contact pads of the support are aligned with and in opposition to corresponding opposing contact pads or traces on the circuit board. Capacitive coupling is used to transmit signals between the two opposing contact pads.
In another embodiment, the compute chip package is mounted to a planar support which also has a plurality of contacts arranged in patterns on both sides of the support. These contacts lOare interconnected with each other by vias so that the package has a series of discrete terminal lands on its lower surface. A circuit board is also provided with an upper surface with a pattern of discrete circuit pads aligned with the terminal lands on the lower surface of the computer chip package. One or more discrete dielectric interposer members are provided between the terminal lands of the chip package and the circuit pads on the circuit board. The interposer members are
15arranged in a pattern that corresponds to the pattern of the terminal lands and circuit pads, and the interposer members are further aligned with and between the terminal lands and circuit pads. The interposer members are of a material having a relatively high dielectric constant, preferably greater than 200
The interposer members may be adhered to either the terminal lands or the circuit pads,
20or as described in another embodiment, the interposer members may be supported by a planar carrier disposed between the lower surface of the chip package and the upper surface of the circuit board. The planar carrier may be fabricated of dielectric elastomeric material, and the interposer members may be overmolded in the planar carrier member.
Other objects, features and advantages of the invention will be apparent from the 5following detailed description taken in connection with the accompanying drawings.
Brief Description of the Drawings
The features of this invention which are believed to be novel are set forth with particularity in the appended claims. The invention, together with its objects and the advantages thereof, may be best understood by reference to the following description taken in conjunction 30with the accompanying drawings, in which like reference numerals identify like elements in the figures and in which: FIG. 1 is a sectional view taken through one embodiment of a contactless interconnecting system according to the invention;
FIG. 2 is a sectional view taken through a computer chip package illustrating a second embodiment of the invention; and,
5 FIG. 3 is a sectional view taken through a computer chip package illustrating a a third embodiment of the invention.
Detailed Description of the Preferred Embodiments
FIG. 1 illustrates a first embodiment of a contactless interconnecting system, generally designated 10, that is shown in place with a computer chip package 12 and which provides a lOconnection between the computer chip package 12, and an underlying substrate 14, such as a printed circuit board. FIG. 2 illustrates a second embodiment of a contactless interconnecting system, generally designated 10 A, also between chip package 12 and circuit board 14.
Computer chip package 12 in both embodiments 10 and 10A may include a silicon wafer 16 mounted on an upper surface 18 of a wall 20 of a housing 22 within which the silicon wafer
15is disposed. A pattern of discrete, conductive terminal lands 24 are deposited on the upper surface 18 of the wall 20. The silicon wafer 16 is connected to these conductive lands 24 by a plurality of leads 26. In this embodiment, the terminal lands 24 are connected through the lower support wall 18 by way of individual respective vias 28 to a matching pattern of discrete, conductive terminal lands, or contact pads 30 that are disposed on the lower surface 32 of the
20support wall 18 of the chip package 12.
The circuit board 14 of either interconnecting system 10 or 10A also has a substantially planar upper surface 34 that is arranged parallel to the lower surface 32 of chip package 12. A pattern of discrete circuit pads 36 may be disposed on upper surface 34 in a pattern such that each one of the pads 36 is aligned with a single one of the terminal lands 30 on the lower surface
2532 of the chip package support wall. The circuit pads 28 are electrically connected to respective circuitry on the circuit board 14 in a conventional manner.
A plurality of discrete interposer members 38 are located between the terminal lands 30 on the bottom of the support wall 20 and the circuit pads 36 disposed on the top, opposing surface of the circuit board 14. The interposer members 38, 38' of the embodiments are spaced
30from each other, as by intervening gaps 40, 40' which are shown as being spaced apart horizontally in FIGS. 1 and 2, and are in a pattern corresponding to and generally aligned with the patterns of both the terminal lands 30 and circuit pads 36. The interposer members are preferably fabricated of a material having a high dielectric constant relative to the dielectric constant of the material in the gaps 40 to prevent coupling between catercornered, or adjacent terminal lands 30 and circuit pads 36. The dielectric constant of the interposer members 38, 38' 5is at least an order of magnitude greater than that of the material in the gaps 40, 40', typically air and the dielectric constant of the interposer members 38, 38' is preferably at least 200. However, as signal frequencies increase the magnitude of the dielectric constant required of the interposer members may decrease. In these embodiments, the terminal lands are preferably of similar or the same dimensions as the circuit board pads 36 and aligned therewith in order to lOensure capacitive coupling between desired pairs of lands and pads, rather than undesired coupling between angled, adjacent lands and pads.
The interposer members 38 in FIG. 1 are supported by a carrier member 42 that is preferably planar and which is disposed between the lower surface 32 of the chip package and the upper surface 34 of the circuit board. This carrier member 42 may, as shown, extend for the
15entire length and width of the computer chip package 12 and is preferably fabricated from a dielectric material, such as plastic, or formed from a dielectric and flexible material, such as a rubber or elastomer. The interposer members may be oveπnolded to the carrier member 42 and the carrier member 42 may include a series of holes formed therein that will accommodate the
- overmolding process. The dielectric constant of the interposer members 38 preferably is an
20order of magnitude greater than that of the dielectric constant of the carrier member 42 to prohibit undesirable and unchosen catercornered coupling.
FIG. 2 shows a second embodiment of the contactless interconnecting system 10A wherein the carrier member 42 used in the first embodiment of FIG. 1 has been eliminated. In this embodiment, the interposer members 38' are adhered to either or both of terminal lands 30
25and circuit pads 36. For example, interposer members may be deposited onto either terminal lands 30 or circuit pads 36 by a suitable printing method. However, gaps 40' again are provided between the interposer members. Again, the dielectric constant of the interposer members 38' should be an order of magnitude greater than any material (i.e., air) filling the gaps 40' to prevent catercornered coupling.
30 In both embodiments of the interconnecting systems 10 and 10A shown in FIGS. 1 and
2, the interposer members 38, 38' are discrete members and are separated, as at gaps 40, 40' and described above. Preferably, the interposer members are of sizes substantially the same as the sizes of aligned terminal lands 30 and circuit pads 36. Electrical signals are capacitively transferred from terminal lands 30 through the interposer members 38, 38' to the circuit pads 36. Gaps 40, 40' between the interposer members with a lower dielectric constant than that of the interposer members provide a dielectric break between catercornered terminal lands 30 and 5circuit pads 36. Since electrical signals prefer to be coupled through high dielectric constant materials, the signals will tend to not cross the gaps 40, 40' between the interposer members of relatively higher dielectric constant materials. Therefore, the discrete or separated interposer members considerably reduce cross-coupling and cross-talk between catercornered sets of terminal lands 30 and circuit pads 36.
10 It should be understood that the use of such terms as "upper", "lower", "top", "bottom",
"vertical" and the like herein and in the claims hereof is not in any way intended to be limiting. Such terms simply provide a clear and concise description and understanding of the invention as viewed in the drawings. Obviously, interconnecting systems 10 and 10A are omni-directional in use or application.
15 A third embodiment of the invention is illustrated in FIG. 3, wherein a contactless interconnecting system 110, is illustrated between a computer chip package 112 and a substrate 114, such as a circuit board .
The chip package 112 includes a housing 115 having a bottom support wall 116, and a silicon wafer 118 is mounted on the substantially planar upper surface 120 of the support wall
20116. The support wall 116 supports a pattern of discrete terminal lands 122 are provided on upper surface 120 of wall 116 and that are interconnected to the silicon wafer 118 by respective leads 124. The pattern of terminal lands 122 define a plurality of gaps 123 therebetween. The support wall 116 in this embodiment provides the same function as the interposer members utilized in the embodiments of FIGS. 1 and 2.
25 The circuit board 114 of the system 110 is disposed in a generally parallel relationship below the support wall 116 of the chip package 112. The circuit board 114 has a planar upper surface 126 with a pattern of discrete circuit pads 128 aligned with terminal lands 122. The pattern of discrete circuit pads 128 also define spaces 129 therebetween similar to the gaps 123 defined by the pattern of discrete terminal lands 122. The circuit pads 128 are electrically
30connected to respective circuitry on the circuit board 114.
The invention contemplates that the support wall 116 of the computer chip package 112 is disposed directly between terminal lands 122 of the chip package and circuit pads 128 of circuit board 114. In this embodiment, the lower surface 121 of the wall 16 mounts directly on the circuit pads 128. In another embodiment, the wall may be fabricated of a material having a high dielectric constant relative to the material (e.g., air) filling the gaps 123 and spaces 129 to prevent cross coupling between adjacent terminal lands 122 and prevent cross coupling between 5adjacent circuit pads 128. In a further embodiment, the wall is fabricated of a material that has a dielectric constant of at least 200. Of course, a variety of materials or compositions could provide such a desired dielectric constant. However, as signal frequencies increase, the magnitude of the dielectric constant required of the wall 116 may decrease. In an additional embodiment, the thickness of the wall 116 should be thin relative to the width of gaps 123 lObetween terminal lands 122 and spaces 129 between circuit pads 128 to promote coupling between aligned terminal lands 122 and circuit pads 128 and to prohibit cross coupling between adjacent terminal lands 122 or adjacent circuit pads 128.
It can be seen from the above, that a portion of the computer chip package (i.e., wall 116) is efficiently used to provide an electromagnetic coupling between silicon wafer 118 and circuit
15board 114. In essence, the wall 16 provides both a support structure as well as an interposing dielectric medium in a plurality of capacitors where terminal lands 122 and the circuit pads 128 act as half-capacitors on opposite sides of the interposing dielectric medium provided by wall 116. Signals are capacitively transferred between the terminal lands 122 of the chip package and the circuit pads 128 of the circuit board 114. Therefore, all other extraneous interconnecting
20components are eliminated, and the circuit board 114, along with circuit pads 128, can be interconnectingly mounted immediately adjacent the bottom surface of the support wall 116 of the chip package.
It will be understood that the invention may be embodied in other specific forms without departing from the spirit or central characteristics thereof. The present examples and
25embodiments, therefore, are to be considered in all respects as illustrative and not restrictive, and the invention is not to be limited to the details given herein.

Claims

Claims:
1. A contactless interconnecting system between a computer chip package and a circuit board, comprising: a computer chip package having a planar lower surface with a pattern of discrete terminal lands disposed thereon; a circuit board having a planar upper surface spaced from and generally parallel to the lower surface of the chip package, the circuit board including a pattern of discrete circuit pads disposed thereon and aligned with said terminal lands; and, a plurality of discrete interposer members between the terminal lands and the circuit pads, the interposer members being in a pattern corresponding to and aligned with the aligned patterns of the terminal lands and circuit pads.
2. The contactless interconnecting system of claim 1, wherein said terminal lands are disposed on a lower surface of a wall of the computer chip package, the terminal lands being connected by vias through the wall to leads from a silicon wafer of the package.
3. The contactless interconnecting system of claim 1 , wherein said interposer members are supported by a dielectric carrier member disposed between the lower surface of the chip package and the upper surface of the circuit board.
4. The contactless interconnecting system of claim 3, wherein said interposer members are overmolded in the carrier member.
5. The contactless interconnecting system of claim 3, wherein said planar carrier member is fabricated of an elastomeric material.
6. The contactless interconnecting system of claim 1, wherein said interposer members are adhered to one of said terminal lands or circuit pads.
7. The contactless interconnecting system of claim 1, wherein said discrete interposer members define gaps therebetween, said interposer members being of a material having a higher dielectric constant than that of the material filling the gaps.
8. A contactless interconnecting system between a computer chip package and a circuit board, comprising: a computer chip package having a lower surface with a pattern of discrete terminal lands disposed thereon; a circuit board having an upper surface spaced from and generally parallel to the lower surface of the chip package and including a pattern of discrete circuit pads aligned with said terminal lands; and, a plurality of discrete interposer members supported by a carrier member disposed between the lower surface of the chip package and the upper surface of the circuit board, the carrier member extending widthwise between said chip package lower surface and said circuit board upper surface, the interposer members being arranged in a pattern corresponding to and generally aligned with said terminal land and circuit pad patterns, and said interposer members having a higher dielectric constant than that of said carrier member.
9. The contactless interconnecting system of claim 8, wherein said terminal lands are on a lower surface of a wall of the computer chip package, the terminal lands being connected by vias through the wall to leads from a silicon wafer of the package.
10. The contactless interconnecting system of claim 8, wherein said interposer members are overmolded on the planar carrier member.
11. The contactless interconnecting system of claim 8, wherein said planar carrier member is fabricated of dielectric elastomeric material.
12. A contactless interconnecting system between a computer chip package and a circuit board, comprising: a computer chip disposed in a package, the computer chip having a plurality of leads extending therefrom for connecting circuit of said computer chip to other circuits; the package including a support wall for supporting the chip and for mounting the package to a circuit board, the support wall being formed from a material having a given dielectric constant, said package further including a plurality of discrete, conductive terminal lands disposed on the upper surface of said support wall and connected to said chip leads; and, a circuit board disposed below said package support wall, the circuit board including a substantially planar upper surface having a pattern of discrete circuit pads disposed thereon in a pattern that locates a single circuit pad in alignment with a single terminal land of said package.
13. The contactless interconnecting system of claim 12, wherein said support wall forms an exterior wall of said package.
14. The contactless interconnecting system of claim 12, wherein said support wall has a dielectric constant of at least 200.
15. A contactless interconnecting system between a computer chip package and a circuit board, comprising: a computer chip package including a housing having an exterior wall including a planar inner surface and the wall having a preselected dielectric material; a silicon wafer mounted in the housing; a pattern of discrete terminal lands on the interior surface of said wall and electrically coupled to the silicon wafer; and, a circuit board juxtaposed against the exterior of said wall and including a substantially planar surface having a pattern of discrete circuit pads aligned with said terminal lands through the wall.
16. The contactless interconnecting system of claim 15 , wherein said wall is fabricated of a material having a dielectric constant of at least 200.
EP01924985A 2000-04-13 2001-04-12 Contactless interconnection system Withdrawn EP1273040A2 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US09/548,940 US6612852B1 (en) 2000-04-13 2000-04-13 Contactless interconnection system
US548940 2000-04-13
US09/548,636 US6362972B1 (en) 2000-04-13 2000-04-13 Contactless interconnection system
US548636 2000-04-13
PCT/US2001/012020 WO2001080316A2 (en) 2000-04-13 2001-04-12 Contactless interconnection system

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EP1273040A2 true EP1273040A2 (en) 2003-01-08

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EP (1) EP1273040A2 (en)
JP (1) JP3701242B2 (en)
KR (1) KR20020090233A (en)
CN (1) CN1237612C (en)
AU (1) AU2001251588A1 (en)
TW (1) TW547773U (en)
WO (1) WO2001080316A2 (en)

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CN100336218C (en) * 2003-08-25 2007-09-05 威盛电子股份有限公司 High-frequency IC multi-bus knot tying structure and method

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DE2902002A1 (en) * 1979-01-19 1980-07-31 Gerhard Krause Three=dimensional integrated circuits - mfd. by joining wafer stack with contacts through conductive adhesive
JPH0583011A (en) * 1991-09-25 1993-04-02 Sumitomo Electric Ind Ltd Input/output coupling device for package for semiconductor device
US6728113B1 (en) * 1993-06-24 2004-04-27 Polychip, Inc. Method and apparatus for non-conductively interconnecting integrated circuits
JPH0998005A (en) * 1995-09-29 1997-04-08 Nec Corp Printed circuit board
US6396712B1 (en) * 1998-02-12 2002-05-28 Rose Research, L.L.C. Method and apparatus for coupling circuit components

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* Cited by examiner, † Cited by third party
Title
See references of WO0180316A2 *

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CN1237612C (en) 2006-01-18
KR20020090233A (en) 2002-11-30
WO2001080316A3 (en) 2002-03-21
TW547773U (en) 2003-08-11
AU2001251588A1 (en) 2001-10-30
CN1422440A (en) 2003-06-04
JP2003531496A (en) 2003-10-21
JP3701242B2 (en) 2005-09-28
WO2001080316A2 (en) 2001-10-25

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