KR20020090233A - Contactless interconnection system - Google Patents

Abstract

The contactless interconnect system is provided between the computer chip package and the circuit board. The chip package has a substantially flat lower surface with discrete terminal regions. The circuit board generally has a top surface parallel and spaced apart from the bottom surface of the chip package. The pattern of discrete circuit pads on the top surface is aligned with the terminal area. The plurality of discontinuous interposer members is a pattern disposed between the terminal region and the circuit board and corresponding to the aligned pattern of the terminal region and the circuit pad. The interposer members are preferably materials having a higher dielectric constant than the material filling the gap between the interposer members.

Description

Contactless interconnect system {CONTACTLESS INTERCONNECTION SYSTEM}

As semiconductor devices become more complex, the interconnections between silicon wafers or “dies” and appropriate circuit hardware have developed and become more complex because of the difficulty of mechanical interconnections. This is due in part to the high density and miniaturization of electrical circuits. In electronic components, signals are being delivered at higher speeds to high frequency applications, and semiconductor packages are becoming thinner and smaller. In some high frequency applications, it will be difficult to use conventional interconnects that rely on metal contacts or terminals.

Known mechanical interconnects are used for conventional terminal pins and sockets or other female, male or interconnect spring connections. In these metal-to-metal interconnects, a wiping action must be provided essentially to remove contaminants or strongly oxidizing materials between the terminals. In small semiconductor interconnections, the terminals are so small that it is difficult to provide this required wiping and to ensure reliable contact force between opposing terminals or contacts. Conventional solder connections are difficult, if possible, because they require extremely complex and difficult tooling to be used in miniaturized or closely spaced components of semiconductor interconnect systems.

Accordingly, the present invention relates to a connector that uses electrical or magnetic field coupling to transfer signals between two terminals or contacts without relying on mechanical contacts.

The present invention generally relates to interconnection achieved between a computer chip package and a circuit board without the use of contacts.

Features of the invention which are considered to be novel will be described in particular in the appended claims. The invention together with the objects and advantages will be better understood by reference to the following description in conjunction with the accompanying drawings, in which like elements of figures are represented by like reference numerals.

1 is a cross-sectional view of one embodiment of a contactless interconnect system in accordance with the present invention.

2 is a cross-sectional view of a computer chip package shown in a second embodiment of the present invention.

3 is a cross-sectional view of a computer chip package of a third embodiment of the present invention.

It is therefore an object of the present invention to provide a novel and improved contactless interconnect system which is particularly suitable for providing a connection between a computer chip package and a circuit board.

Another object of the present invention is to provide an interconnect structure using capacitive coupling between first and second terminal arrays separated by dielectric material without using metal to metal contacts to provide a connection.

In one embodiment of the invention, a computer chip package is provided to be mounted on a flat support. The support has a plurality of contact pads or traces formed thereon, and leads or other connections are provided for connecting the chip outputs to the contact pads. The contact pads are mounted on the surface of the support and the support is positioned on the circuit board such that the contact pads of the support are aligned to face the corresponding contact pads or traces of the circuit board. Capacitive coupling is used to transfer signals between two opposing contact pads.

In another embodiment, a computer chip package is mounted to a flat support having a plurality of contacts aligned in a pattern on both sides of the support. These contacts are interconnected by vias so that the package has a series of discrete terminal lands on its bottom surface. The circuit board is also provided on the top surface in a pattern of discrete terminal circuit pads aligned with the terminal area of the bottom surface of the computer chip package. One or more discrete dielectric interposer members are provided between the terminal region of the chip package and the circuit pad of the circuit board. The interposer members are aligned in a pattern corresponding to the pattern of the terminal region and the circuit pad, and the interposer members are aligned between the terminal region and the circuit pad. The interposer member is preferably of a material having a relatively high dielectric constant of at least 200.

The interposer member may be attached to the terminal area or circuit pad or as described in other embodiments, the interposer member may be supported by a flat carrier disposed between the lower surface of the chip package and the upper surface of the circuit board. . The flat carrier can be made of dielectric elastomeric material and the interposer member can be overmold to the flat carrier member.

Other objects, features and advantages of the present invention will become apparent from the following detailed description with reference to the accompanying drawings.

1 is a contactless interconnect, generally designated 10, which is suitably positioned in a computer chip package 12 and provides a connection between the computer chip package 12 and a substrate substrate 14, such as a printed circuit board. One embodiment of a system is shown. 2 shows a second embodiment of a contactless interconnect system, generally indicated at 10A, between the chip package 12 and the circuit board 14.

The computer chip package of the two embodiments 10, 10A may comprise a silicon wafer mounted to the top surface 18 of the wall 20 of the housing 22 in which the silicon wafer is disposed. The pattern of discontinuous conductive terminal regions 24 is metallized on the upper surface 18 of the wall 20. The silicon wafer 16 is connected to the conductive region 24 by a plurality of leads 26. In this embodiment, the terminal regions 24 have individual vias 28 in the discontinuous matching pattern, conductive terminal region or contact pad 30 disposed on the lower surface 32 of the support wall 18 of the chip package 12. Is connected via the lower support wall 18.

The circuit board 14 of the interconnect system 10 or 10A also has a substantially flat top surface 34 arranged parallel to the bottom surface 32 of the chip package 12. The pattern of discontinuous circuit pads 36 may be disposed on the top surface 34 in a pattern in which each of the pads 36 is aligned with only one of the terminal regions 30 of the bottom surface 32 of the chip package support wall. have. The circuit pad 28 may be electrically connected to each circuit of the circuit board 14 in a conventional manner.

A plurality of discontinuous interposer members 38 are positioned between the terminal region 30 of the bottom of the support wall 20 and the circuit pads 36 disposed on opposite surfaces of the upper portion of the circuit board 14. The interposer members 38, 38 ′ of these embodiments are spaced apart from each other by intervening gaps 40, 40 ′, shown horizontally spaced apart in FIGS. 1 and 2, and with the two terminal regions 30. The pattern corresponds to and generally aligned with the patterns of the circuit pad 36. The interposer member is preferably made of a material having a high dielectric constant relative to the dielectric constant of the gap 40 material to prevent the diagonal or adjacent coupling between the adjacent terminal region 30 and the circuit pad 36. The dielectric constant of the interposer members 38, 38 'has a magnitude at least greater than the dielectric constant of the material of the gaps 40, 40', generally air, and the dielectric constant of the interposer members 38, 38 'is good. Preferably at least 200. However, as the signal frequency increases, the magnitude of the dielectric constant required for the interposer member may decrease. In this embodiment, the terminal region is preferably of similar or identical dimensions to the circuit board pads 36 and is capacitive between the region and the desired pairs of pads without undesirable coupling between adjacent regions and pads. Aligned to be a bond.

The interposer members 38 of FIG. 1 are preferably flat and supported by a carrier member 42 disposed between the bottom surface of the chip package and the top surface 34 of the circuit board. The carrier member 42 extends the entire length and width of the computer chip package 12 and is preferably made of a dielectric material such as plastic or formed of a dielectric and flexible material such as rubber or elastomer, as shown. . The interposer member is overmolded in the carrier member 42, and the carrier member 42 may include a series of holes formed to accommodate the overmolding process. The dielectric constant of the interposer member 38 preferably has a size greater than the dielectric constant of the carrier member 42 to prevent undesirable and unselected diagonal coupling.

FIG. 2 shows a second embodiment of a contactless interconnect system 10A with the carrier member 42 used in the first embodiment of FIG. 1 removed. In this embodiment, the interposer member 38 ′ is bonded to one or both of the terminal regions 30 and the circuit pads 36. For example, the interposer member may be metallized onto the terminal region 30 or the circuit pad 36 by a suitable printing method. However, the gap 40 'is again provided between the interposer members. Again, the dielectric constant of interposer member 38 'must be greater than any material (e.g., air) filling gap 40' to prevent diagonal coupling.

In both embodiments of the interconnect systems 10, 10A shown in Figures 1 and 2, the interposer members 38, 38 'are discontinuous members and are separated in the gaps 40, 40' as described above. Preferably, the interposer member is sized equally to the size of the substantially aligned terminal region 30 and circuit pad 36. Electronic signals are capacitively transferred from the terminal region 30 to the circuit pads 36 through the interposer members 38, 38 ′. The gaps 40, 40 ′ between the interposer members having a lower dielectric constant than the interposer members provide dielectric isolation between the diagonal terminal region 30 and the circuit pad 36. Since the electronic signal is preferably coupled through a high dielectric constant material, the signal does not cross the gaps 40 and 40 'between the relatively high dielectric constant materials. Thus, the discontinuous or separated interposer members significantly reduce cross-coupling and crosstalk between the terminal area 30 and the diagonal set of circuit pads 36.

It is to be understood that the use of the terms "top", "bottom", "ceiling", "bottom", "vertical" and the like in the present specification and claims is not limited. These terms provide an understanding of the present invention in light of a simple and concise description and drawings. Clearly, interconnect systems 10 and 10A are omni directional in use or application.

A third embodiment of the present invention is shown in FIG. 3 in which a contactless interconnect system 110 is shown between a computer chip package 112 and a substrate 114 such as a circuit board.

The chip package 112 includes a housing 115 having a bottom support wall 116, and the silicon wafer 118 is mounted to the substantially flat top surface 120 of the support wall 116. The support wall 116 supports a pattern of discrete terminal regions 122 provided on the top surface 120 of the wall 116 and is interconnected to the silicon wafer 118 by respective leads 124. The pattern of the terminal region 122 defines a plurality of gaps 123 therebetween. The support wall 116 of this embodiment provides the same function as the interposer member utilized in the embodiment of Figs.

The circuit board 114 of the system 110 is disposed in a generally parallel relationship under the support wall of the chip package 112. The circuit board 114 has a flat top surface 126 having a pattern of discrete circuit pads 128 that are aligned with the terminal region 122. The pattern of discrete circuit pads 128 defines a space 129 similar to the gap 123 therebetween defined by the pattern of discrete terminal regions 122. The circuit pad 128 is electrically connected to each circuit on the circuit board 114.

The present invention intends that the support wall 116 of the computer chip package 112 is disposed directly between the terminal region 122 of the chip package and the circuit pad 128 of the circuit board 114. In this embodiment, the bottom surface 121 of the wall 16 is mounted directly to the circuit pad 128. In another embodiment, the wall is a material (e.g., filling the gap 123 and space 129 to prevent cross coupling between adjacent terminal regions 122 and to prevent cross coupling between adjacent circuit pads 128). Can be made of materials with a high dielectric constant. In another embodiment, the wall is made of a material having a dielectric constant of at least 200. Of course, various materials or mixtures can provide the desired dielectric constant. However, as the signal frequency increases, the magnitude of the dielectric constant required for the wall 116 may decrease. In a further embodiment, the thickness of the wall 116 promotes coupling between the aligned terminal regions 122 and the circuit pads 128 and cross couplings between adjacent terminal regions 122 or adjacent circuit pads 128. To prevent this, the gap 123 between the terminal regions 122 and the width of the space 129 between the circuit pads 128 will be thinner.

As can be seen above, a portion (eg, wall 116) of the computer chip package is effectively used to provide electromagnetic coupling between the silicon wafer 118 and the circuit board 114. Essentially, the wall 116 is a plurality of capacitors in which the terminal region 122 and the circuit pad 128 act as half-capacitors on opposite sides of the interposed dielectric medium provided by the wall 116. It serves as an intermediate dielectric medium as well as a support structure. The signal is capacitively transferred between the terminal region 122 of the chip package and the circuit pad 128 of the circuit board 114. Thus, all other external interconnect components are removed, and with the circuit pad 128, the circuit board 114 can be interconnected and mounted directly adjacent to the bottom surface of the support wall 116 of the chip package. .

It will be appreciated that the invention may be embodied in other specific forms without departing from its spirit or central feature. Accordingly, the present examples and embodiments are to be considered as illustrative and not restrictive, and are not limited to the details.

Claims (16)

A solid-state interconnect system between a computer chip package and a circuit board, A computer chip package having a flat bottom surface having a pattern of discrete terminal regions; A circuit board having a flat top surface parallel to and spaced apart from the bottom surface of the chip package, the circuit board comprising a pattern of discrete circuit pads aligned with and disposed on the terminal region; And a plurality of discrete interposer members arranged between the terminal regions and the circuit pads and having a corresponding pattern with the aligned pattern of the terminal regions and the circuit pads. 10. The contactless interconnect system of claim 1 wherein the terminal region is disposed on a bottom surface of a wall of a computer chip package, the terminal region being connected by vias to leads through the wall from the silicon wafer of the package. . The contactless interconnect system of claim 1 wherein the interposer members are supported by a dielectric carrier member disposed between the bottom surface of the chip package and the top surface of the circuit board. 4. The contactless interconnect system of claim 3 wherein the interposer members are overmolded on a carrier member. 4. The contactless interconnect system of claim 3 wherein the flat carrier member is made of an elastomeric material. 2. The contactless interconnect system of claim 1 wherein the interposer members are bonded to one of the terminal regions or circuit pads. The solid state interconnect system of claim 1 wherein the discrete interposer members define a gap therebetween, the interposer members being a material having a higher dielectric constant than the material filling the gap. A solid-state interconnect system between a computer chip package and a circuit board, A computer chip package having a bottom surface having a pattern of discrete terminal regions; A circuit board having a top surface parallel to and spaced apart from a bottom surface of the chip package, the circuit board comprising a pattern of discrete circuit pads aligned in the terminal region; A plurality of discontinuous interposer members supported by a carrier member disposed between the bottom surface of the chip package and the top surface of the circuit board, The carrier member extends in a width direction between the chip package lower surface and the circuit board upper surface, The interposer member is aligned with the terminal space and the circuit pad pattern and in a corresponding pattern, And the interposer member has a higher dielectric constant than the carrier member. 9. The contactless interconnect system of claim 8 wherein the terminal region is on a lower surface of a wall of a computer chip package, the terminal region being connected by vias to leads through the wall from the silicon wafer of the package. . 9. The contactless interconnect system of claim 8 wherein the interposer member is overmolded on a flat carrier member. 9. The contactless interconnect system of claim 8 wherein the flat carrier member is made of a dielectric elastomeric material. A solid-state interconnect system between a computer chip package and a circuit board, A computer chip disposed in a package, comprising: a computer chip having a plurality of leads extending to connect a circuit of the computer chip to another circuit; A support wall formed of a material having a given dielectric constant for supporting the chip and mounting the package on a circuit board, and a plurality of discontinuous conductive terminal regions disposed on an upper surface of the support wall and connected to the chip leads. With the package to say, And a circuit board comprising a substantially flat top surface disposed below the package support wall and having a pattern of discrete circuit pads arranged in a pattern in which a single circuit pad is arranged in a single terminal region of the package. Solid state interconnect system characterized by. 13. The contactless interconnect system of claim 12 wherein the support wall forms an outer wall of the package. 13. The contactless interconnect system of claim 12 wherein the support wall has a dielectric constant of at least 200. A solid-state interconnect system between a computer chip package and a circuit board, A computer chip comprising a housing having a flat inner surface and having an outer wall having a preselected dielectric material; A silicon wafer mounted in the housing, A pattern of discrete terminal regions of the inner surface of the wall electrically coupled to the silicon wafer, And a circuit board comprising a substantially flat surface lying parallel to the outside of the wall and having a pattern of discrete circuit pads aligned through the wall to the terminal area. 16. The contactless interconnect system of claim 15 wherein the wall is made of a material having a dielectric constant of at least 200.