CN1422440A - Contactless interconnection system - Google Patents
Contactless interconnection system Download PDFInfo
- Publication number
- CN1422440A CN1422440A CN01807908A CN01807908A CN1422440A CN 1422440 A CN1422440 A CN 1422440A CN 01807908 A CN01807908 A CN 01807908A CN 01807908 A CN01807908 A CN 01807908A CN 1422440 A CN1422440 A CN 1422440A
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- Prior art keywords
- interconnection system
- bonding land
- encapsulation
- circuit board
- terminal bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
- Combinations Of Printed Boards (AREA)
- Connecting Device With Holders (AREA)
Abstract
A contactless interconnecting system is provided between a computer chip package and a circuit board. The chip package has a substantially planar lower surface with a pattern of discrete terminal lands. The circuit board has a substantially planar upper surface spaced from and generally parallel to the lower surface of the chip package. A pattern of discrete circuit pads on the upper surface are aligned with the terminal lands. A plurality of discrete interposer members are disposed between the terminal lands and the circuit pads and are in a pattern corresponding to and aligned with the aligned patterns of the terminal lands and circuit pads. The interposer members are preferably of a material having a higher dielectric constant that of the material filling the gaps between interposer members.
Description
Background of invention
The interconnection that the present invention relates generally to not use contact and between computer chip encapsulation and circuit board, obtain.Along with semiconductor equipment becomes more complicated, because mechanically interconnected difficulty, the interconnection sustainable development between silicon wafer or " tube core " and the circuit hardware that matches also becomes more complicated.This part is because the miniaturization and the high density of electronic circuit.For frequency applications, the signal in the electronic unit transmits with fast speed, and semiconductor packages is just in attenuation and compacter.In some frequency applications, be difficult to use the conventional interconnect that relies on Metal Contact or terminal.
The traditional terminal lead of known mechanically interconnected use is connected with structure the moon or intermeshing spring with socket or other sun.Using the interconnection of these metals to metal, mainly is to provide erasing to do to pollute and oxidant in order to remove between terminal.In small-sized semiconductor interconnect, to such an extent as to terminal is to be difficult to provide necessary erasing and to obtain reliable contact force between relative terminal or contact so for a short time.Even possible words, traditional being welded to connect is very difficult, and this is because the small-sized or closely spaced parts of semiconductor interconnect system need use with the instrument of very complicated difficulty.
Therefore, the present invention relates to a kind of connector, it does not rely on Mechanical Contact, but uses the electric or magnetic field to be coupled transmission signals between two terminals or contact.
Summary of the invention
Therefore, general purpose of the present invention provides a kind of new and improved contactless interconnection system, and it is particularly suitable for providing connection between computer chip encapsulation and circuit board.
Another object of the present invention provides a kind of interconnection structure, and this structure does not use metal to provide connection to the contact of metal, and uses capacitive coupling between first and second array of terminals that insulating material is separated.
In one embodiment of the present of invention, provide the computer chip that is installed on planar support encapsulation.This support has a plurality of contact pads or circuit in the above, also provides lead or other to connect so that chip output is connected to contact pad.Contact pad is installed on the face of support, and then, this support is positioned on the circuit board, so that the contact pad that supports is also relative with it with relative contact pad or line aligning on the corresponding circuit board.Capacitive coupling is used for transmitting two signals between the relative contact pad.
In another embodiment, the computer chip encapsulation is installed on the planar support, and this support also has a plurality of contact pads, and they are supporting both sides one-tenth arranged in patterns.These contacts are interconnected each other by path (vias) and have a series of discontinuous terminals bonding land so that be encapsulated in its lower surface.Circuit board also has upper surface, has the pattern of the discontinuous capacitance pad of aiming at the terminal bonding land on the computer chip encapsulation lower surface on it.Between the terminal bonding land and the circuit pad on the circuit board of Chip Packaging, provide one or more discontinuous insulation to insert member.These insert members and are arranged in a pattern, and this pattern is corresponding to the pattern of terminal bonding land and circuit pad, and should insert member also with terminal bonding land and circuit pad alignment, and between terminal bonding land and circuit pad.Inserting construction material is a kind of material with quite high dielectric constant, and this dielectric constant is more preferably greater than 200.
Insert member and can adhere on terminal bonding land or the circuit pad, perhaps,, insert member and can support by the flat carrier that is configured between Chip Packaging lower surface and the circuit board upper surface as describing in another embodiment.This flat carrier can be by the tartan manufacturing of insulation, and should insert member can be by excessive molded in the flat carrier member.
From the detailed description of carrying out below in conjunction with accompanying drawing, other purposes of the present invention, feature, advantage will be clearly.
Brief Description Of Drawings
Believe that characteristics of the present invention are novel, in additional claim, can be stated especially.By understanding the present invention together with its purpose and advantage with reference to the detailed description of carrying out below in conjunction with accompanying drawing, in the accompanying drawings, the element of same Reference numeral TYP.Wherein,
Fig. 1 is the cutaway view that intercepts by an embodiment according to contactless interconnection system of the present invention;
Fig. 2 is that it shows second embodiment of the present invention by the cutaway view of computer chip encapsulation intercepting;
Fig. 3 is that it shows the 3rd embodiment of the present invention by the cutaway view of computer chip encapsulation intercepting.
DETAILED DESCRIPTION OF THE PREFERRED
Fig. 1 shows first embodiment of contactless interconnection system, and this system is general to represent that it illustrates with computer chip encapsulation 12 with 10, and provide computer chip encapsulate 12 with following substrate 14 (for example printed circuit board (PCB)) between be connected.Fig. 2 shows second embodiment of contactless interconnection system, and this system represents with 10A that generally it is also between Chip Packaging 12 and circuit board 14.
In two embodiment 10 and 10A, computer chip encapsulation 12 may comprise silicon wafer 16, and this silicon wafer is installed on the upper surface 18 of wall 20 of housing 22, and silicon wafer is configured in the housing 22.The pattern of terminal bonding land 24 discontinuous, conduction is deposited on the upper surface 18 of wall 20.Silicon wafer 16 is connected on these conductive land 24 by a plurality of leads 26.In this embodiment, terminal bonding land 24 is connected to via independent path separately 28 on the matched patterns of discontinuous conducting terminal bonding land or contact pad 30 by lower support wall 18, and contact pad 30 is configured on the lower surface 32 of supporting walls 18 of Chip Packaging 12.
The circuit board 14 of any one interconnection system 10 or 10A has flat substantially upper surface 34, and upper surface 34 is parallel to the lower surface 32 of Chip Packaging 12 and arranges.The pattern of discontinuous circuit pad 36 can be with following pattern arrangement on the upper surface 34: make each pad 36 be aligned in the independent terminal bonding land 30 on the lower surface of Chip Packaging supporting walls.Circuit pad 28 is electrically connected on the circuit board 14 circuit separately in the usual way.
A plurality of discontinuous insertion members 38 are in the terminal bonding land 30 on supporting walls 20 bottoms and be configured between top apparent surface's the circuit pad 36 of circuit board 14.By inserting gap 40,40 ' separates each other insertion member 38,38 ' among the embodiment respectively, as shown in Fig. 1 and Fig. 2, insert member 38,38 ' and separated by level, and have and both corresponding patterns of pattern of terminal bonding land 30 and circuit wafer 36, and generally aim at this pattern.Insert member preferably by the high dielectric constant materials manufacturing, in case cornerwise or contiguous terminal bonding land 30 and the coupling between the circuit wafer 36, wherein high-k is for the dielectric constant of the material in gap 40.The dielectric constant of insertion member 38,38 ' is the high order of magnitude of dielectric constant of the material of ratio gap 40,40 ' (normally air) at least, and the dielectric constant that inserts member 38,38 ' preferably is at least 200.Yet along with the increase of signal frequency, the numerical value that inserts the required dielectric constant of member may reduce.In these embodiments, preferably there is similar or same size the terminal bonding land with circuit board wafer 36 and aims at it, so that guarantee required pair of engaging district and the coupling between the pad, and guarantee do not have the bonding land of undesired angled vicinity and the coupling between the pad.
In Fig. 1, insert member 38 and support by support element 42, this support element 42 is the plane preferably, and is configured between the upper surface 34 of the lower surface 32 of Chip Packaging and circuit.This support element 42 (as shown in the figure) extends to the whole length and the width of computer chip encapsulation 12, and is preferably made by insulating material (for example plastics), is perhaps formed by insulation and flexible material (for example rubber or synthetic rubber).Insert member and can be molded into support element 42, and support element 42 can comprise a series of hole that is formed on wherein that these holes are adapted to excessive molding process by excessive.The dielectric constant that inserts member 38 cans be compared to the high order of magnitude of dielectric constant of support element 42 most, to prevent unwanted and non-selected diagonal coupling.
Fig. 2 shows second embodiment of contactless interconnection system 10A, and wherein, support element 42 used in first embodiment of Fig. 1 has been cancelled.In this embodiment, insert one side or the both sides that member 38 ' is adhered to terminal bonding land 30 and circuit wafer 36.For example, inserting member can be deposited to by suitable printing method on terminal bonding land 30 or the circuit pad 36.Yet, still between the insertion member, provide gap 40 '.And the dielectric constant that inserts member 38 ' should be than the high order of magnitude of any material (for example air) of filling gap 40 ' to prevent the diagonal coupling.
In two embodiment of interconnection system illustrated in figures 1 and 2 10 and 10A, inserting member 38,38 ' is discontinuous member, and as mentioned above, 40,40 ' locates to separate in the gap.Preferably, insert scantling measure-alike with terminal bonding land of aiming at 30 and circuit pad 36 basically.The signal of telecommunication capacitively 30 is transferred to circuit pad 36 by inserting member 38,38 ' from the terminal bonding land.The gap 40,40 ' of inserting between the member has than inserting the low dielectric constant of member, and they provide the insulation breakdown (break) between diagonal terminal bonding land 30 and the circuit pad 36.Because the signal of telecommunication preferably is coupled by high dielectric constant materials, then signal will trend towards not passing gap 40,40 ', and its intermediate gap 40,40 ' is between the insertion member of relative high dielectric constant material.Therefore, insertion member discontinuous or that separate has reduced the cross-couplings between terminal bonding land 30 and the circuit pad 36 diagonal groups widely and has crosstalked.
Should understand, the application of those terms, for example herein with claim in " on ", D score, " top ", " end ", " vertical " and similar term, it is in office that where face will be limited, such term only provides to clear and simple and clear narration and understanding of the present invention, just as seen in the accompanying drawings.Clearly, interconnection system 10 and 10A are omnibearing in using or using.
The 3rd embodiment of the present invention is shown in Figure 3, and wherein, contactless interconnection system 110 illustrates between computer chip encapsulation 112 and substrate 114 (for example circuit board).
Chip Packaging 112 comprises the silicon chip 118 on housing 115 with end supporting walls 116 and the flat substantially upper surface 120 that is installed in supporting walls 116.Supporting walls 116 supports discontinuous terminal bonding land 122 patterns, and terminal bonding land 122 is positioned on the upper surface 120 of wall 116, and is interconnected to silicon wafer 118 by lead 124 separately.The pattern of terminal bonding land 122 defines a plurality of gaps 123 therebetween.Supporting walls 116 in the present embodiment provides and the same function of function as the insertion member that uses among Fig. 1 and Fig. 2 embodiment.
The circuit board 114 of this system 110 is general become supporting walls 116 that parallel relation are configured in Chip Packaging 112 below.This circuit board 114 has flat upper surface 126, and this upper surface 126 has the pattern of the discontinuous capacitance pad of aiming at terminal bonding land 122 128.Be similar to the space that pattern limited 123 of discontinuous terminal bonding land 122, this pattern of discontinuous capacitance pad 128 also defines space 129 betwixt.Circuit pad 128 is electrically connected to the circuit separately on circuit board 114.
In the present invention: the supporting walls 116 of this computer chip encapsulation 112 directly is configured between the circuit pad 128 of the terminal bonding land 122 of Chip Packaging and circuit board 114.In this embodiment, the lower surface 121 of wall 116 is directly installed on the circuit pad 128.In another embodiment, this wall can be by the made of high-k (than the dielectric constant height that is filled in the material (being air) in gap 123 and the space 129), to prevent the cross-couplings between the terminals of adjacent bonding land 122 and to prevent cross-couplings between the adjacent circuit sheet 128.In another embodiment, this wall is by having the made that is at least 200 dielectric constant.Certainly, many materials or composite material can provide required like this dielectric constant, yet along with the increase of signal frequency, the numerical value of the required dielectric constant of wall 116 can reduce.In additional embodiment, width with respect to the space 129 between gap between the terminal bonding land 122 123 and the circuit pad 128, the thickness of wall 116 should be thinner, with the terminal bonding land of increase aiming at 122 and the coupling between the circuit pad 128, and prevent contiguous terminal bonding land 122 or the circuit pad 128 that is close between cross-couplings.
From as can be seen above, the part (being wall 116) of computer chip encapsulation is used to provide the electromagnetic coupled between silicon wafer 118 and the circuit board 114 effectively.In essence, wall 116 not only provides supporting construction but also provide the insertion dielectric in a plurality of capacitors, and wherein, the effect of half capacitor is provided respectively on the relative edge of the insertion dielectric that is provided by wall 116 for terminal bonding land 122 and circuit pad 128.Signal is the capacitive character transmission between the circuit pad 128 of the terminal bonding land 122 of Chip Packaging and circuit board 114.Therefore, every other additional interconnection parts are removed, and circuit board 114 can be installed to the basal surface of the supporting walls 116 of direct adjacent chips encapsulation with circuit pad 128 with interconnecting.
Should be appreciated that the present invention can use other forms to implement not breaking away under its spirit and the key property.Therefore, current for example and embodiment think in every respect to illustrate as an example and unrestricted, and the invention is not restricted to given details here.
Claims (16)
1. the contactless interconnection system between computer chip encapsulation and the circuit board, this contactless interconnection system comprises:
Have the computer chip encapsulation of flat lower surface, have discontinuous terminal bonding land pattern on this lower surface;
Circuit board with flat upper surface, the lower surface of this upper surface and Chip Packaging separate and almost parallel with it, and this circuit board comprises that the position thereon and aim at the discontinuous circuit welding disk pattern of described terminal bonding land; And
A plurality of discontinuous insertion member between terminal bonding land and circuit pad, it is corresponding with the pattern that is aligned with each other of circuit pad with the terminal bonding land and aim at it to insert the pattern of member.
2. the contactless interconnection system described in claim 1, wherein said terminal bonding land are positioned at the lower surface of the wall of computer chip encapsulation, and this terminal bonding land is connected to lead from the silicon wafer of encapsulation by wall by path.
3. the contactless interconnection system described in claim 1, wherein said insertion member is supported by the insulating carrier member between Chip Packaging lower surface and circuit board upper surface.
4. the contactless interconnection system described in claim 3, wherein said insertion member in support element by excessive molded.
5. the contactless interconnection system described in claim 3, wherein said flat carrier member is by the tartan manufacturing.
6. the contactless interconnection system described in claim 1, wherein said insertion member is adhered in described terminal bonding land or the circuit pad.
7. the contactless interconnection system described in claim 1, wherein said discontinuous insertion component limit they between the gap, the dielectric constant height of the material in the permittivity ratio filling gap of described insertion construction material.
8. the contactless interconnection system between computer chip encapsulation and the circuit board, this contactless interconnection system comprises:
Have the computer chip encapsulation of flat lower surface, have discontinuous terminal bonding land pattern on this lower surface;
Have upper surface and comprise the circuit board of the pattern of the discontinuous circuit pad of aiming at described terminal bonding land, wherein the lower surface of this upper surface and Chip Packaging separates and almost parallel with it; And
A plurality of discontinuous insertion members, they are supported by the support element between the upper surface of the lower surface of Chip Packaging and circuit board, the horizontal expansion between described Chip Packaging lower surface and described circuit board upper surface of this support element, this insertion member is arranged in a kind of pattern, this pattern is corresponding with the circuit welding disk pattern with described terminal bonding land and aim at it, and described insertion member has the dielectric constant higher than the dielectric constant of described support element.
9. the contactless interconnection system described in claim 8, wherein said terminal bonding land are positioned at the lower surface of the wall of computer chip encapsulation, and this terminal bonding land is connected to lead from the silicon wafer of encapsulation by wall by path.
10. the contactless interconnection system described in claim 8, wherein said insertion member in flat support element by excessive molded.
11. the contactless interconnection system described in claim 8, wherein said flat carrier member is by the manufacturing of insulation tartan.
12. the contactless interconnection system between computer chip encapsulation and the circuit board, this contactless interconnection system comprises:
Be arranged in the computer chip of encapsulation, this computer chip has the multiple conducting wires from its extension, is used for the circuit of described computer chip is connected to other circuit;
This encapsulation comprises supporting walls, be used for supporting chip and this encapsulation is installed to circuit board, this supporting walls is made of the material with given dielectric constant, and described encapsulation also comprises on the upper surface that is positioned at described supporting walls and is connected to a plurality of discontinuous conducting terminal bonding land of described chip lead; And
Be positioned at the circuit board below the described encapsulation supporting walls, this circuit board comprises flat basically upper surface, this upper surface has the pattern of the discontinuous circuit pad of configuration thereon, and its pattern is: independent circuit pad is aimed at placement with the independent terminal bonding land of described encapsulation.
13. the contactless interconnection system described in claim 12, wherein said supporting walls has constituted the outer wall of described encapsulation.
14. having, the contactless interconnection system described in claim 12, wherein said supporting walls be at least 200 dielectric constant.
15. the contactless interconnection system between computer chip encapsulation and the circuit board, this contactless interconnection system comprises:
The computer chip encapsulation, it comprises the housing with outer wall, this wall comprises flat inner surface, and this wall has predetermined dielectric material;
Be installed in the silicon wafer in the housing;
The pattern of discontinuous terminal bonding land, it is positioned at the inner surface of described wall and is electrically coupled to silicon wafer; And
Circuit board, it is with respect to the outer surface of described wall and put and comprise that flat basically surface, this surface have discontinuous circuit welding disk pattern, and this circuit pad is aimed at described terminal bonding land by this wall.
16. the contactless interconnection system described in claim 15, wherein said wall are at least 200 made by dielectric constant.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/548,940 US6612852B1 (en) | 2000-04-13 | 2000-04-13 | Contactless interconnection system |
| US09/548,636 US6362972B1 (en) | 2000-04-13 | 2000-04-13 | Contactless interconnection system |
| US09/548,940 | 2000-04-13 | ||
| US09/548,636 | 2000-04-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1422440A true CN1422440A (en) | 2003-06-04 |
| CN1237612C CN1237612C (en) | 2006-01-18 |
Family
ID=27068917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB018079083A Expired - Fee Related CN1237612C (en) | 2000-04-13 | 2001-04-12 | Contactless interconnection system |
Country Status (7)
| Country | Link |
|---|---|
| EP (1) | EP1273040A2 (en) |
| JP (1) | JP3701242B2 (en) |
| KR (1) | KR20020090233A (en) |
| CN (1) | CN1237612C (en) |
| AU (1) | AU2001251588A1 (en) |
| TW (1) | TW547773U (en) |
| WO (1) | WO2001080316A2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100336218C (en) * | 2003-08-25 | 2007-09-05 | 威盛电子股份有限公司 | High-frequency IC multi-bus knot tying structure and method |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2902002A1 (en) * | 1979-01-19 | 1980-07-31 | Gerhard Krause | Three=dimensional integrated circuits - mfd. by joining wafer stack with contacts through conductive adhesive |
| JPH0583011A (en) * | 1991-09-25 | 1993-04-02 | Sumitomo Electric Ind Ltd | Input/output coupling device for package for semiconductor device |
| US6728113B1 (en) * | 1993-06-24 | 2004-04-27 | Polychip, Inc. | Method and apparatus for non-conductively interconnecting integrated circuits |
| JPH0998005A (en) * | 1995-09-29 | 1997-04-08 | Nec Corp | Printed circuit board |
| US6396712B1 (en) * | 1998-02-12 | 2002-05-28 | Rose Research, L.L.C. | Method and apparatus for coupling circuit components |
-
2001
- 2001-04-12 TW TW090205708U patent/TW547773U/en not_active IP Right Cessation
- 2001-04-12 WO PCT/US2001/012020 patent/WO2001080316A2/en not_active Application Discontinuation
- 2001-04-12 CN CNB018079083A patent/CN1237612C/en not_active Expired - Fee Related
- 2001-04-12 EP EP01924985A patent/EP1273040A2/en not_active Withdrawn
- 2001-04-12 KR KR1020027013712A patent/KR20020090233A/en not_active Application Discontinuation
- 2001-04-12 AU AU2001251588A patent/AU2001251588A1/en not_active Abandoned
- 2001-04-12 JP JP2001577610A patent/JP3701242B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100336218C (en) * | 2003-08-25 | 2007-09-05 | 威盛电子股份有限公司 | High-frequency IC multi-bus knot tying structure and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1237612C (en) | 2006-01-18 |
| KR20020090233A (en) | 2002-11-30 |
| WO2001080316A3 (en) | 2002-03-21 |
| TW547773U (en) | 2003-08-11 |
| AU2001251588A1 (en) | 2001-10-30 |
| JP2003531496A (en) | 2003-10-21 |
| JP3701242B2 (en) | 2005-09-28 |
| EP1273040A2 (en) | 2003-01-08 |
| WO2001080316A2 (en) | 2001-10-25 |
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