經濟部智慧財產局貝工消费合作社印製 五、發明說明（） 之尺寸，且通常係以導線架製作，且護纣於塑楔外殼之中。 該封裝積體電路接著放置並錫銲於印刷電路板，以形成一 完整之電子系統。現行方法之優點包括成本低廉以及在後 續夾持時可供作保護之用。此外，該封裝爲用以測試積體 電路之標準化載體，如此’印刷電路板之設計變更可成本 低廉地以及快速地進行。組裝積體電路於印刷電路板可進 一步地自動化。最後，該電路系統允許印刷電路板之修改。 然而，當積體電路需要比傳統接線科技所可能達到之 更高性能及更大輸出/輸入腳端數目時，需要一種更有效率 之方法。該傳統之方法已限制電子性能及散熱之能力。該 封裝之電子寄生特性，傳導體之長度，由印刷電路板結構 所引發之電子寄生，以及用於印刷電路板之介電材料都限 制該方法之電子性能。這些限制更侷限系統之訊號數目於 數百以內，不論該積體電路或系統之複雜程度有多大。由 於現有之單積體電路連接比多重積體電路性能差，此限制 了整體系統之性能。 積體電路在100MHz以上作動。然而，現有連接積體 電路之方法限制係受限於操作於ΙΟΟΜΗζ以下之系統。一 用於連接積體電路之有效率裝置因此必須跟上積體電路進展之腳歩。 發明槪論 本發明提供一系統及方法，用以有效率地連接複數個 積體電路，其爲改進整體系統性能之所憑藉》 在本發明之系統之具體例中，對應複數積體電路之複 數載體，且一塊板具有許多板區域，用以承載許多數積體 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -I -I ----- I - D I UK n I ^n n i n )OJI n I ϊ n n I (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印氧 A7 B7___ 五、發明説明（丨） 相關申請案之對照參考資料 此申請爲美國臨時申請專利”用以封裝稹體電路之系 統及方法"之非臨時申請，美國序號60/028/,905，於1996 年十月二i--日入檔，擁有人爲Sammy K. Brown，George E. Avery，以及列名共同發明人之Andrew K. Wiggin，且 歸屬於Alpine Microsystem。由參照整篇60/028/,905之申 誚，此篇與其配合。 本發明之背景 本發明係關於半導體裝置之封裝，特別地關於一種連 接稹體電路（ICs>於半導體底材之系統及方法。 典型電子系統係由兩片以上之積體電路製造，以提供 完全之系統功能。直到最近，大部分之應用仍不致遭遇明 顯之性能及輸出/輸入腳端數目之限制。然而，隨漸增之裝 置倂入單晶片以及隨著脈街速度之增快，性能限制及输出/ 輸入腳端之數目將爲半導體製造者所關心之主要問題。此 係由於以多片積體電路爲基礎之電子系統之整體性能，爲 個別積體電路性能與積髋電路間傳送訊號之性能之函數。 積體電路間傳送訊號之性能亦爲訊號數目及該裝置之電子 特性之函數，其中該裝置用於連接積體電路與輸出/輸入腳 端。一種用於連接積體電路之更有效率之裝置因此成爲成 本、尺寸、性能、重量及電子系統之重要影響。 現今，用以連接積體電路之普遍方法爲首先封裝個之 別稹體電路，隨後裝置封裝好之稹髋電路於例如印刷電路 板之底材•封裝積髖電路之典型尺寸爲積體電路之數倍大 本紙張尺度逍用中國國家標準（CNS ) A4規格（210X297公釐） 裝 訂 線 (請先閲讀背面之注意事填寫本頁)Printed by the Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The size of the invention description () is usually made with a lead frame and is protected in a plastic wedge shell. The packaged integrated circuit is then placed and soldered to a printed circuit board to form a complete electronic system. The advantages of the current method include its low cost and its protection for subsequent clamping. In addition, the package is a standardized carrier for testing integrated circuits, so that the design changes of the printed circuit board can be performed inexpensively and quickly. Assembling integrated circuits on printed circuit boards can be further automated. Finally, the circuit system allows modification of printed circuit boards. However, when integrated circuits require higher performance and larger numbers of output / input pins than are possible with conventional wiring technology, a more efficient method is needed. This traditional approach has limited electronic performance and the ability to dissipate heat. The electronic parasitic characteristics of the package, the length of the conductor, the electronic parasitics induced by the printed circuit board structure, and the dielectric materials used for the printed circuit board all limit the electronic performance of the method. These restrictions limit the number of signals in the system to a few hundred, regardless of the complexity of the integrated circuit or system. Since the performance of the existing single integrated circuit is worse than that of the multiple integrated circuit, this limits the performance of the overall system. The integrated circuit operates above 100MHz. However, the limitations of existing methods for connecting integrated circuits are limited to systems operating below 100 MHz. An efficient device for connecting integrated circuits must therefore keep pace with the progress of integrated circuits. Disclosure of the Invention The present invention provides a system and method for efficiently connecting a plurality of integrated circuits, which is the basis for improving the performance of the overall system. In a specific example of the system of the present invention, the complex numbers corresponding to the complex integrated circuits are Carrier, and a board with many board areas to carry many digital products 4 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -I -I ----- I-DI UK n I ^ nnin) OJI n I ϊ nn I (please read the precautions on the back before filling this page) Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, printed oxygen A7 B7___ 5. Description of the invention (丨) Cross-reference for related applications Information This application is a non-provisional application for the US provisional patent "System and Method for Packaging Carcass Circuits", US Serial No. 60/028 /, 905, filed on October 2nd, 1996, the owner, Sammy K. Brown, George E. Avery, and Andrew K. Wiggin, co-inventor listed, and belonging to Alpine Microsystem. By referring to the entire application of 60/028 /, 905, this article cooperates with it. The present invention BACKGROUND The present invention relates to The packaging of conductor devices is particularly related to a system and method for connecting semiconductor circuits (ICs) to semiconductor substrates. Typical electronic systems are manufactured from two or more integrated circuits to provide complete system functions. Until recently, large Some applications still do not encounter obvious limitations on performance and the number of output / input pins. However, with the increasing number of devices integrated into a single chip and as the speed of pulses increases, the performance limits and the number of output / input pins It will be a major concern for semiconductor manufacturers. This is because the overall performance of electronic systems based on multi-chip integrated circuits is a function of the performance of individual integrated circuits and the performance of transmitting signals between integrated circuits. The performance of the transmitted signal is also a function of the number of signals and the electronic characteristics of the device, where the device is used to connect the integrated circuit with the output / input pins. A more efficient device used to connect the integrated circuit is therefore a cost , Size, performance, weight, and the significant impact of electronic systems. Today, the common method for connecting integrated circuits is to first package Different types of body circuits are then packaged. Hip circuits are packaged on a substrate such as a printed circuit board. The typical size of packaged hip circuits is several times larger than that of integrated circuits. The paper size is free of Chinese National Standards (CNS) A4. Specifications (210X297 mm) gutter (please read the notes on the back first and fill in this page)
A7 B7 經濟部智慧財產局員工消费合作社印製 五、發明說明（ 電路。每一載體具有第一及第二組接觸點，以及在其間之 一組許多連接點。當對應之積體電路裝置於載體表面，該 第一組接觸點連接於相對應積體電路之接觸點》每一板區 域具有一組板連接點’其分別連接載體之第二組接觸點’ 且該板具有一組板連接點，其選擇性地連接該組板接觸 點。當載體個別裝置於該板，該一連串之板區域更進一步 地形成一開口，其尺寸之配合埋藏個別載體之積體電路。 本發明方法之一具體例中，複數積體電路裝置於對應 之載體。每“蜀-應之載體具有足夠接觸點之表面，並且一 組載體上之接觸點藉固定之連接點通往積體電路之一組接 觸點。提供一具有開口之板，且該積體電路係以裝於板上 之載體配合裝入該板之開口。 這些以及其他本發明之具體例，其具有之優點及特色， 在下文及該附圖有詳細之描述。在該圖中，相似之參考號 碼代表相同或相似功能之元件。 簡要之圖說明 圖1.顯示根據本發明系統之用於有效率地連接積體電 路之不同元件拆解視圖； 圖2. 2A-2C分別顯示在該板上之積體電路/載體局部組 合上視圖，稹體電路/載體局部組合側視圖，以及裝置於板 上之積體電路載體局部組合側視圈： 圖3顯示載體上一組電子連接點之例子； 圖4 A-4B分別顯示裝置於一載體之單片積體電路，以 及裝置於一載體之多片稹體電路； 本紙張尺度適用t國國家標準（CNS>A4規格（210x297公釐） ---------------------訂*-------- (請先閱讀背面之注意事項再填寫本頁)A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (Circuit. Each carrier has a first and a second set of contact points, and a set of many connection points in between. When the corresponding integrated circuit device is installed in On the surface of the carrier, the first set of contact points is connected to the contact points of the corresponding integrated circuit. Each board area has a set of board connection points 'which respectively connect to the second set of contact points of the carrier', and the board has a set of board connections. Point, which selectively connects the contact points of the group of boards. When the carrier is individually mounted on the board, the series of board areas further forms an opening whose size matches the buried integrated circuit of the individual carrier. One of the methods of the present invention In the specific example, the plural integrated circuit is installed on the corresponding carrier. Each "Shu-Ying carrier has a surface with sufficient contact points, and the contact points on a group of carriers lead to a group of integrated circuit contacts through fixed connection points. Point. A board having an opening is provided, and the integrated circuit is fitted into the opening of the board with a carrier mounted on the board. These and other specific examples of the present invention have Advantages and features are described in detail below and in the accompanying drawings. In the figure, similar reference numbers represent elements with the same or similar functions. Brief illustration of the figure 1. Shows the system according to the invention for efficient use Disassembly view of different components connected to the integrated circuit; Figure 2. 2A-2C shows the top view of the integrated circuit / carrier partial combination on the board, the side view of the integrated circuit / carrier partial combination, and the device mounted on the board Integrated side view circle of integrated circuit carrier: Figure 3 shows an example of a group of electronic connection points on the carrier; Figure 4 A-4B shows a single-chip integrated circuit mounted on a carrier, and multiple chips mounted on a carrier 载体Body circuit; This paper size applies to national standards (CNS > A4 size (210x297 mm)) --------------------- Order * ------ -(Please read the notes on the back before filling this page)
經濟部智慧財產局貝工消费合作社印製 五、發明說明（） 之尺寸，且通常係以導線架製作，且護纣於塑楔外殼之中。 該封裝積體電路接著放置並錫銲於印刷電路板，以形成一 完整之電子系統。現行方法之優點包括成本低廉以及在後 續夾持時可供作保護之用。此外，該封裝爲用以測試積體 電路之標準化載體，如此’印刷電路板之設計變更可成本 低廉地以及快速地進行。組裝積體電路於印刷電路板可進 一步地自動化。最後，該電路系統允許印刷電路板之修改。 然而，當積體電路需要比傳統接線科技所可能達到之 更高性能及更大輸出/輸入腳端數目時，需要一種更有效率 之方法。該傳統之方法已限制電子性能及散熱之能力。該 封裝之電子寄生特性，傳導體之長度，由印刷電路板結構 所引發之電子寄生，以及用於印刷電路板之介電材料都限 制該方法之電子性能。這些限制更侷限系統之訊號數目於 數百以內，不論該積體電路或系統之複雜程度有多大。由 於現有之單積體電路連接比多重積體電路性能差，此限制 了整體系統之性能。 積體電路在100MHz以上作動。然而，現有連接積體 電路之方法限制係受限於操作於ΙΟΟΜΗζ以下之系統。一 用於連接積體電路之有效率裝置因此必須跟上積體電路進展之腳歩。 發明槪論 本發明提供一系統及方法，用以有效率地連接複數個 積體電路，其爲改進整體系統性能之所憑藉》 在本發明之系統之具體例中，對應複數積體電路之複 數載體，且一塊板具有許多板區域，用以承載許多數積體 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -I -I ----- I - D I UK n I ^n n i n )OJI n I ϊ n n I (請先閱讀背面之注意事項再填寫本頁) B7__ 五、發明說明（） {清先閱璜背面之注意事項再填寫本頁) 晶體132及134分別地連接至電源平面120及接地平面 122。此預防載體區域112之短路令整個載體晶圓112a短 路。在切割階段670期間，如圖6所示，測試電路區域130， 以及電源平面120與接地平面122，如圖8所示，分成兩 部分。此令載體晶圓llh之切割不損及個別載體區域112。 在步驟672進行不良連接之測試，通過測試，該組裝於步 驟674完成，如圖6所示。 經濟部智慧財產局貝工消费合作社印製 參考圖9，已知該載體212之連接線與晶片之連接點 相當，載體.2*12〃可有許多不同電路，爲可能裝置其士之積 體電路21(Τ操作所必需。在生產積體電路時，此提供較大 之彈性度，可降低每單位之價格。例如，考慮一位於典型 積體電路上之裝置品質，該最小特徵尺寸爲0.25微米等 級。然而，與積體電路有關之裝置並無須調整爲具有0.25 微米等級之最小特徵尺寸。輸入/輸出緩衝器214爲其中一 例。藉載體212,該輸入/輸出緩衝器214可在其中成形， 且仍然以低成本爲積體電路提供相同之功能。該輸入/輸出 緩衝器可建構成使其具有遠大於積體電路之特徴尺寸。藉 避免電路調整到微小尺寸之不必要，節省了相對積體電路 210之製造成本。更適切地說，這些電路，在此以輸入/輸 出緩衝器爲例，可製成較大之特徵尺寸，例如1微米之等 級》以相似之方式，可爲幫助伴隨之積體電路310作動之 載體312提供其他裝置，例如圖10所示之時脈配電網路 314,如圖11所示之具有溫度感側器414之電力配電網路， 以及如圖12所示之RLC電路514* 13 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐)Printed by the Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The size of the invention description () is usually made with a lead frame and is protected in a plastic wedge shell. The packaged integrated circuit is then placed and soldered to a printed circuit board to form a complete electronic system. The advantages of the current method include its low cost and its protection for subsequent clamping. In addition, the package is a standardized carrier for testing integrated circuits, so that the design changes of the printed circuit board can be performed inexpensively and quickly. Assembling integrated circuits on printed circuit boards can be further automated. Finally, the circuit system allows modification of printed circuit boards. However, when integrated circuits require higher performance and larger numbers of output / input pins than are possible with conventional wiring technology, a more efficient method is needed. This traditional approach has limited electronic performance and the ability to dissipate heat. The electronic parasitic characteristics of the package, the length of the conductor, the electronic parasitics induced by the printed circuit board structure, and the dielectric materials used for the printed circuit board all limit the electronic performance of the method. These restrictions limit the number of signals in the system to a few hundred, regardless of the complexity of the integrated circuit or system. Since the performance of the existing single integrated circuit is worse than that of the multiple integrated circuit, this limits the performance of the overall system. The integrated circuit operates above 100MHz. However, the limitations of existing methods for connecting integrated circuits are limited to systems operating below 100 MHz. An efficient device for connecting integrated circuits must therefore keep pace with the progress of integrated circuits. Disclosure of the Invention The present invention provides a system and method for efficiently connecting a plurality of integrated circuit, which is the basis for improving the performance of the overall system. Carrier, and a board with many board areas to carry many digital products 4 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -I -I ----- I-DI UK n I ^ nnin) OJI n I ϊ nn I (Please read the precautions on the back before filling out this page) B7__ V. Description of the invention () {Please read the precautions on the back before filling out this page) Crystals 132 and 134 respectively The ground is connected to the power plane 120 and the ground plane 122. This short circuit in the carrier region 112 prevents the entire carrier wafer 112a from being short-circuited. During the cutting phase 670, as shown in FIG. 6, the test circuit area 130, and the power plane 120 and the ground plane 122, as shown in FIG. 8, are divided into two parts. This allows the dicing of the carrier wafer 11h not to damage the individual carrier regions 112. A bad connection test is performed in step 672. After the test, the assembly is completed in step 674, as shown in FIG. Printed with reference to Figure 9 by the Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. It is known that the connection line of the carrier 212 is equivalent to the connection point of the chip. The carrier .2 * 12〃 can have many different circuits, which is the product of a possible installation Circuit 21 (Required for T operation. This provides greater flexibility when producing integrated circuits, which can reduce the price per unit. For example, consider the quality of a device located on a typical integrated circuit. The minimum feature size is 0.25 Micron level. However, devices related to integrated circuits do not need to be adjusted to have a minimum feature size of 0.25 micron level. The input / output buffer 214 is one example. With the carrier 212, the input / output buffer 214 can be formed therein And still provide the same function for integrated circuits at low cost. The input / output buffer can be constructed to have a special size much larger than integrated circuits. By avoiding unnecessary adjustment of the circuit to a small size, it saves relative The manufacturing cost of the integrated circuit 210. More appropriately, these circuits, taking the input / output buffer as an example, can be made to a larger feature size, such as 1 In a similar way, the "meter level" can provide other devices for the carrier 312 that assists the accompanying integrated circuit 310, such as the clock distribution network 314 shown in FIG. 10, and the temperature sensor shown in FIG. The power distribution network of 414, and the RLC circuit shown in Figure 12 514 * 13 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)
A7 B7 經濟部智慧財產局員工消费合作社印製 五、發明說明（ 電路。每一載體具有第一及第二組接觸點，以及在其間之 一組許多連接點。當對應之積體電路裝置於載體表面，該 第一組接觸點連接於相對應積體電路之接觸點》每一板區 域具有一組板連接點’其分別連接載體之第二組接觸點’ 且該板具有一組板連接點，其選擇性地連接該組板接觸 點。當載體個別裝置於該板，該一連串之板區域更進一步 地形成一開口，其尺寸之配合埋藏個別載體之積體電路。 本發明方法之一具體例中，複數積體電路裝置於對應 之載體。每“蜀-應之載體具有足夠接觸點之表面，並且一 組載體上之接觸點藉固定之連接點通往積體電路之一組接 觸點。提供一具有開口之板，且該積體電路係以裝於板上 之載體配合裝入該板之開口。 這些以及其他本發明之具體例，其具有之優點及特色， 在下文及該附圖有詳細之描述。在該圖中，相似之參考號 碼代表相同或相似功能之元件。 簡要之圖說明 圖1.顯示根據本發明系統之用於有效率地連接積體電 路之不同元件拆解視圖； 圖2. 2A-2C分別顯示在該板上之積體電路/載體局部組 合上視圖，稹體電路/載體局部組合側視圖，以及裝置於板 上之積體電路載體局部組合側視圈： 圖3顯示載體上一組電子連接點之例子； 圖4 A-4B分別顯示裝置於一載體之單片積體電路，以 及裝置於一載體之多片稹體電路； 本紙張尺度適用t國國家標準（CNS>A4規格（210x297公釐） ---------------------訂*-------- (請先閱讀背面之注意事項再填寫本頁) 經 濟 部 中 央 標 準 局 工 消 費 合 作 社 印 % ' , , ΙΛ.. ：·!.. A7 B7_____ 五、發明説明（f ) 圖5顯示根撺本發明有效率地連接積體電路之方法之 步驟： 圖6顯示根據本發明之另一連接積儺電路之方法之步 驟； 圖7顯示根據本發明之載髋晶圓之簡化平面視圃； 圖8爲圖7中根據本發明之載體晶圓之詳細平面視圖： 圖9爲顯示於圖2A-2C中之載體之示意®，其根據第 一替代具體例； 圖10爲顯示於圖2A-2C中之載體之示意圖，其根據第 二替代具體例： 圖11爲顯示於圖2A-2C中之載體之示意圖，其根據第 三替代具體例： 圖12爲顯示於圖2A-2C中之載體之示意圖，其根據第 四替代具體例； 圖13爲根據本發明，裝置於底材之積體電路-載體-板 局部組合示意圖，其裝置顯示於圖2 A-2C ;以及 圖14爲根據本發明，依另一具體例，裝置於底材之積 體電路-載體-板局部組合示意圖。 較佳具體例之描述 本發明提供用有效率地連接積體電路之一系統及一方 法，以形成一具有改良之整體系統性能之複合電子元件》 圖1顯示一裝置於載體12及具開口之板14之積體電 路10之拆解視圖。如圖所示，板14具有4 ,開口 16， 然而，開口數目可根據欲安裝於板14之載體數目而改變· 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） I — I « 訂 P (請先閱讀背面之注意事項.缜寫本頁) A 7 B7 經濟部中央橾準局另工消费合作社印製 五、發明説明（f) 相似地，雖然開口 16在顯示上尺寸相同，在另一例子中 它們可以有相異之尺寸•而與欲於板14電氣連接之稹體 電路尺寸所決定之開口尺寸相同》在圖1所顯示之例子中， 載體12只連接於稹體笔路10。然而，如隨後之討論，載 體12可連接一片以上之稹體電路或其他電子元件。若載 體12只連接一積體電路，用於該系統之載體數目將視複 合稹體電路中之積體電路數目而定。在一較佳具體例中， 載體之尺寸對應複合稹體電路之積體電路之尺寸•且板之 尺寸對應複合積體電路之尺寸。 載體12以與板14及積體電路10之熱變形相容較佳， 此係由於載體12連接稹體電路10及板14·對於積體電 路10，載體12，及板14間之熱膨脹係數之要求可藉利用 複合材料而達到•例如連接積體電路及封裝之導線。同樣 地，黏合之材料可用以限制應力大小。然而較佳之方式爲 載體12及板14用相似於積體電路10之熱膨脹係數（CTE) 之材料製作。在較佳具體例中，載體12及板14以同積體 電路之材料製作。由於典型積體電路由單晶矽製作，其有 相對之低CTE*故矽爲載體12及板14較佳之材料。然而， 鎵砷化合物或其他具有相同CTE之材料亦可使用。 圖1亦顯示板I4上之連接方式。板14係利用半導體 微影製程製作；因此板14上互連之集線密度比傅統之水 平連接還高。載體12之連接點22預先製作，配合板14 上之連接點24之搭接襯墊型態。因此板14至少兼具機 械基座，以及在相鄰載體與稹體電路之間之穿過連接線20 7 (請先閱讀背面之注意事項4填寫私頁) -s 丁 % 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 經濟部中央標準局貝工消費合作社印製 A 7 B7 五、發明説明（L) 之單一層線路之功用。在板14中以無導通孔較佳，因爲 該積體電路連接點，藉由允許在稹體電路問傅輸之訊號通 過相鄰之積體電路，可以比較理想地分布於載體之間》由 於所有局部系統之線路較理想地横越載體分配*板上線路 之複雜度得以降低到單一網路組之程度•與一單連接點板 比較，載體間之連接點分配大幅地簡化連接之工作，而且 明顯地改善整體性能表現。雖然板14以僅具有一層連接 點較佳•在生產量不困難之應用下•板14可具有多層連 接點。在此種應用中，在板14中可能有導通孔*因爲該 連接點14將包括穿越線及交叉跨越。 圖2 A-2C分別顯示一板14中之積體電路/載體局部組 合25上視圖，一積體電路載體局部組合之側面視圖，以 及在板14之積體電路/載體局部組合之側視圖。如圖2B 所示，局部組合25,其包含裝置於載體12之積體電路10’ 以錫鉛突塊（如連接點21及22)預製，其中錫鉛突塊突塊 擺置成陣列，其對準以反映積體電路1〇及板14之搭接襯 墊。積體電路1〇係經由連接點21以倒裝片接合之方式 裝置於載體12。如圖2C所示，每一局部組合25裝置於 板14，使得積體電路10將配合開口 16內》如圖所示，載 體12圍繞開口 16延伸且經由連接點22連接於板I4。典 型地積體電路1〇與載體12間之接點數目將不等於載體I2 與板14間之連接點22之數目。 開口 16之利用使得訊號接線全部排在稹體電路1〇頂 部面•載體12頂部面•及板14頂部面所形成平面之內* 8 lifti本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） (請先閱讀背面之注意事項J填寫本頁) -'6 % 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（7 ) 配置具有許多儍點，此係因矽之化學性質在寅際上不 適於形成導通孔，鍍膜超過數個十分之一微米以上厚度· 藉由利用與載體12及板14之相同材料，可於載體12及 板14之間直接錫銲接合。由於稹體電路1〇及載體12以 相同材料製作較佳•訊號接線亦可直接銲於載體並連接該 積體電路。如前面所討論，在載體12上之錫鉛突塊對準 以反映出積體電路10之搭接襯墊》因此•槙體電路10無 需錫給突塊。 使用錫鉛突塊於連接積體電路於載體，及連接載體至 板’其優點爲一面稹陣列可用於最大可能外部訊號接點之 數量•此外，由於打線所引發之寄生可以消除•錫鉛突塊 倒裝片接合爲一自動化之製程，且積體電路之成本不隨腳 端數目增加而增加。因此，錫鉛突塊亦可用於組合較高之 輸出/輸入接腳而保持成本低廉。 圖3顯示一電子連接於載體12之範例。爲簡化起見， 顯示相對較小之連接點•如圔所示，載體12具有連接點 22,其沿著周圍分布，以及連接點21，其包圍中心部分地 分布。連接點21及22分別連接稹體電路10於載體12， 及連接載體12至板14»連接點21可用固定接線通往連接 點22，且如此線路具有至少一交叉跨越。這些交叉跨越允 許訊號在載體12上傅入或傅出積體電路。此外，載體12 上之訊號路徑可與積體電路訊號線獨立。這些獨立訊號線 提供由鄰近槙體電路傳送訊號至另一稹體電路之功用》在 此措施下*稹體電路之連接點橫越個別載體地分布· 9 本紙张尺度適用中國國家標準（CNS ) A4規格（210X297公釐） — I I II |种衣 II 訂 I I务 (請先閱讀背面之注意事項填寫本頁) 五、發明説明（客） 連接點21及22根據特殊後合稹體電路之應用而預先 決定。由於連接點21及22係利用半導體微影技術製造， 其最後線路密度與晶片接線之接點密度非常接近。積體電 路間之接點數目，亦即外部接線•一般需要比用於連接稹 體電路上電晶體之接線密度明顯還低之接線密度•如此， 該外部接線密度可一直保持足夠之水準，其使用與製造積 體電路本身之相同或較低先進之半導體製程*利用相同之 技術*該外部接線可製作配合放入與積體電路本身面稹相 同或較小之區域。此提供比現行方法更明顯之產量優點， 當印刷電路板尺寸及面稹比稹體電路本身大許多倍時。 載體12係由多層半導體金屬化製程所製作。訊號線間 之交叉跨越藉利用經由使用位於相同層之導通孔而達成》 由於所有導通孔在相同層上，連接點21及22之訂製變更· 可因此令在單一阻膜之製作在製造層次上樊得較爲簡單。 對於每一新應用，導通孔之位置可根據所需之特積體電路 接線而決定。一旦積體電路位置決定，只有含導通孔之層 需要改變。 圖4A顯示一裝®於載體12之單片稹體電路10。如圖 4B所示，多重積體電路晶片亦可裝置於載體12»雖然圖 4A及4B只顯示載體12上之積體電路，而電晶髋，電容 器，以及其他電子元件亦可隨積體電路裝置於載體12上。 如此，載體12本身具有多晶片模組之功能《此優點甚多， 因爲在板I4上可連接更多元件。再者，以載體12爲中繼 媒介之板，連接線可與晶片上接線相容· 本紙張尺度適用中國國家標準（CNS ) A4規格（210><297公釐} 經 濟 部 中 央 標 準 局 貝 工 消 費 合 作 社 _ A7 _B7__ 五、發明説明（，） 圖5爲顯示根據本發明連接積髋電路之較佳方法之流 程圖。如圖所示*對於每片複合稹體電路，板晶圓•載體 晶圓，以及積體電路晶圇分開製作。考慮步驟501，板晶 圓製作完成後，在步驟503板上開口成形》個別基板在步 驟505分離，且在步驟507進行測試，載體在步驟521製 作，且在步驟523測試並分類缺陷》缺陷之單元丟棄，且 在步驟525將好的單冗分離成個別載體。考慮步騍541至 步驟5W，積雅電路亦在製作出來後測試缺陷*好的單元 亦由缺陷單元分類出來並分離成個別積體電路。在步踝 5 50,好的積體電路已裝置於載體上，在步驟55 5完成最 後之積體電路測試•此與其他積體電路次系統組合之額外 步驟消除”已知良好之晶片”之顧慮。由於無須顧慮小晶片 品質，組合產出之減損可以因而消除。該積體電路/載體局 部組合在步驟570裝置於板上。不良之連接測試在步騍572 進行，通過測試後，組裝在步驟574完成〃 參考圖6及圖7,顯示根據本發明關於連接積體電路 之另一替代方法。特別地，步驟601，603，605及607對 應步驟501，503 · 505及507 .如同圖5之討論。然而， 圖6顯示之方法，其不同處在載體切割前，個別積體電路 110裝置於載體之上。特別地，載體晶圓112a在步騍621 製作，使其在載體區域112間有許多分隔區》在一分割製 程裡，積體電路110在步驟641製作，此後•積體電路110 在步驟645切割並在步騍641裝置於載體晶圓112a上， 其係利用上述之銲接技術·以此方式，每一載髋區域於是 V ,本紙張尺度適用中國國家梯準（CNS ) A4規格（210 X 297公釐） (请先閲讀背面之注意事項.彳壤寫本頁) 装.A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (Circuit. Each carrier has a first and a second set of contact points, and a set of many connection points in between. When the corresponding integrated circuit device is installed in On the surface of the carrier, the first set of contact points is connected to the contact points of the corresponding integrated circuit. Each board area has a set of board connection points 'which respectively connect to the second set of contact points of the carrier', and the board has a set of board connections. Point, which selectively connects the contact points of the group of boards. When the carrier is individually mounted on the board, the series of board areas further forms an opening whose size matches the buried integrated circuit of the individual carrier. One of the methods of the present invention In the specific example, the plural integrated circuit is installed on the corresponding carrier. Each "Shu-Ying carrier has a surface with sufficient contact points, and the contact points on a group of carriers lead to a group of integrated circuit contacts through fixed connection points. Point. A board having an opening is provided, and the integrated circuit is fitted into the opening of the board with a carrier mounted on the board. These and other specific examples of the present invention have Advantages and features are described in detail below and in the accompanying drawings. In the figure, similar reference numbers represent elements with the same or similar functions. Brief illustration of the figure 1. Shows the system according to the invention for efficient use Disassembly view of different components connected to the integrated circuit; Figure 2. 2A-2C shows the top view of the integrated circuit / carrier partial combination on the board, the side view of the integrated circuit / carrier partial combination, and the device mounted on the board Integrated side view circle of integrated circuit carrier: Figure 3 shows an example of a group of electronic connection points on the carrier; Figure 4 A-4B shows a single-chip integrated circuit mounted on a carrier, and multiple chips mounted on a carrier 载体Body circuit; This paper size applies to national standards (CNS > A4 size (210x297 mm)) --------------------- Order * ------ -(Please read the notes on the back before filling out this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Industrial and Consumer Cooperatives,% ',, ΙΛ ..: ·! .. A7 B7_____ 5. Explanation of the Invention (f) Figure 5 shows the root cause The steps of the method for efficiently connecting integrated circuits of the present invention: FIG. 6 shows FIG. 7 shows a simplified plan view of a hip-bearing wafer according to the present invention; FIG. 8 is a detailed plan view of the carrier wafer according to the present invention in FIG. 7: FIG. 9 is Schematic representation of the carrier shown in Figs. 2A-2C®, according to the first alternative specific example; Fig. 10 is a schematic diagram of the carrier shown in Figs. 2A-2C, according to the second alternative specific example: Fig. 11 is shown in the figure The schematic diagram of the carrier in 2A-2C, according to the third alternative specific example: Fig. 12 is a schematic diagram of the carrier shown in Fig. 2A-2C, according to the fourth alternative specific example; Fig. 13 is a device according to the present invention, which is installed at the bottom Schematic diagram of the partial combination circuit of the material-carrier-board, whose device is shown in Figs. 2A-2C; and Fig. 14 is a partial view of the integrated circuit-carrier-board of the substrate according to the present invention according to another specific example Combination diagram. Description of the preferred embodiment The present invention provides a system and a method for efficiently connecting integrated circuits to form a composite electronic component with improved overall system performance. FIG. 1 shows a device on a carrier 12 and an opening with a Disassembled view of the integrated circuit 10 of the board 14. As shown in the figure, the board 14 has 4, openings 16, however, the number of openings can be changed according to the number of carriers to be mounted on the board 14. This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) I — I «Order P (please read the notes on the back first. Please write this page) A 7 B7 Printed by the Central Consumers' Bureau of the Ministry of Economic Affairs and printed by a separate consumer cooperative. V. Description of the invention (f) Similarly, although the opening 16 is the size of the display Same, in another example, they can have different sizes • and the same opening size determined by the size of the body circuit to be electrically connected to the board 14 "In the example shown in Figure 1, the carrier 12 is only connected to the Body Pen Road 10. However, as discussed later, the carrier 12 may be connected to more than one body circuit or other electronic components. If the carrier 12 is connected to only one integrated circuit, the number of carriers used in the system will depend on the number of integrated circuits in the complex integrated circuit. In a preferred embodiment, the size of the carrier corresponds to the size of the integrated circuit of the composite circuit, and the size of the board corresponds to the size of the integrated circuit. The carrier 12 is preferably compatible with the thermal deformation of the board 14 and the integrated circuit 10, because the carrier 12 is connected to the body circuit 10 and the board 14. For the integrated circuit 10, the thermal expansion coefficient of the carrier 12, and the board 14 Requirements can be achieved through the use of composite materials such as wires for integrated circuits and packages. Similarly, bonded materials can be used to limit the amount of stress. However, the preferred method is that the carrier 12 and the board 14 are made of a material similar to the coefficient of thermal expansion (CTE) of the integrated circuit 10. In a preferred embodiment, the carrier 12 and the board 14 are made of a material of an integrated circuit. Since a typical integrated circuit is made of monocrystalline silicon, which has a relatively low CTE *, silicon is a preferred material for the carrier 12 and the board 14. However, gallium arsenic compounds or other materials with the same CTE can also be used. Figure 1 also shows the connection on the board I4. Board 14 is manufactured using a semiconductor lithography process; therefore, the density of the interconnects on board 14 is higher than the horizontal connection of Fu Tong. The connection points 22 of the carrier 12 are made in advance, and the overlapping pads of the connection points 24 on the board 14 are matched. Therefore, the board 14 has at least both a mechanical base and a connecting wire 20 7 between the adjacent carrier and the body circuit (please read the notes on the back first and fill in the private page) -s ding% This paper size is applicable to China National Standard (CNS) A4 Specification (210X297mm) Printed by the Central Standards Bureau of the Ministry of Economy, Shellfish Consumer Cooperative, A 7 B7 V. Function of Single Layer Circuit of Invention Description (L). It is better to have no via holes in the board 14, because the integrated circuit connection points can be ideally distributed between the carriers by allowing signals from the integrated circuit to pass through adjacent integrated circuits. All local system lines are ideally distributed across the carrier. The complexity of the on-board circuits is reduced to a single network group. Compared with a single connection point board, the connection point allocation between carriers greatly simplifies the connection work, and Significantly improve overall performance. Although it is better for the board 14 to have only one layer of connection points. • In applications where throughput is not difficult, the board 14 may have multiple layers of connection points. In such applications, there may be vias * in the board 14 because the connection point 14 will include crossing lines and crossovers. 2A-2C show a top view of the integrated circuit / carrier partial combination 25 in a board 14, a side view of a partial circuit carrier partial combination, and a side view of the integrated circuit / carrier partial combination on the board 14, respectively. As shown in FIG. 2B, the partial combination 25 includes a built-in circuit 10 'mounted on the carrier 12 and prefabricated with tin-lead bumps (such as the connection points 21 and 22). The tin-lead bump bumps are arranged in an array. Align to reflect the bonding pads of integrated circuit 10 and board 14. The integrated circuit 10 is mounted on the carrier 12 in a flip-chip bonding manner via a connection point 21. As shown in FIG. 2C, each partial combination 25 is mounted on the board 14, so that the integrated circuit 10 will fit into the opening 16. As shown in the figure, the carrier 12 extends around the opening 16 and is connected to the board I4 via the connection point 22. The number of contacts between the typical ground integrated circuit 10 and the carrier 12 will not be equal to the number of connection points 22 between the carrier I2 and the board 14. The use of the opening 16 allows all signal wiring to be arranged within the plane formed by the top surface of the body circuit 10, the top surface of the carrier 12, and the top surface of the board 14 * 8 lifti (Mm) (Please read the note on the back J to complete this page first) -'6% Printed by A7 B7, Shellfish Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs 5. Description of the invention (7) The configuration has many silly points, this is due to silicon The chemical properties are not suitable for the formation of vias. The thickness of the coating is more than a few tenths of a micrometer. By using the same material as the carrier 12 and the board 14, it can be directly soldered between the carrier 12 and the board 14. Together. Since the body circuit 10 and the carrier 12 are preferably made of the same material, the signal wiring can also be directly soldered to the carrier and connected to the integrated circuit. As previously discussed, the tin-lead bumps on the carrier 12 are aligned to reflect the lap pads of the integrated circuit 10. Therefore, the bulk circuit 10 does not require tin to the bumps. The use of tin-lead bumps to connect the integrated circuit to the carrier, and to connect the carrier to the board 'has the advantage of one side. The array can be used for the largest possible number of external signal contacts. In addition, parasitics caused by wire bonding can be eliminated. The flip chip bonding is an automated process, and the cost of the integrated circuit does not increase with the number of pins. Therefore, tin-lead bumps can also be used to combine higher output / input pins while keeping costs low. FIG. 3 shows an example of an electronic connection to the carrier 12. For the sake of simplicity, relatively small connection points are shown. As shown by 圔, the carrier 12 has connection points 22 that are distributed along the periphery, and connection points 21 that are partially distributed around the center. The connection points 21 and 22 respectively connect the body circuit 10 to the carrier 12 and the connection carrier 12 to the board 14. The connection point 21 can be connected to the connection point 22 by fixed wiring, and thus the line has at least one crossover. These crossings allow signals to be fused into or out of the integrated circuit on the carrier 12. In addition, the signal path on the carrier 12 can be independent of the integrated circuit signal line. These independent signal lines provide the function of transmitting signals from adjacent carcass circuits to another carcass. "Under this measure, the connection points of carcass circuits are distributed across individual carriers. 9 This paper standard applies to Chinese National Standards (CNS) A4 specification (210X297 mm) — II II | Seed coat II Order II service (please read the precautions on the back to fill out this page) V. Invention description (customer) Connection points 21 and 22 are based on the application of special post-combination circuit And predetermined. Since the connection points 21 and 22 are manufactured using semiconductor lithography technology, the final circuit density is very close to the contact density of the chip wiring. The number of contacts between integrated circuits, that is, external wiring. Generally, a wiring density that is significantly lower than the wiring density used to connect the transistors on the body circuit is generally required. Use the same or lower advanced semiconductor manufacturing process as the integrated circuit itself * Use the same technology * The external wiring can be made to fit into the same or smaller area as the integrated circuit itself. This provides a more significant yield advantage over current methods, when the printed circuit board size and area are many times larger than the bulk circuit itself. The carrier 12 is made by a multilayer semiconductor metallization process. The crossover between signal lines is achieved by using vias on the same layer. As all vias are on the same layer, the customization of connection points 21 and 22 can be changed. Therefore, the production of a single barrier film can be made at the manufacturing level. Shangfan is relatively simple. For each new application, the location of the vias can be determined based on the wiring required for the special integrated circuit. Once the integrated circuit location is determined, only the layer containing the vias needs to be changed. FIG. 4A shows a monolithic body circuit 10 mounted on a carrier 12. As shown in FIG. 4B, a multiple integrated circuit chip can also be mounted on the carrier 12. Although FIGS. 4A and 4B only show the integrated circuit on the carrier 12, but the hip, capacitor, and other electronic components can also be integrated with the integrated circuit. It is mounted on the carrier 12. In this way, the carrier 12 itself has the function of a multi-chip module. This has many advantages, because more components can be connected to the board I4. Furthermore, the board with carrier 12 as the relay medium can be compatible with the wiring on the chip. This paper size applies the Chinese National Standard (CNS) A4 specification (210 > < 297 mm). Industrial and consumer cooperatives _ A7 _B7__ V. Description of the invention (,) Figure 5 is a flow chart showing a preferred method of connecting hip-hop circuits according to the present invention. As shown in the figure * For each composite carcass circuit, board wafer • carrier The wafer and the integrated circuit wafer are separately produced. Consider step 501, after the wafer fabrication is completed, the opening is formed in step 503. The individual substrates are separated in step 505, and the test is performed in step 507. The carrier is produced in step 521. , And test the defect in step 523 and classify the defective unit discarded, and separate the good single redundancy into individual carriers in step 525. Consider step 541 to step 5W, Jieya circuit also tests the defect after making it * good The unit is also classified by the defective unit and separated into individual integrated circuits. At step ankle 5 50, a good integrated circuit has been installed on the carrier, and the final integrated circuit test is completed at step 55 5 This additional step in combination with other integrated circuit sub-systems eliminates the concerns of "known good wafers". Because there is no need to worry about small chip quality, the impairment of the combined output can be eliminated. The integrated circuit / carrier partial combination is in step 570 The device is on the board. The bad connection test is performed in step 572. After passing the test, the assembly is completed in step 574. Referring to FIGS. 6 and 7, another alternative method for connecting integrated circuits according to the present invention is shown. In particular, Steps 601, 603, 605, and 607 correspond to steps 501, 503, 505, and 507. As discussed in Figure 5. However, the method shown in Figure 6 differs in that the individual integrated circuit 110 is mounted on the carrier before the carrier is cut. In particular, the carrier wafer 112a is produced in step 621 so that there are many partitions between the carrier regions 112. In a split process, the integrated circuit 110 is produced in step 641, and thereafter the integrated circuit 110 is produced in step 645. It is cut and mounted on the carrier wafer 112a in step 641, which uses the welding technique described above. In this way, each hip-bearing area is then V. This paper size is applicable to the Chinese national standard. CNS) A4 size (210 X 297 mm) (Please read the back of the note. Write soil left foot of this page) installed.
、1T 中 央 標 準 局 貝 工 消 费 合 作 社 A7 B7 _ 五、發明説明（丨〇 ) 將至少具有一積體電路110» 參考圖3、6及7,在切割載體12前連接稹體電路110· 使得在最後組裝前，達到100%之功能測試以及積體電路 110之老化試驗。最後，載體晶圓U2包括一電源平面120 及接地平面122,以及訊號線124。每一載體區域112可 經由接線126連接到電源平面120及接地平面122。在此 配置中，於步驟6 55中，稹體電路110,伴隨載髋112, 可於完全組裝並輸送給終端使用者之前進行測試•特別 地*該訊號線124,該電源平面120及接地平面122係與 必要之連接點21接通，以幫助柵極偏壓及信號輸送至積 體電路110。如此，提早缺陷積體電路110之偵測可藉降 低由所缺陷造成之相關成本而達到。該載體區域112及棟 體電路110可在切割後以及在裝置入板114之前丟棄，此 係節省安置發揮適當功能之板14之成本所憑藉。此外， 所降低爲積體電路110於功能測試時將造成損害之可能 性，此係由於傳輸至110之測試訊號及偏壓發生於連接墊 片124a及126a。在老化試驗期間稹體電路110與測試儀 器（未顯示）間並無實質之接觸。 參考圖7及圖8,信號線124及連接線126藉由穿越 測試電路區域130,其位於相鄰之載體區域112之間，通 往每一載體區域112。同樣包括在內地，測試電路區域130 亦爲適當地配置位於載體之積體電路之另一必備電路元 件，以供作功能測試。例如，獨立之電晶體132及134可 安置其中•以此方式·每一積懺電路110可經由獨立之電 1..本紙張尺度適用中國國家標準（CNS) A4規格（ 210X297公釐） I I I I I I |辦农I I 訂I 矣 (锖先閱讀背面之注意事項4填寫本頁) B7__ 五、發明說明（） {清先閱璜背面之注意事項再填寫本頁) 晶體132及134分別地連接至電源平面120及接地平面 122。此預防載體區域112之短路令整個載體晶圓112a短 路。在切割階段670期間，如圖6所示，測試電路區域130， 以及電源平面120與接地平面122，如圖8所示，分成兩 部分。此令載體晶圓llh之切割不損及個別載體區域112。 在步驟672進行不良連接之測試，通過測試，該組裝於步 驟674完成，如圖6所示。 經濟部智慧財產局貝工消费合作社印製 參考圖9，已知該載體212之連接線與晶片之連接點 相當，載體.2*12〃可有許多不同電路，爲可能裝置其士之積 體電路21(Τ操作所必需。在生產積體電路時，此提供較大 之彈性度，可降低每單位之價格。例如，考慮一位於典型 積體電路上之裝置品質，該最小特徵尺寸爲0.25微米等 級。然而，與積體電路有關之裝置並無須調整爲具有0.25 微米等級之最小特徵尺寸。輸入/輸出緩衝器214爲其中一 例。藉載體212,該輸入/輸出緩衝器214可在其中成形， 且仍然以低成本爲積體電路提供相同之功能。該輸入/輸出 緩衝器可建構成使其具有遠大於積體電路之特徴尺寸。藉 避免電路調整到微小尺寸之不必要，節省了相對積體電路 210之製造成本。更適切地說，這些電路，在此以輸入/輸 出緩衝器爲例，可製成較大之特徵尺寸，例如1微米之等 級》以相似之方式，可爲幫助伴隨之積體電路310作動之 載體312提供其他裝置，例如圖10所示之時脈配電網路 314,如圖11所示之具有溫度感側器414之電力配電網路， 以及如圖12所示之RLC電路514* 13 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) A7 __B7 五、發明説明（丨> ) 參考圖I3,顯示該稹體電路710具有鑲嵌用表面710a 及在反側之主表面710b。該鑲嵌用表面710a用前面所述 之錫鉛突塊7 20連接載體712之鑲嵌用表面712a。該板714 包含一鑲嵌用表面714a及在反側之主表面714b，載雔712 用前面所述之錫鉛突塊722鑲嵌於銀嵌用表面714a，使得 積體電路 710安裝於孔穴716之內。較佳地，選擇錫鉛 突塊 720及722，使得主表面710b與主表面714b共面。 以此方式，一散熱基座 725可鑲嵌於稹體電路710之主 表面710b及板714之主表面714b。如散熱之功用外，該 散熱基座爲板714及稹體電路710提供機械支撐。此組合 可進一步地鑲嵌於一封裝底材，例如以錫鉛突塊鑲嵌於一 印刷電路板726，其載體712安裝於板714及印刷電路板 726之間。 或者，如圖14所示，該局部組合之方向可轉換，使得 積體電路810及板814安置於載體812及印刷電路板826 之間。以此方式，該板814之主表面814b連接印刷電路 板826。使用如線S30所示之打線技術，可達成電氣連接 印刷電路板826及板S14之錶嵌用表面810。 I I n I n 訂 I 务 (請先閱讀背面之注意事項/%寫本頁) 經濟部中央標準局貝工消費合作社印装 本紙張尺度適用中國國家梯準.(CNS ) A4規格（210x297公釐）1T Central Standards Bureau Shellfish Consumer Cooperative A7 B7 _ 5. Description of the invention (丨 〇) will have at least one integrated circuit 110 »Referring to Figures 3, 6 and 7, connect the body circuit 110 before cutting the carrier 12 so that Before final assembly, 100% functional test and aging test of integrated circuit 110 are achieved. Finally, the carrier wafer U2 includes a power plane 120 and a ground plane 122, and a signal line 124. Each carrier region 112 may be connected to a power plane 120 and a ground plane 122 via a wiring 126. In this configuration, in step 6 55, the corpus callosum 110, with the hip-bearing 112, can be tested before it is fully assembled and delivered to the end user. Specifically * the signal line 124, the power plane 120, and the ground plane 122 is connected to the necessary connection point 21 to help the gate bias and signal to the integrated circuit 110. In this way, early detection of the defect integrated circuit 110 can be achieved by reducing the related costs caused by the defects. The carrier area 112 and the building circuit 110 can be discarded after being cut and before the device is placed into the board 114, which saves the cost of placing the board 14 for proper functions. In addition, the reduction is the possibility that the integrated circuit 110 will cause damage during the functional test. This is because the test signals and bias voltages transmitted to 110 occur at the connection pads 124a and 126a. There was no substantial contact between the carcass circuit 110 and a tester (not shown) during the aging test. Referring to FIG. 7 and FIG. 8, the signal line 124 and the connection line 126 pass through the test circuit area 130 and are located between adjacent carrier areas 112 to each carrier area 112. Also included in the Mainland, the test circuit area 130 is also another necessary circuit component of the integrated circuit located on the carrier for proper function testing. For example, independent transistors 132 and 134 can be placed in this way. • In this way, each integrated circuit 110 can be passed through an independent power supply. 1. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) IIIIII | Farming II Order I 矣 (锖 Please read the notes on the back 4 to fill in this page) B7__ V. Description of the invention () {Please read the notes on the back of the book before filling in this page) Crystals 132 and 134 are connected to the power plane respectively 120 和 GND 平面 122. This short circuit in the carrier region 112 prevents the entire carrier wafer 112a from being short-circuited. During the cutting phase 670, as shown in FIG. 6, the test circuit area 130, and the power plane 120 and the ground plane 122, as shown in FIG. 8, are divided into two parts. This allows the dicing of the carrier wafer 11h not to damage the individual carrier regions 112. A bad connection test is performed in step 672. After the test, the assembly is completed in step 674, as shown in FIG. Printed with reference to Figure 9 by the Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. It is known that the connection line of the carrier 212 is equivalent to the connection point of the chip. The carrier .2 * 12〃 can have many different circuits, which is a product that can be installed. Circuit 21 (Required for T operation. This provides greater flexibility when producing integrated circuits, which can reduce the price per unit. For example, consider the quality of a device located on a typical integrated circuit. The minimum feature size is 0.25 Micron level. However, devices related to integrated circuits do not need to be adjusted to have a minimum feature size of 0.25 micron level. The input / output buffer 214 is one example. With the carrier 212, the input / output buffer 214 can be formed therein And still provide the same function for integrated circuits at low cost. The input / output buffer can be constructed to have a special size much larger than integrated circuits. By avoiding unnecessary adjustment of the circuit to a small size, it saves relative The manufacturing cost of the integrated circuit 210. More appropriately, these circuits, taking the input / output buffer as an example, can be made to a larger feature size, such as 1 In a similar way, the "meter level" can provide other devices for the carrier 312 that assists the accompanying integrated circuit 310, such as the clock distribution network 314 shown in FIG. 10, and the temperature sensor shown in FIG. The power distribution network of 414 and the RLC circuit 514 * as shown in Figure 12 13 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) A7 __B7 V. Description of the invention (丨 >) Reference Figure I3 shows that the body circuit 710 has a mounting surface 710a and a main surface 710b on the opposite side. The mounting surface 710a is connected to the mounting surface 712a of the carrier 712 by the tin-lead bump 7 20 described above. The board 714 includes a mounting surface 714a and a main surface 714b on the opposite side. The carrier 712 is mounted on the silver mounting surface 714a with the tin-lead bump 722 described above, so that the integrated circuit 710 is installed in the hole 716. Preferably, the tin-lead bumps 720 and 722 are selected so that the main surface 710b is coplanar with the main surface 714b. In this way, a heat sink base 725 can be embedded in the main surface 710b of the body circuit 710 and the main surface 714b of the board 714 .In addition to the function of heat dissipation, the heat dissipation base is a board 714 and body circuit 710 provide mechanical support. This combination can be further embedded in a packaging substrate, such as tin-lead bumps in a printed circuit board 726, and its carrier 712 is mounted between the board 714 and the printed circuit board 726 Or, as shown in FIG. 14, the direction of the partial combination can be switched, so that the integrated circuit 810 and the board 814 are disposed between the carrier 812 and the printed circuit board 826. In this way, the main surface 814b of the board 814 is connected to the printing Circuit board 826. Using the wire bonding technology as shown by line S30, it is possible to achieve a surface 810 for electrically connecting the printed circuit board 826 and the board S14. II n I n Order I service (please read the notes on the back /% write this page) The printed paper size of the Central Standards Bureau of the Ministry of Economic Affairs Shellfish Consumer Cooperatives is applicable to the Chinese national standard. (CNS) A4 size (210x297 mm) )