FR2782841B1 - Procede permettant de former des plots de contact et, en meme temps, de rendre plane une surface de substrat dans des circuits integres - Google Patents

Procede permettant de former des plots de contact et, en meme temps, de rendre plane une surface de substrat dans des circuits integres

Info

Publication number
FR2782841B1
FR2782841B1 FR9905762A FR9905762A FR2782841B1 FR 2782841 B1 FR2782841 B1 FR 2782841B1 FR 9905762 A FR9905762 A FR 9905762A FR 9905762 A FR9905762 A FR 9905762A FR 2782841 B1 FR2782841 B1 FR 2782841B1
Authority
FR
France
Prior art keywords
plane
substrate
same time
integrated circuits
contact plates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9905762A
Other languages
English (en)
Other versions
FR2782841A1 (fr
Inventor
Un Yoon Bo
Ji Hong Seok
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of FR2782841A1 publication Critical patent/FR2782841A1/fr
Application granted granted Critical
Publication of FR2782841B1 publication Critical patent/FR2782841B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
FR9905762A 1998-05-07 1999-05-06 Procede permettant de former des plots de contact et, en meme temps, de rendre plane une surface de substrat dans des circuits integres Expired - Fee Related FR2782841B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980016333A KR100268459B1 (ko) 1998-05-07 1998-05-07 반도체 장치의 콘택 플러그 형성 방법

Publications (2)

Publication Number Publication Date
FR2782841A1 FR2782841A1 (fr) 2000-03-03
FR2782841B1 true FR2782841B1 (fr) 2003-08-29

Family

ID=19537111

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9905762A Expired - Fee Related FR2782841B1 (fr) 1998-05-07 1999-05-06 Procede permettant de former des plots de contact et, en meme temps, de rendre plane une surface de substrat dans des circuits integres

Country Status (9)

Country Link
US (1) US6218291B1 (fr)
JP (1) JP4031148B2 (fr)
KR (1) KR100268459B1 (fr)
CN (1) CN1114942C (fr)
DE (1) DE19920970C2 (fr)
FR (1) FR2782841B1 (fr)
GB (1) GB2337161B (fr)
NL (1) NL1011933C2 (fr)
TW (1) TW444373B (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100474537B1 (ko) * 2002-07-16 2005-03-10 주식회사 하이닉스반도체 산화막용 ｃｍｐ 슬러리 조성물 및 이를 이용한 반도체소자의 제조 방법
US6818555B2 (en) * 2002-10-07 2004-11-16 Taiwan Semiconductor Manufacturing Co., Ltd Method for metal etchback with self aligned etching mask
JP4679277B2 (ja) * 2005-07-11 2011-04-27 富士通セミコンダクター株式会社 半導体装置の製造方法
US7964502B2 (en) 2008-11-25 2011-06-21 Freescale Semiconductor, Inc. Multilayered through via
US9716035B2 (en) * 2014-06-20 2017-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Combination interconnect structure and methods of forming same
CN105336676B (zh) * 2014-07-29 2018-07-10 中芯国际集成电路制造(上海)有限公司 接触插塞的形成方法
WO2018031926A1 (fr) * 2016-08-11 2018-02-15 Tokyo Electron Limited Procédé de planarisation à base de gravure d'un substrat

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4676867A (en) * 1986-06-06 1987-06-30 Rockwell International Corporation Planarization process for double metal MOS using spin-on glass as a sacrificial layer
JPH01108746A (ja) * 1987-10-21 1989-04-26 Toshiba Corp 半導体装置の製造方法
US4879257A (en) * 1987-11-18 1989-11-07 Lsi Logic Corporation Planarization process
DE69034137D1 (de) * 1990-10-01 2004-06-03 St Microelectronics Srl Herstellung von Kontaktanschlüssen bei der alles überdeckenden CVD-Abscheidung und Rückätzen
US5143867A (en) * 1991-02-13 1992-09-01 International Business Machines Corporation Method for depositing interconnection metallurgy using low temperature alloy processes
JP3216104B2 (ja) * 1991-05-29 2001-10-09 ソニー株式会社 メタルプラグ形成方法及び配線形成方法
JPH05190684A (ja) * 1992-01-16 1993-07-30 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5618381A (en) * 1992-01-24 1997-04-08 Micron Technology, Inc. Multiple step method of chemical-mechanical polishing which minimizes dishing
JP2756887B2 (ja) * 1992-03-02 1998-05-25 三菱電機株式会社 半導体装置の導電層接続構造およびその製造方法
US5250472A (en) * 1992-09-03 1993-10-05 Industrial Technology Research Institute Spin-on-glass integration planarization having siloxane partial etchback and silicate processes
US5312512A (en) * 1992-10-23 1994-05-17 Ncr Corporation Global planarization using SOG and CMP
US5268330A (en) * 1992-12-11 1993-12-07 International Business Machines Corporation Process for improving sheet resistance of an integrated circuit device gate
US5328553A (en) * 1993-02-02 1994-07-12 Motorola Inc. Method for fabricating a semiconductor device having a planar surface
JP3326698B2 (ja) * 1993-03-19 2002-09-24 富士通株式会社 集積回路装置の製造方法
US5356513A (en) * 1993-04-22 1994-10-18 International Business Machines Corporation Polishstop planarization method and structure
JPH07106419A (ja) * 1993-10-05 1995-04-21 Toshiba Corp 半導体装置の製造方法
US5496774A (en) * 1993-12-01 1996-03-05 Vlsi Technology, Inc. Method improving integrated circuit planarization during etchback
US5545581A (en) * 1994-12-06 1996-08-13 International Business Machines Corporation Plug strap process utilizing selective nitride and oxide etches
US5786273A (en) * 1995-02-15 1998-07-28 Matsushita Electric Industrial Co., Ltd. Semiconductor device and associated fabrication method
JP2638546B2 (ja) * 1995-02-28 1997-08-06 日本電気株式会社 半導体装置の製造方法
US5527736A (en) * 1995-04-03 1996-06-18 Taiwan Semiconductor Manufacturing Co. Dimple-free tungsten etching back process
US5747383A (en) * 1995-09-05 1998-05-05 Taiwan Semiconductor Manufacturing Company Ltd Method for forming conductive lines and stacked vias
US5665657A (en) * 1995-09-18 1997-09-09 Taiwan Semiconductor Manufacturing Company, Ltd Spin-on-glass partial etchback planarization process
US5847464A (en) * 1995-09-27 1998-12-08 Sgs-Thomson Microelectronics, Inc. Method for forming controlled voids in interlevel dielectric
US5861342A (en) * 1995-12-26 1999-01-19 Vlsi Technology, Inc. Optimized structures for dummy fill mask design
US5830804A (en) * 1996-06-28 1998-11-03 Cypress Semiconductor Corp. Encapsulated dielectric and method of fabrication
US6025269A (en) * 1996-10-15 2000-02-15 Micron Technology, Inc. Method for depositioning a substantially void-free aluminum film over a refractory metal nitride layer
KR100243272B1 (ko) * 1996-12-20 2000-03-02 윤종용 반도체 소자의 콘택 플러그 형성방법
KR100266749B1 (ko) * 1997-06-11 2000-09-15 윤종용 반도체 장치의 콘택 플러그 형성 방법
US5961617A (en) * 1997-08-18 1999-10-05 Vadem System and technique for reducing power consumed by a data transfer operations during periods of update inactivity

Also Published As

Publication number Publication date
DE19920970A1 (de) 1999-11-18
NL1011933C2 (nl) 2002-09-24
GB2337161B (en) 2000-11-08
CN1235373A (zh) 1999-11-17
KR19990084516A (ko) 1999-12-06
US6218291B1 (en) 2001-04-17
JP4031148B2 (ja) 2008-01-09
GB9909486D0 (en) 1999-06-23
NL1011933A1 (nl) 1999-11-09
CN1114942C (zh) 2003-07-16
DE19920970C2 (de) 2002-10-24
GB2337161A (en) 1999-11-10
JP2000003915A (ja) 2000-01-07
TW444373B (en) 2001-07-01
KR100268459B1 (ko) 2000-10-16
FR2782841A1 (fr) 2000-03-03

Similar Documents

Publication Publication Date Title
IT1299859B1 (it) Unita' elettro-ottica di rilevamento dell'intera superficie lateale di articoli di forma sostanzialmente cilindrica.
NO20025684L (no) Substrat med en redusert lysspredende ultrafobisk overflate og fremgangsmåte for fremstilling av denne
FR2766617B1 (fr) Dispositif a semiconducteurs ayant plusieurs types de transistors formes dans une puce et procede pour sa fabrication
FR2727241B1 (fr) Procede pour former des entretoises destinees notamment a des visuels a grande surface
FR2756663B1 (fr) Procede de traitement d'un substrat semi-conducteur comprenant une etape de traitement de surface
DE69529858D1 (de) Oberflächenbehandlung für Halbleitersubstrat
DE59914532D1 (de) Verfahren zum nasschemischen pyramidalen Texturätzen von Siliziumoberflächen
FR2761912B1 (fr) Procede destine a faire adherer un produit sur une surface
FR2797140B1 (fr) Procede de fabrication de connexions traversantes dans un substrat et substrat equipe de telles connexions
FR2809867B1 (fr) Substrat fragilise et procede de fabrication d'un tel substrat
FR2822167B1 (fr) Procede de metallisation d'une piece substrat
FR2835095B1 (fr) Procede de preparation d'ensembles a semi-conducteurs separables, notamment pour former des substrats pour l'electronique, l'optoelectrique et l'optique
FR2837620B1 (fr) Procede de transfert d'elements de substrat a substrat
DE60042993D1 (de) Verfahren zum thermischen Behandeln eines Substrates
FR2851259B1 (fr) Procede de fabrication de monocristaux hexagonaux et leur utilisation comme substrat pour des composants semi-conducteurs.
FR2782841B1 (fr) Procede permettant de former des plots de contact et, en meme temps, de rendre plane une surface de substrat dans des circuits integres
DE19839710B4 (de) Vorrichtung zum verspannenden Verbinden von zwei in Abstand befindlichen Bauteilen
FR2704689B1 (fr) Procede de formation de motif fin dans un dispositif a semi-conducteur.
DE10234710B8 (de) System zum Trocknen von Halbleitersubstraten
FR2797523B1 (fr) Procede d'inspection d'un substrat semiconducteur
DE69917826D1 (de) Keramisches Substrat und dessen Polierverfahren
DE59901572D1 (de) Vorrichtung zum herstellen und bearbeiten von halbleitersubstraten
DE59805067D1 (de) Verfahren zum Ätzen von Halbleiterscheiben
DE59700260D1 (de) Vorrichtung zum Halten eines flachen Substrats
EP0962964A4 (fr) Detergent destine aux procedes permettant de produire des dispositifs a semi-conducteur ou a cristaux liquides

Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20100129