CN1114942C - 在集成电路中形成接触销且同时平面化衬底表面的方法 - Google Patents
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Abstract
一种用于在集成电路中形成接触销且同时平面化衬底表面的方法,首先,在其中具有多个扩散区的半导体衬底上形成导电结构。在包括导电结构的半导体衬底上形成第一绝缘层。用接触孔形成掩模腐蚀第一绝缘层以形成接触孔。在第一绝缘层上形成导电层,用导电层填满接触孔。腐蚀该导电层直到露出第一绝缘层的上表面为止。在第一绝缘层上形成第二绝缘层。可以形成没有空隙的接触销,同时通过平面化腐蚀第二和第一绝缘层来平面化衬底表面。
Description
本发明涉及半导体器件的制造。特别是,本发明涉及用于在集成电路中形成接触销且同时平面化衬底表面的新方法。
随着集成电路器件变得更复杂化,就需要更大量的互连级以连接器件的各个部分。一般接触通孔形成在互连级之间以使一级连接到另一级。但按这种方式使用多层互连时,很难形成上层互连级和接触通孔,这是由于由下层互连级引起的不平坦地形特征造成的。因此互连级的地形会影响制造集成电路器件的容易程度。
多层互连级的不平坦地形特征是由在彼此上方形成各种互连层引起的,结果在器件表面产生凸凹不平处。本领域技术人员应该认识到,当上互连层在不平坦构形上穿过时很难保持其横截面不变。这导致具有较高电流密度的互连线部分有电迁移问题并引起相关器件失效机理。这些台阶覆盖问题可能引起互连信号线本身中以及在互连线之间所形成的接触通孔中存在空隙和其它缺陷。
作为互连信号线中的其它缺陷的例子,其中可能产生的是开路或短路问题。就是说,由多层结构中的各个互连层引起的严重不平坦地形导致上述在其上所形成的另一互连层的开路或短路。
互连信号线中的其它缺陷的另一例子是使用用于形成接触销的常规方法,按该方法,必须在底层区域(或半导体衬底)上生长或淀积很厚层的绝缘材料以形成接触销。根据该常规方法,接触销是用化学机械抛光(CMP)工艺形成的,该工艺是在淀积导电层以填满穿过很厚的绝缘层形成的接触孔或通孔之后即刻进行的。考虑到用于形成接触销的CMP工艺,绝缘层必须形成得很厚。当穿过很厚的绝缘层形成接触孔或通孔时,其高宽比增加了。这产生两个缺陷:第一,在很厚的绝缘层上淀积导电层以填满接触孔或通孔时可能产生空隙。第二,由于绝缘层很厚而使CMP处理时间加长。
因此,希望提供用于形成接触通孔的方法而没有空隙和其它缺陷,并且得到更平坦的地形。还希望这种方法不会显著地增加制造工艺的复杂性。
因此本发明的目的是提供用于形成集成电路中的接触销的方法,而不会产生由台阶覆盖问题引起的缺陷。
本发明的另一目的是提供能够获得更加平坦地形的接触销形成方法。
本发明的又一目的是提供可以减小穿过绝缘层所形成的接触孔或通孔的高宽比的接触销形成方法。
因此,根据本发明,提供用于在集成电路中形成接触销的方法。首先,在其中具有多个扩散区的半导体衬底上形成导电结构。在包括导电结构的半导体衬底上形成第一绝缘层。第一绝缘层在成组地形成导电结构的第一区域具有比在未形成导电结构的第二区域高的台阶。用构图的光刻胶掩模作为开口形成掩模对第一绝缘层进行腐蚀以形成接触孔。在第一绝缘层上形成导电层,填满接触孔。腐蚀该导电层,直到露出第一绝缘层的上表面为止。在第一绝缘层上形成第二绝缘层。形成接触销,同时通过平面化-腐蚀第二和第一绝缘层而平面化衬底表面,留下第二区域中的一部分第二绝缘层。在形成导电层之前,还可以在第一绝缘层、接触孔的侧壁和底部上形成阻挡层。而且在形成导电结构之前,还可以在导电结构和半导体衬底之间形成氧化物层。
通过下面参照附图的说明使本发明更容易被理解,而且其目的对于本领域技术人员来说也更明显,其中:
图1A-1D是根据本发明的第一实施例以截面表示在集成电路中形成接触销且同时平面化衬底表面的新方法的流程图;和
图2A-2D是根据本发明的第二实施例表示在集成电路中形成接触销同时平面化衬底表面的新方法的流程图。
下面介绍的工艺步骤和结构没有构成制造集成电路的完整的工艺流程。本发明可以结合目前本领域中使用的集成电路制造技术来实施,并包括了这些通常实施的工艺步骤而用于解释本发明。表示制造过程中的集成电路的部分横截面的附图中不是按比例画出的,而只是用于表示本发明的主要特征。
现在参照图1A-1D介绍第一优选实施例,其中在制造过程中形成接触销,以使中间夹着层间绝缘层的两导电层电连接,同时使衬底表面平面化。现在具体地参照图1A,在集成电路中通过接触孔108在底层区域100上形成一般由多晶硅构成的导电层110。底层区域100可是半导体衬底或互连信号线。在通过半导体衬底100上的接触孔108填充导电层的情况下,该衬底可具有器件隔离区102,如图1A所示,以确定其上的有源区和无源区。器件隔离区102例如是用浅槽隔离(STI)方法形成的。在具有生长或淀积其间的栅氧化物层(未示出)的衬底100上形成可用做半导体存储器件的字线的栅极104。例如存储器件的源和漏区的扩散区也可以位于栅极104两侧的有源区内,只是未示出。在包括栅极104的衬底100上淀积适当厚度的第一绝缘层106,从而可以减少化学机械抛光(CMP)处理时间。这里,本实施例的两个最主要的特征之一是绝缘层106可以具有适合于后来进行的CMP工艺的厚度,以形成接触销。在淀积中,考虑到后来用于形成接触销的CMP工艺,不必使第一绝缘层106形成得非常厚。这是因为第一绝缘层106没有在其形成之后即刻被平面化-腐蚀以形成接触销。接触销用于电连接多层结构中、或扩散区和互连线的每个中的顶层互连线和底层互连线。绝缘层106一般可以由氧化硅(SiO2)构成,但可替换的是,也可以是采用化学汽相淀积法(CVD)、回流法、淀积/腐蚀和高密度等离子体法(HDP)等方法中的一种制成的以下一组材料中的一种它们选自:未掺杂的硅酸盐玻璃(USG)、硼磷硅玻璃(BPSG)、磷硅玻璃(PSG)、SiN、SiON、SiOF、或它们的复合材料。绝缘层106还可以使用旋涂方法由选自SOG、可流动的氧化物(FOX)、聚合物或其混合材料中的一种构成。
再参照图1A,然后在绝缘层106上淀积光刻胶掩模(未示出)并构图,用构图的光刻胶掩模做开口形成掩模而进行腐蚀工艺,由此在要形成接触销的地方形成通过绝缘层106的接触孔108。在绝缘层106上淀积一般由多晶硅构成的导电层110,以填满接触孔108。代替多晶硅,导电层110可以使用CVD、物理汽相淀积(PVD)、回流或压力填充方法由钨(W)、铝(Al)、铜(Cu)、钛(Ti)、TiN、W-Si、Al-Cu和Al-Cu-Si中的一种材料形成。在本例中,导电多晶硅层将作为例子在后面介绍。
图1B表示在进行深腐蚀工艺以形成多晶硅接触销之后的集成电路。干法或湿法深腐蚀导电多晶硅层110,直到完全露出绝缘层106的上表面为止,由此形成多晶硅接触销110a。在这里,如现有技术所述,形成栅极的区域‘A’相对于未形成栅极的区域‘B’具有高度(即粗糙表面)。这导致衬底表面的不平坦地形,即在衬底表面产生凸凹不平。特别是,由于区域‘B’的绝缘层106比区域‘A’的薄,所以在区域‘A’和‘B’之间产生更严重的不平坦地形。根据本例,为了除去衬底表面的不平坦地形,必须在第一绝缘层106上进行绝缘层的淀积和平面化,如图1C和1D所示。
或者,导电多晶硅层110可以被过腐蚀。如此形成的多晶硅接触销110a相对于第一绝缘层106下凹。可以进行用于平面化的CMP工艺。
参照图1C,在第一绝缘层106上,包括多晶硅接触销110a淀积第二绝缘层112。第二绝缘层112最好由与第一绝缘层106或后来在其上所形成的层间绝缘层的相同材料制成。
最后,如图1D所示,进行现有技术中公知的CMP工艺,直到露出多晶硅接触销110a的上表面为止,由此部分第二绝缘层112保留在凹处所在的区域‘B’中。CMP工艺使用浆料作为抛光材料,其具有导电多晶硅层110相对于绝缘层106和112的腐蚀选择性,最好在1∶10和10∶1之间。接触销110a在CMP工艺中用作腐蚀停止层。这里,另一重要特征是,在不平坦衬底表面的凹处被第二绝缘层112填满之后,进行CMP工艺以形成接触销110a。
结果,根据本发明,完全形成接触销110a,同时借助于第二绝缘层保留在‘B’区域中的那部分112a平面化衬底表面。
而且,考虑到用于形成接触销的后续的CMP工艺,不要使第一绝缘层106形成得厚。就是说,本发明的第一绝缘层106可以形成得具有适当厚度,并且不一定与现有技术的一样厚。因此,可以减少形成接触销所需的CMP处理时间。
另外,由于第一绝缘层106形成得相对较薄,因此,可减小接触孔或通孔的高宽比。并可以形成没有空隙的接触销。
图2A-2D表示根据本发明第二实施例在集成电路中形成接触销且同时平面化衬底表面的新方法。参见图2A,例如金属的互连线202将要形成在集成电路的底层区域200上。底层区域200可以是半导体衬底或互连信号线。在底层区域200上,包括互连线202淀积具有厚度的第一绝缘层204。绝缘层204具有适当的厚度,可减少后面的CMP工艺处理时间,如第一实施例那样。互连线202用于使多级互连线例如底层区域200后来在其上形成的接触销电连接。绝缘层204可以典型地由氧化硅(SiO2)制成,但是也可以由选自:未掺杂硅酸盐玻璃(USG)、硼磷硅玻璃(BPSG)、磷硅玻璃(PSG)、SiN、SiON、SiOF或其混合材料中的一种使用化学汽相淀积(CVD)、回流、淀积/腐蚀和高密度等离子体(HDP)方法中的一种方法形成。绝缘层204还可以使用旋涂方法由选自SOG、可流动的氧化物(FOX)、聚合物或其混合材料中的一种构成。
这里,本例的最重要特征之一是,绝缘层204可以具有适合于后来进行CMP工艺以形成接触销的厚度。在淀积中,考虑到后来用于形成接触销的CMP工艺,不要使第一绝缘层204形成得非常厚。这是因为第一绝缘层204不是在其形成以形成接触销之后即刻被平面化腐蚀的。
参照图2A,然后在绝缘层204上淀积光刻胶掩模(未示出)并构图,用构图的光刻胶掩模作开口形成掩模进行腐蚀工艺,由此形成穿过要构成接触销的绝缘层204的接触孔206。接触孔206是通过绝缘层204并在互连线202上形成的。在绝缘层204上、接触孔206的两侧壁和底部上形成一般由TiN构成的阻挡层207,以便改善与后来要形成的接触销的接触电阻,抑制互连线202和接触销之间的反应,并提高与接触销的粘附性。代替TiN,阻挡层207可以由选自Ti、Ta、TaN、WN、和TiSiN中的一种构成。然后在绝缘层204上涂上一般由钨(W)构成的导电层208,填满接触孔206。代替钨,导电层208可以由选自:Al、Cu、Ti、TiN、多晶硅、W-Si、Al-Cu和Al-Cu-Si中的一种使用CVD、PVD、回流或压力填充方法形成。在本例中,导电钨层将作为例子在后面介绍。
图2B表示在进行深腐蚀工艺以形成接触销之后的集成电路。导电钨层208被干法或湿法深腐蚀,然后去掉TiN阻挡层。深腐蚀工艺继续进行直到完全露出绝缘层204的上表面为止,由此形成钨接触销208a。在深腐蚀工艺中,最好部分TiN阻挡层207不保留在相对低的台阶中,即‘D’区域。与两相邻互连线之间的间隔长的区域‘D’相比,绝缘层204在两相邻互连线之间的间隔短的区域‘C’处具有高度,如图2A所示。由于区域‘D’的绝缘层210比区域‘C’的薄,所以在区域‘C’和‘D’之间产生更严重的不平坦地形。这样,为了除去衬底表面的不平坦地形,需要对第一绝缘层204上的绝缘层进行淀积和平面化,如图2C和2D所示。
参见图2C,在进行导电钨层208和TiN阻挡层207的深腐蚀之后,在第一绝缘层204上,包括接触销208a淀积第二绝缘层210。第二绝缘层210最好由与第一绝缘层204或后来在其上所形成的绝缘层的材料相同的材料构成。
接下来是第二绝缘层210的平面化,形成如图2D所示的结构。正如所看到的,图2D中所示的器件结构与衬底表面被平面化的图1D中所示器件结构相似。第二绝缘层210的平面化可以用本领域公知CMP工艺实现,并继续进行到露出接触销208a的上表面为止。CMP工艺使用具有低选择性的浆料,以便同时抛光绝缘层和导电钨栓。结果,第二绝缘层210的部分210a保留在相对于接触销208a存在相对低台阶的‘C’和‘D’区域中。因此,完全形成接触销208a并且借助于第二绝缘层的残留部分210a同时平面化衬底表面。这里,另一重要特征是,CMP工艺是在用第二绝缘层210填满不平坦衬底表面的凹处之后进行的,以形成接触销208a。虽然上面没有提到,本领域技术人员应该意识到第二实施例的工作效果与第一实施例的效果一样。
Claims (9)
1.一种用于在集成电路中形成接触销的方法,包括以下步骤:
在其中具有多个扩散区的半导体衬底上形成导电结构;
在包括导电结构的半导体衬底上形成第一绝缘层,所述第一绝缘层在成组地形成导电结构的第一区域具有比未形成导电结构的第二区域高的台阶;
用构图的光刻胶掩模作为开口形成掩模对第一绝缘层进行腐蚀以形成接触孔;
在第一绝缘层上形成导电层,用导电层填满接触孔;
腐蚀导电层直到露出第一绝缘层的上表面为止;
在第一绝缘层上形成第二绝缘层;以及
平面化-腐蚀第二和第一绝缘层以形成接触销,并同时通过在第二区域中留下一部分第二绝缘层而平面化衬底表面。
2.根据权利要求1的方法,其中所述接触孔是通过第一绝缘层并在半导体衬底上形成的。
3.根据权利要求2的方法,其中所述接触孔是形成在半导体衬底中的每个扩散区上的。
4.根据权利要求1的方法,其中所述接触孔是通过第一绝缘层并在导电结构上形成的。
5.根据权利要求4的方法,还包括在形成导电层之前,在第一绝缘层上、接触孔的两侧壁和底部上形成阻挡层的步骤。
6.根据权利要求5的方法,其中所述阻挡层由Ti、TiN、Ta、TaN、WN、和TiSiN或其混合材料中的一种构成。
7.根据权利要求1的方法,其中所述接触孔是在半导体衬底中的导电结构上和每个扩散区上形成的。
8.根据权利要求1的方法,其中所述第二绝缘层是由与第一绝缘层相同的材料构成的。
9.根据权利要求1的方法,还包括在形成导电结构之前,在导电结构和半导体衬底之间形成氧化物层的步骤。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105336676A (zh) * | 2014-07-29 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | 接触插塞的形成方法 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100474537B1 (ko) * | 2002-07-16 | 2005-03-10 | 주식회사 하이닉스반도체 | 산화막용 cmp 슬러리 조성물 및 이를 이용한 반도체소자의 제조 방법 |
US6818555B2 (en) * | 2002-10-07 | 2004-11-16 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for metal etchback with self aligned etching mask |
JP4679277B2 (ja) * | 2005-07-11 | 2011-04-27 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
US7964502B2 (en) | 2008-11-25 | 2011-06-21 | Freescale Semiconductor, Inc. | Multilayered through via |
US9716035B2 (en) * | 2014-06-20 | 2017-07-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Combination interconnect structure and methods of forming same |
US9991133B2 (en) * | 2016-08-11 | 2018-06-05 | Tokyo Electron Limited | Method for etch-based planarization of a substrate |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4676867A (en) * | 1986-06-06 | 1987-06-30 | Rockwell International Corporation | Planarization process for double metal MOS using spin-on glass as a sacrificial layer |
JPH01108746A (ja) * | 1987-10-21 | 1989-04-26 | Toshiba Corp | 半導体装置の製造方法 |
US4879257A (en) * | 1987-11-18 | 1989-11-07 | Lsi Logic Corporation | Planarization process |
DE69034137D1 (de) * | 1990-10-01 | 2004-06-03 | St Microelectronics Srl | Herstellung von Kontaktanschlüssen bei der alles überdeckenden CVD-Abscheidung und Rückätzen |
US5143867A (en) * | 1991-02-13 | 1992-09-01 | International Business Machines Corporation | Method for depositing interconnection metallurgy using low temperature alloy processes |
JP3216104B2 (ja) * | 1991-05-29 | 2001-10-09 | ソニー株式会社 | メタルプラグ形成方法及び配線形成方法 |
JPH05190684A (ja) * | 1992-01-16 | 1993-07-30 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US5618381A (en) * | 1992-01-24 | 1997-04-08 | Micron Technology, Inc. | Multiple step method of chemical-mechanical polishing which minimizes dishing |
JP2756887B2 (ja) * | 1992-03-02 | 1998-05-25 | 三菱電機株式会社 | 半導体装置の導電層接続構造およびその製造方法 |
US5250472A (en) * | 1992-09-03 | 1993-10-05 | Industrial Technology Research Institute | Spin-on-glass integration planarization having siloxane partial etchback and silicate processes |
US5312512A (en) * | 1992-10-23 | 1994-05-17 | Ncr Corporation | Global planarization using SOG and CMP |
US5268330A (en) * | 1992-12-11 | 1993-12-07 | International Business Machines Corporation | Process for improving sheet resistance of an integrated circuit device gate |
US5328553A (en) * | 1993-02-02 | 1994-07-12 | Motorola Inc. | Method for fabricating a semiconductor device having a planar surface |
JP3326698B2 (ja) * | 1993-03-19 | 2002-09-24 | 富士通株式会社 | 集積回路装置の製造方法 |
US5356513A (en) * | 1993-04-22 | 1994-10-18 | International Business Machines Corporation | Polishstop planarization method and structure |
JPH07106419A (ja) * | 1993-10-05 | 1995-04-21 | Toshiba Corp | 半導体装置の製造方法 |
US5496774A (en) * | 1993-12-01 | 1996-03-05 | Vlsi Technology, Inc. | Method improving integrated circuit planarization during etchback |
US5545581A (en) * | 1994-12-06 | 1996-08-13 | International Business Machines Corporation | Plug strap process utilizing selective nitride and oxide etches |
US5786273A (en) * | 1995-02-15 | 1998-07-28 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and associated fabrication method |
JP2638546B2 (ja) * | 1995-02-28 | 1997-08-06 | 日本電気株式会社 | 半導体装置の製造方法 |
US5527736A (en) * | 1995-04-03 | 1996-06-18 | Taiwan Semiconductor Manufacturing Co. | Dimple-free tungsten etching back process |
US5747383A (en) * | 1995-09-05 | 1998-05-05 | Taiwan Semiconductor Manufacturing Company Ltd | Method for forming conductive lines and stacked vias |
US5665657A (en) * | 1995-09-18 | 1997-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd | Spin-on-glass partial etchback planarization process |
US5847464A (en) * | 1995-09-27 | 1998-12-08 | Sgs-Thomson Microelectronics, Inc. | Method for forming controlled voids in interlevel dielectric |
US5861342A (en) * | 1995-12-26 | 1999-01-19 | Vlsi Technology, Inc. | Optimized structures for dummy fill mask design |
US5830804A (en) * | 1996-06-28 | 1998-11-03 | Cypress Semiconductor Corp. | Encapsulated dielectric and method of fabrication |
US6025269A (en) * | 1996-10-15 | 2000-02-15 | Micron Technology, Inc. | Method for depositioning a substantially void-free aluminum film over a refractory metal nitride layer |
KR100243272B1 (ko) * | 1996-12-20 | 2000-03-02 | 윤종용 | 반도체 소자의 콘택 플러그 형성방법 |
KR100266749B1 (ko) * | 1997-06-11 | 2000-09-15 | 윤종용 | 반도체 장치의 콘택 플러그 형성 방법 |
US5961617A (en) * | 1997-08-18 | 1999-10-05 | Vadem | System and technique for reducing power consumed by a data transfer operations during periods of update inactivity |
-
1998
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105336676A (zh) * | 2014-07-29 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | 接触插塞的形成方法 |
CN105336676B (zh) * | 2014-07-29 | 2018-07-10 | 中芯国际集成电路制造(上海)有限公司 | 接触插塞的形成方法 |
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JP2000003915A (ja) | 2000-01-07 |
DE19920970C2 (de) | 2002-10-24 |
US6218291B1 (en) | 2001-04-17 |
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FR2782841A1 (fr) | 2000-03-03 |
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