ES2110811T3 - Metodo para encapsular un circuito integrado. - Google Patents

Metodo para encapsular un circuito integrado.

Info

Publication number
ES2110811T3
ES2110811T3 ES95201126T ES95201126T ES2110811T3 ES 2110811 T3 ES2110811 T3 ES 2110811T3 ES 95201126 T ES95201126 T ES 95201126T ES 95201126 T ES95201126 T ES 95201126T ES 2110811 T3 ES2110811 T3 ES 2110811T3
Authority
ES
Spain
Prior art keywords
semiconductor circuit
lead frame
supporting surface
encapsulating
plastic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES95201126T
Other languages
English (en)
Inventor
Peter Jacobus Kaldenberg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EURASEM BV
Original Assignee
EURASEM BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EURASEM BV filed Critical EURASEM BV
Application granted granted Critical
Publication of ES2110811T3 publication Critical patent/ES2110811T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/54—Encapsulations having a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

METODO PARA ENCAPSULAR UN CIRCUITO SEMICONDUCTOR INTEGRADO (MATRIZ) QUE COMPRENDE LOS SIGUIENTES PASOS: A) MONTAR EL CIRCUITO SEMICONDUCTOR SOBRE LA SUPERFICIE DE SOPORTE DE UN MARCO CONDUCTOR, B) FIJAR HILOS DE CONEXION ENTRE LAS ARANDELAS DEL CIRCUITO SEMICONDUCTOR Y PARTES ELEGIDAS DEL MARCO CONDUCTOR (ENLACE), C) PRODUCIR UN EMBALAJE PLASTICO MEDIANTE UN MOLDE, CUYO EMBALAJE RODEA AL MENOS EL CIRCUITO SEMICONDUCTOR, LA SUPERFICIE DE SOPORTE, LOS HILOS DE CONEXION Y PARTE DEL MARCO CONDUCTOR. DE ACUERDO CON LA INVENCION ENTRE EL PASO B) Y EL PASO C) SE REALIZA UN PASO ADICIONAL: SUMINISTRAR UN VOLUMEN PREDETERMINADO DE PLASTICO TRANSPARENTE DE RADIACION EN ESE LADO DEL CIRCUITO SEMICONDUCTOR OPUESTO AL LATERAL QUE ESTA FIJADO A LA SUPERFICIE DE SOPORTE, CUYO MATERIAL PLASTICO TIENE UNA TEMPERATURA DE VIDRIO INFERIOR A LA TEMPERATURA QUE SE USA PARA REALIZAR EL PASO C).
ES95201126T 1994-05-09 1995-05-02 Metodo para encapsular un circuito integrado. Expired - Lifetime ES2110811T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL9400766A NL9400766A (nl) 1994-05-09 1994-05-09 Werkwijze voor het inkapselen van een geintegreerde halfgeleiderschakeling.

Publications (1)

Publication Number Publication Date
ES2110811T3 true ES2110811T3 (es) 1998-02-16

Family

ID=19864175

Family Applications (1)

Application Number Title Priority Date Filing Date
ES95201126T Expired - Lifetime ES2110811T3 (es) 1994-05-09 1995-05-02 Metodo para encapsular un circuito integrado.

Country Status (10)

Country Link
US (1) US5863810A (es)
EP (1) EP0682374B1 (es)
JP (1) JPH07307359A (es)
AT (1) ATE162011T1 (es)
DE (1) DE69501361T2 (es)
DK (1) DK0682374T3 (es)
ES (1) ES2110811T3 (es)
GR (1) GR3026168T3 (es)
NL (1) NL9400766A (es)
SI (1) SI0682374T1 (es)

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EP0646971B1 (de) 1993-09-30 1997-03-12 Siemens Aktiengesellschaft Zweipoliges SMT-Miniatur-Gehäuse für Halbleiterbauelemente und Verfahren zu dessen Herstellung
US5866953A (en) * 1996-05-24 1999-02-02 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant
DE19638667C2 (de) * 1996-09-20 2001-05-17 Osram Opto Semiconductors Gmbh Mischfarbiges Licht abstrahlendes Halbleiterbauelement mit Lumineszenzkonversionselement
BRPI9715293B1 (pt) 1996-06-26 2016-11-01 Osram Ag elemento de cobertura para um elemento de construção optoeletrônico
JP3012816B2 (ja) * 1996-10-22 2000-02-28 松下電子工業株式会社 樹脂封止型半導体装置およびその製造方法
JP3189115B2 (ja) * 1996-12-27 2001-07-16 株式会社新川 半導体装置及びワイヤボンディング方法
EP0936683A4 (en) * 1997-06-27 2000-11-22 Iwasaki Electric Co Ltd REFLECTIVE LIGHT-EMITTING DIODE
DE29825062U1 (de) * 1997-07-29 2004-07-22 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement
JP2000114304A (ja) * 1998-10-08 2000-04-21 Shinkawa Ltd ワイヤボンディング方法
US6140141A (en) * 1998-12-23 2000-10-31 Sun Microsystems, Inc. Method for cooling backside optically probed integrated circuits
FR2798226B1 (fr) * 1999-09-02 2002-04-05 St Microelectronics Sa Procede de mise en boitier d'une puce de semi-conducteur contenant des capteurs et boitier obtenu
SG106050A1 (en) * 2000-03-13 2004-09-30 Megic Corp Method of manufacture and identification of semiconductor chip marked for identification with internal marking indicia and protection thereof by non-black layer and device produced thereby
US6379988B1 (en) 2000-05-16 2002-04-30 Sandia Corporation Pre-release plastic packaging of MEMS and IMEMS devices
US6531341B1 (en) 2000-05-16 2003-03-11 Sandia Corporation Method of fabricating a microelectronic device package with an integral window
US6384473B1 (en) 2000-05-16 2002-05-07 Sandia Corporation Microelectronic device package with an integral window
FR2819103B1 (fr) * 2000-12-29 2003-12-12 St Microelectronics Sa Boitier semi-conducteur optique a pastille transparente et son procede de fabrication
CN1288750C (zh) * 2001-11-23 2006-12-06 皇家飞利浦电子股份有限公司 半导体器件和包封集成电路的方法
FR2835653B1 (fr) * 2002-02-06 2005-04-15 St Microelectronics Sa Dispositif semi-conducteur optique
JP2003243577A (ja) * 2002-02-18 2003-08-29 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US6835592B2 (en) * 2002-05-24 2004-12-28 Micron Technology, Inc. Methods for molding a semiconductor die package with enhanced thermal conductivity
JP4190269B2 (ja) 2002-07-09 2008-12-03 新光電気工業株式会社 素子内蔵基板製造方法およびその装置
DE10254648A1 (de) * 2002-11-22 2004-06-09 Infineon Technologies Ag Trägerstruktur für einen Chip und Verfahren zum Herstellen derselben
JP2004319530A (ja) * 2003-02-28 2004-11-11 Sanyo Electric Co Ltd 光半導体装置およびその製造方法
US20060124915A1 (en) * 2003-05-19 2006-06-15 Siegfried Buettner Production of an optoelectronic component that is enclosed in plastic, and corresponding methods
US20050009239A1 (en) * 2003-07-07 2005-01-13 Wolff Larry Lee Optoelectronic packaging with embedded window
US7179688B2 (en) * 2003-10-16 2007-02-20 Kulicke And Soffa Industries, Inc. Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method
US20050146057A1 (en) * 2003-12-31 2005-07-07 Khor Ah L. Micro lead frame package having transparent encapsulant
US7064424B2 (en) * 2004-05-06 2006-06-20 Wilson Robert E Optical surface mount technology package
US20060043612A1 (en) * 2004-09-02 2006-03-02 Stats Chippac Ltd. Wire sweep resistant semiconductor package and manufacturing method thereof
US7015587B1 (en) * 2004-09-07 2006-03-21 National Semiconductor Corporation Stacked die package for semiconductor devices
US7273767B2 (en) * 2004-12-31 2007-09-25 Carsem (M) Sdn. Bhd. Method of manufacturing a cavity package
US7808004B2 (en) * 2006-03-17 2010-10-05 Edison Opto Corporation Light emitting diode package structure and method of manufacturing the same
TWI313501B (en) * 2006-03-22 2009-08-11 Ind Tech Res Inst A process for manufacture plastic package of mems devices and the structure for the same
US20070292982A1 (en) * 2006-06-16 2007-12-20 Jeffery Gail Holloway Method for Manufacturing Transparent Windows in Molded Semiconductor Packages
WO2008082565A1 (en) * 2006-12-29 2008-07-10 Tessera, Inc. Microelectronic devices and methods of manufacturing such devices
JP5388673B2 (ja) * 2008-05-07 2014-01-15 パナソニック株式会社 電子部品
EP2154713B1 (en) * 2008-08-11 2013-01-02 Sensirion AG Method for manufacturing a sensor device with a stress relief layer
US9366593B2 (en) * 2013-09-27 2016-06-14 Infineon Technologies Ag Pressure sensor package with integrated sealing
EP3121853B1 (en) * 2015-07-23 2022-01-19 ams AG Method of producing an optical sensor at wafer-level and optical sensor
JPWO2022085446A1 (es) * 2020-10-19 2022-04-28

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Also Published As

Publication number Publication date
DE69501361D1 (de) 1998-02-12
DK0682374T3 (da) 1998-05-04
JPH07307359A (ja) 1995-11-21
US5863810A (en) 1999-01-26
SI0682374T1 (en) 1998-06-30
ATE162011T1 (de) 1998-01-15
DE69501361T2 (de) 1998-05-07
EP0682374A1 (en) 1995-11-15
EP0682374B1 (en) 1998-01-07
NL9400766A (nl) 1995-12-01
GR3026168T3 (en) 1998-05-29

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