EP3010042B1 - Halbleiterbauelement - Google Patents

Halbleiterbauelement Download PDF

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EP3010042B1
EP3010042B1 EP14811117.2A EP14811117A EP3010042B1 EP 3010042 B1 EP3010042 B1 EP 3010042B1 EP 14811117 A EP14811117 A EP 14811117A EP 3010042 B1 EP3010042 B1 EP 3010042B1
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region
layer
type
voltage
separation region
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French (fr)
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EP3010042A4 (de
EP3010042A1 (de
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Masaharu Yamaji
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
    • H01L29/7818—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
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    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET

Definitions

  • the present invention relates to semiconductor devices such as high-voltage integrated circuit devices.
  • IGBTs Insulated Gate Bipolar Transistors
  • MOSFETs Metal-Oxide-Semiconductor Field-Effect Transistors
  • FIG. 10 is a structural diagram of a main part that includes a power module forming a motor control inverter and a main circuit drive circuit (for example, see PTL 1). Power devices used to drive a three-phase motor 70 form a bridge circuit and are stored in the same package so as to have a structure as a power module 71.
  • the power module 71 is composed of IGBTs as power devices and diodes.
  • the power devices may be MOSFETs.
  • the IGBTs are represented by upper arm output elements Q1 to Q3 and lower arm output elements Q4 to Q6, and the diodes are represented by D1 to D6.
  • a gate of each IGBT is connected to an output of a main circuit drive circuit 72, and outputs U, V, and W of the inverter formed by the power module 71 are connected to the three-phase motor 70.
  • the main power supply VCC2 supplies a high voltage of usually AC 100 to 400 V. Particularly, when each of the Q4, the Q5, and the Q6 is in an OFF state and each of the Q1, the Q2, and the Q3 is in an ON state, an emitter potential of each of the Q1, the Q2, and Q3 is at high voltage level.
  • input/output terminals I/O (Input/Output) of the main circuit drive circuit 72 are usually connected to a microcomputer that entirely controls the inverter circuit composed of the power module 71.
  • the main circuit drive circuit 72 is composed of a high-voltage integrated circuit device.
  • FIG. 11 is a location diagram of a main part including each element in a case in which the main circuit drive circuit is composed of a high-voltage integrated circuit device.
  • the main circuit drive circuit 72 transmits and receives signals to and from a microcomputer through the input/output terminals I/O.
  • the main circuit drive circuit 72 includes a control circuit (CU: Control Unit) that generates a control signal for turning ON/OFF IGBTs.
  • the main circuit drive circuit 72 includes gate drive circuits (GDUs: Gate Driver Units) that receive a signal from the CU to drive the gates of the IGBTs and also detects overcurrent in the IGBTs to transmit an abnormal signal to the CU.
  • GDUs Gate Driver Units
  • LSU level shift circuit
  • the GDUs include a GDU-U, a GDU-V, and a GDU-W respectively connected to the Q1, the Q2, and the Q3 respectively and a GDU-X, a GDU-Y, and a GDU-Z respectively connected to the Q4, the Q5, and the Q6 respectively.
  • the GDU-U, the GDU-V, and the GDU-W respectively are circuits whose U-OUT, V-OUT, and W-OUT terminals respectively are at reference potential. Next will be a description of one example of the LSU in the circuit.
  • FIG. 12 is a basic structure diagram of an LSU (a level shift circuit).
  • the basic structure uses a high-voltage n-channel MOSFET 61 and a resistor RL1.
  • the high-voltage n-channel MOSFET 61 serves to level-shift a signal S1 from a CU (a control circuit) and output it to a GDU-U, a GDU-V, and a GDU-W.
  • a signal S2 to be input to an upper arm GDU is output from between the high-voltage n-channel MOSFET 61 and the resistor RL1.
  • the high-voltage n-channel MOSFET 61 used in the LSU is required to have a breakdown voltage of about from 600 to 1400 V equivalent to that of the IGBTs (the upper and lower arm output elements Q1 to Q6) that drive the three-phase motor 70.
  • FIG. 13 is a circuit structural diagram in a case in which the GDU-U that drives the upper arm output element Q1 of FIG. 10 and the GDU-X illustrated in FIG. 11 , an LSU, and a bootstrap diode Db are integrated in one chip. Obviously, the GDU-V and the GDU-W have the same structure.
  • FIG. 14 illustrates a sectional view of a main part in a case in which the high-voltage integrated circuit device illustrated in FIG. 13 is formed on an epitaxial substrate.
  • the diagram illustrates the GDU-U and the bootstrap diode Db illustrated in FIG. 13 .
  • a Vb voltage (voltage of C1) provides a power supply to the GDU-U.
  • the Vb voltage is set to about 15 V in order to surely enhance (full ON) the external IGBT (Q1) that the HV gate driver IC drives.
  • the Vb voltage is the voltage of a floating power supply, and a U-OUT voltage that has a rectangular waveform at high frequency is used as a reference potential.
  • the floating power supply is composed of a combination of the bootstrap diode Db and a bootstrap capacitor C1.
  • the bootstrap circuit operates when the gate of the low-side IGBT (Q4) is in an ON state and the U-OUT voltage drops to ground potential through the IGBT (Q4) At this time, the bootstrap capacitor C1 is charged by a VDD power supply as a low voltage power supply of 15 V through the bootstrap diode Db.
  • a reverse breakdown voltage of the bootstrap diode Db is required to be set to a breakdown voltage value of about from 600 to 1400 V equivalent to the high-voltage n-channel MOSFET 61.
  • the bootstrap capacitor C1 used for charging here needs to have a large capacitance of 100 nF or more and thus can hardly be integrated. Due to this, it is common to use an externally-attached tantalum capacitor, ceramic capacitor, or the like.
  • PTL 3 suggests that the formation of a pn diode by using an SOI (Silicon on Insulator) substrate makes voltage resistance of a bootstrap diode higher and reduces hole leakage to the substrate.
  • SOI Silicon on Insulator
  • PTL 4 discloses a SON (Silicon on Nothing) structure formation technique that does not cause cost increase and low reliability, in which a plurality of grooves are two-dimensionally formed in an array on a surface of a silicon substrate and then the silicon substrate is subjected to heat processing to change the plurality of grooves to a single planar cavity.
  • SON Silicon on Nothing
  • PTL 5 provides a method for manufacturing a low-cost and high-quality SON semiconductor substrate that includes a first step of implanting ion for forming a minute cavity in a desired region on a substrate and a second step of performing heat processing on the substrate with the minute cavity formed by the first step, in which the second step includes at least a high temperature heat processing step for exposing the substrate to a temperature of 1000°C or higher.
  • PTL 5 discloses a method that can manufacture a high performance high-voltage integrated circuit device by performing the above semiconductor substrate manufacturing method in steps of the method.
  • PTL 6 discloses a technique that can maintain high breakdown voltage when reverse breakdown voltage is applied and can prevent hole leakage to a substrate when charging a bootstrap capacitor, by locating a bootstrap diode in a high-voltage junction terminating region surrounding a high-side drive circuit unit and forming a cavity below an anode region and a cathode region of the diode.
  • PTL 7 discloses a bootstrap emulator function in which a bootstrap FET (a field-effect transistor) is located in a part of a high-voltage junction terminating region surrounding a high-side drive circuit unit and the gate of the FET is controlled at a timing when charging a bootstrap capacitor.
  • a bootstrap FET a field-effect transistor
  • PTL 8 describes a SOI lateral semiconductor device that can obtain high breakdown voltage and low switching loss even with the use of a thin buried oxide film formed by a SIMOX method.
  • a high-voltage IGBT and a MOSFET are arranged in parallel so as to vertically sandwich a buried oxide film of a partial SOI substrate formed by oxygen ion implantation.
  • the bootstrap diode Db has a structure in which an n - layer as a N epi layer and an n + buried layer are provided on a p - substrate, and a p + diffusion is formed as an anode diffusion region.
  • PTL 6 previously cited also states that, in a period of time for charging the bootstrap capacitor, holes escape from an anode region-side (VDD) as the p + region of the bootstrap diode Db to a p - substrate via an n + buried layer to become a leakage current Ileak.
  • VDD anode region-side
  • the high-voltage n - channel MOSFET as the level shift element uses, as a backgate layer, the p-type GND region surrounding the periphery thereof and, as a drain drift layer, the n - region as a withstand voltage region surrounded by the p - region, the bootstrap diode is fixed at the VDD potential illustrated in FIG. 13 and the cathode region is connected to the U-VCC terminal similarly illustrated in FIG. 13 . Accordingly, the high voltage n-channel MOSFET and the bootstrap diode cannot be located close to each other, and need to be sufficiently spaced apart from each other. Alternatively, an element separation structure is additionally needed, such as trench groove formation or formation of a diffusion layer for separation in each thereof. This leads to increase in chip area of the HV gate driver IC and increase in production cost.
  • Fig. 15 is a planar structural diagram of a case in which both of the high-voltage n-channel MOSFET and the bootstrap diode described in PTL 6 are located in the same high-voltage junction terminating region.
  • potentials of a drain layer of a level shifter (the high-voltage n-channel MOSFET) and a cathode region 7K of the bootstrap diode illustrated in FIG. 15 there is a difference between the drain potential and the VCC potential, as described above.
  • the drain layer and the anode region 6A are located at a distance of about several hundred ⁇ m from each other.
  • the cathode region 7K and the drain layer are also spaced apart from each other at a distance of about several hundred ⁇ m so that, for example, in such a reverse recovery state where the drain and the cathode region 7K are raised to high voltage, electron carriers substituted in the cathode region 7K are not mistakenly injected into the drain layer of the high voltage n-channel MOSFET. This is because, since the high voltage n-channel MOSFET is the level shift element, injection of the electron carriers to the drain layer leads to malfunction of the level shift circuit.
  • the two elements the high voltage n-channel MOSFET and the bootstrap diode, can be located in different high-voltage junction terminating regions.
  • the locations thereof occupy an extra location area, thus inevitably increasing the chip area of the HV gate driver IC.
  • problems caused by locating both of the high-voltage n-channel MOSFET and the bootstrap diode in the same high-voltage junction terminating region include, besides electrical separation between the elements, reduction in charging ability of the bootstrap diode.
  • two high voltage n-channel MOSFETs are needed for a setting signal and a resetting signal. Locating these elements in the high-voltage junction terminating region imposes restriction on location areas for the anode region and the cathode region of the bootstrap diode.
  • a power device here, power MOSFET
  • a bootstrap capacitor to be charged has a capacitance of about from 100 nF to 1 ⁇ F.
  • a charging current of the diode in charging the capacitor may be of about several ten mA.
  • the capacitance of a bootstrap capacitor to be charged is about from several ⁇ F to several ten ⁇ F.
  • the diode when charging the capacitor, the diode needs to supply about several hundred mA of charging current.
  • a forward voltage (VF) at that time is around several V that is equivalent to a discharging voltage of the capacitor.
  • VF forward voltage
  • a drift resistance of the bootstrap diode needs to be reduced and a sufficient element area needs to be secured.
  • US 5 412 234 A describes to limit the voltage across a diode to the level of the pinch-off voltage of a JFET in an integrated circuit by connecting the diode in series with the JFET.
  • the JFET together with at least one further circuit element is formed in a common island surrounded by an island insulation region.
  • the gate of the JFET extends along the edge of the island and is separated from the relevant portion of the island insulation region substantially only by the source of the JFET. In the pinch-off condition, the gate divides the island into a high-voltage portion and a low-voltage portion which is coupled to the diode.
  • EP 1 067 599 A1 describes a monocrystalline silicon substrate that is subjected to the following operations: implantation of doping impurities in a high concentration to form a planar region of a first type, selective anisotropic etching in order to hollow out trenches to a depth greater than the depth of the planar region, oxidation of the silicon inside the trenches starting a certain distance from the surface of the substrate, until a silicon dioxide plaque is formed, surmounted by residues of strongly-doped silicon, epitaxial growth between and on top of the silicon residues to close the trenches and to bring about a redistribution of the doping impurities into the silicon grown to produce a buried region in an epitaxial layer.
  • An object of the present invention is to provide a semiconductor device that can suppress leakage current by holes that flows to a substrate side in forward biasing of a bootstrap diode, and can increase charging current for a bootstrap capacitor, as well as can suppress increase in chip area.
  • the present invention relates to a semiconductor device according to independent claim 1. Preferred embodiments are described in the dependent claims.
  • the semiconductor device comprises:
  • the present invention it is possible to suppress leakage current by holes that flows to a substrate side in forward biasing of a bootstrap diode, and to increase charging current for a bootstrap capacitor, as well as, to suppress increase in chip area.
  • n or "p” is put in each layer and each region, which means that electrons or holes are majority carriers.
  • signs "+” and “-” attached to “n” and “p” mean that the semiconductor region has a relative impurity concentration higher or lower, respectively, than semiconductor regions without the signs "+” and "-”.
  • FIGs. 1 , 3 , and 6 to 9 of the accompanying drawings that will be illustrated in the first to the fourth embodiments, hatching that represents sections is omitted for easier viewing of the drawings.
  • the first to fourth embodiments below will focus on and exemplarily describe high-voltage integrated circuit devices, as typical examples of a "semiconductor device" of the present invention.
  • FIGs. 1 to 3 illustrate diagrams of parts relating to a gate driver circuit portion (GDU-U, LSU, and bootstrap diode Db) of U phase, among U phase, V phase, and W phase of a high side of a bridge circuit, for example, illustrated in FIGs. 10 and 11 .
  • GDU-U gate driver circuit portion
  • LSU bootstrap diode Db
  • a high-voltage integrated circuit device 100 mainly includes a semiconductor base body where an n - type epitaxial growth layer (semiconductor layer) 2 as a surface layer is formed on a surface of a p - type semiconductor substrate 1 made of, for example, monocrystalline silicon.
  • the high-voltage integrated circuit device 100 according to the first embodiment of the invention includes an n - type buried layer 50 formed by diffusion at a depth of about 2 to 10 ⁇ m from the surface of the semiconductor substrate 1 or formed by epitaxial growth on the surface of the semiconductor substrate 1.
  • the high-voltage integrated circuit device 100 includes a p-channel MOSFET 31 and a p-type offset region 21 located in an upper part of an epitaxial growth layer 2 on the buried layer 50 and an n-channel MOSFET 32 formed in the offset region 21.
  • the p-channel MOSFET 31 and the n-channel MOSFET 32 forms a CMOS circuit 33.
  • the CMOS circuit 33 is a logic circuit.
  • the high-voltage integrated circuit device 100 includes, as illustrated in FIG. 1 and FIG. 2A , an n + -type cathode region 7 formed in a ring-like shape so as to surround the CMOS circuit 33 in an upper part of the epitaxial growth layer 2, a p + -type anode region 6 spaced apart from the cathode region 7 to be formed in a ring-like shape so as to surround the cathode region 7, and a p-type floating region (a second separation region) 5 spaced apart from the anode region 6 to be formed in a ring-like shape so as to surround the anode region 6.
  • the cathode region 7 and the anode region 6 form a bootstrap diode Db.
  • the high-voltage integrated circuit device 100 includes a p-type deep region (a first separation region) 4 that is spaced apart from the floating region 5 to be formed so as to surround the floating region 5 and to which GND potential is applied.
  • a p-type deep region (a first separation region) 4 that is spaced apart from the floating region 5 to be formed so as to surround the floating region 5 and to which GND potential is applied.
  • circuits of other phases (V phase and W phase) can similarly be formed, as illustrated in FIG. 11 .
  • X phase-, Y phase-, and Z-phase circuits can also be formed on the same semiconductor substrate.
  • the high-voltage integrated circuit device 100 includes a cavity (a first insulating separation region) 3 of a SON structure formed so as to contact with the floating region 5 and a p-type diode separation layer (a third separation region) 52.
  • the cavity 3 is formed by forming a large number of minute trenches from a surface of the buried layer 50 to an inside of the buried layer 50 and performing annealing processing. Accordingly, the cavity 3 is formed inside the buried layer 50.
  • the diode separation layer 52 is surrounded by the cathode region 7.
  • the deep region 4 is a region for fixing a potential of the semiconductor substrate 1 to, for example, a GND potential.
  • a p-type base region 4a is a diffusion layer selectively formed in an upper part of the epitaxial growth layer 2 and used as a backgate layer of a high voltage n-channel MOSFET 62 as a level shift device.
  • the high voltage n-channel MOSFET 62 includes two MOSFETs, a setting MOSFET 62a and a resetting MOSFET 62b (see FIG. 2B ).
  • n + -type source region 55 and a p + -type contact region 56 of the high voltage n-channel MOSFET 62 are formed on an upper part of the base region 4a.
  • a gate electrode 53 made of polysilicon via a gate oxide film 37 (such as SiO 2 ) as a gate insulating film.
  • the p-type deep region 4 and the p-type base region 4a are in contact with each other, but may be formed to be spaced apart from each other.
  • the n + -type source region 55 is formed on the upper part of the base region 4a, and the p + -type contact region 56 is formed on an upper part of each of the deep region 4 and the base region 4a.
  • a p-type high-side separation layer (a fourth separation region) 51 is spaced apart from the diode separation layer 52 to be formed so as to surround the CMOS circuit 33 and contact with the cavity 3 located below the CMOS circuit 33.
  • an n + -type drain contact region 57 is formed on a surface of the epitaxial growth layer 2 (a region E) surrounded by the high-side separation layer 51 and the diode separation layer 52 as a drain pickup layer of the high voltage n-channel MOSFET 62, and a drain electrode 54 is formed on the drain contact region 57.
  • No cavity 3 is formed at a bottom portion of the epitaxial growth layer 2 surrounded by the high-side separation layer 51 and the diode separation layer 52.
  • One end of a level shift resistor RL is connected to the drain electrode 54 and the other end thereof is connected to a U-VCC terminal 13.
  • the deep region 4 is connected to a GND terminal 11, and the anode region 6 is connected to a VDD terminal 12.
  • the cathode region 7 is connected to the U-VCC terminal 13.
  • the U-VCC terminal 13 is connected to a high potential-side of an externally-attached bootstrap capacitor C1 and furthermore connected to a p + -type source region 18 of the p-channel MOSFET 31 forming the CMOS circuit 33.
  • a lower potential-side of the bootstrap capacitor C1 is connected to an n + -type source region 22 of the n-channel MOSFET 32 forming the CMOS circuit 33 and furthermore connected to a U-OUT terminal 14.
  • a p + -type drain region 19 of the p-channel MOSFET 31 and an n + -type drain region 23 of the n-channel MOSFET 32 are connected to each other, and then the connection is connected to a U-GATE terminal 15.
  • a floating potential region 34 in which the CMOS circuit 33 is formed is connected to a high potential-side of a bootstrap power supply.
  • the VDD terminal 12 is a high potential-side terminal of a VDD power supply (control power supply) 16 that drives a low-side circuit, and the VDD power supply 16 is a low voltage power supply that supplies several ten volts.
  • the U-VCC terminal 13 is a high potential-side terminal of the bootstrap capacitor C1 that drives a high-side circuit.
  • An intermediate potential of the U-OUT terminal 14 varies between a high potential-side potential VCC2H and a low potential-side potential VCC2L of a main power supply VCC2.
  • VCC2H high potential-side potential
  • VCC2L low potential-side potential
  • the high-side separation layer 51 and the diode separation layer 52 are partially connected to each other, as illustrated in FIGs. 2A and 2B , and formed simultaneously.
  • Each of the deep region 4, the floating region 5, the anode region 6, the cathode region 7, the diode separation layer 52, and the high-side separation layer 51 is formed in a closed ring-like shape so that a planar shape of each thereof surrounds the floating potential region 34, as illustrated in FIG. 2A .
  • reference signs 8, 9, 10, 26, 27, 29, 30, and 54 represent electrodes connected to each layer
  • reference signs 25, 28, and 53 represent gate electrodes.
  • reference signs 20 and 57, and 24 and 56 are contact regions.
  • the anode region 6 has a structure in which a p + -type region that becomes a contact layer is formed in an upper part of a p-type region (not illustrated)
  • the cathode region 7 has a structure in which an n + -type region that becomes a contact layer is formed in an upper part of an n-type region (not illustrated).
  • the p-type region and the n-type region are omitted.
  • the floating region 5, the diode separation layer 52, and the high-side separation layer 51 are floating regions whose potentials are not fixed.
  • the FET may be either of MOS type having a gate insulating film made of an oxide film or of MIS type having a gate insulating film made of a silicon oxide film, a silicon nitride film, or an insulating film such as a layered film thereof.
  • the cavity 3 is selectively formed in an upper part of the buried layer 50.
  • the cavity 3 is at least formed beneath (a bottom portion) the bootstrap diode Db, beneath (a bottom portion) a part between the drain contact regions 57 of the high voltage n-channel MOSFET 62, and beneath (a bottom portion) the floating potential region 34.
  • the floating region 5, the high-side separation layer 51, and the diode separation layer 52, respectively, are formed so as to contact with the cavity 3.
  • the high-side separation layer 51 and the diode separation layer 52 are connected to form a region and both thereof are at the same potential.
  • Each of the floating region 5, the high-side separation layer 51, and the diode separation layer 52 is formed so as to reach beneath the epitaxial growth layer 2 from a surface thereof to a depth direction thereof.
  • the cavity 3 provided beneath the epitaxial growth layer 2 in such a manner as to cover an area below a region where the bootstrap diode Db is formed corresponds to the first insulating separation region of the present invention. Additionally, the cavity 3 provided in a lower part of the epitaxial growth layer 2 in such a manner as to cover an area below the logic circuit (the floating potential region 34) corresponds to a second insulating separation region of the invention.
  • the region of the epitaxial growth layer 2 having the bootstrap diode Db formed thereon has the same thickness as the floating potential region 34 having the CMOS circuit (the logic circuit) 33 formed thereon and is located in an island shape so as to surround the floating potential region 34 on the buried layer 50.
  • the deep region 4 is provided in a ring-like shape so as to surround the region of the epitaxial growth layer 2 having the bootstrap diode Db formed thereon and is spaced apart from the floating potential region 34 to be formed so as to reach the semiconductor substrate 1 from the surface of the epitaxial growth layer 2.
  • the floating region 5 is spaced apart from the deep region 4 to be formed in a ring-like shape so as to surround the epitaxial growth layer 2 of the part where the bootstrap diode Db is formed and reaches the cavity 3 in such a manner as to pass through from the surface of the epitaxial growth layer 2 to the cavity 3.
  • LOCOS is selectively formed on the surface of the epitaxial growth layer 2, and in active portions without the LOCOS are formed a GND electrode 8 connected to the deep region 4, an anode electrode 9 connected to the anode region 6, a cathode electrode 10 connected to the cathode region 7, and the like.
  • the GND terminal 11 is connected to the GND electrode 8
  • the VDD terminal 12 is connected to the anode electrode 9
  • the U-VCC terminal 13 is connected to the cathode electrode 10.
  • the high voltage n-channel MOSFET 62 and the level shift resistor RL form a level shift circuit LSU.
  • the potential of the drain contact region 57 is a ground potential when the high voltage n-channel MOSFET 62 is ON, and the potential thereof is a potential of the U-VCC terminal 13 when it is OFF.
  • the potential of the U-VCC terminal 13 becomes a potential obtained by adding a voltage (a fixed voltage) of the VDD power supply 16 to a potential of the U-OUT terminal 14.
  • FIGs. 4A and 4B are plan views of a main part of another example of the high-voltage integrated circuit device 100 according to the first embodiment of the present invention.
  • FIG. 4A is a general view of gate driver circuits (GDUs) and a withstand-voltage structure portion surrounding the gate driver circuits (GDUs), and
  • FIG. 4B is an enlarged view illustrated by enlarging a region Fb illustrated in FIG. 4A .
  • the high-voltage integrated circuit device 100 illustrated in FIGs. 4A and 4B is a modification of the high-voltage integrated circuit device 100 according to the first embodiment of the invention, and is different from the semiconductor device according to the first embodiment of the invention in terms of the following point.
  • FIGs. 4A and 4B different from FIGs. 2A and 2B is as follows: in FIGs. 2A and 2B , the planar shape of the high-side separation layer 51 is formed in the ring-like shape surrounding the floating potential region 34, whereas, in FIGs. 4A and 4B , the planar shape thereof is formed so as to surround the drain of the high voltage n-channel MOSFET 62.
  • the floating region 5 may be connected to the diode separation layer 52, and the bootstrap diode Db may be formed in a region surrounded by the floating region 5 and the diode separation layer 52.
  • FIG. 5 is a circuit structural diagram in a case in which gate driver circuits (GDU-U and GDU-V driving the upper arm IGBTs of FIG. 10 ) and a level shift circuit (LSU) of FIG. 11 and a bootstrap diode (Db) are integrated into one chip.
  • FIG. 5 illustrates an upper arm output element Q1 (U phase) and a lower arm output element Q4 (X phase) that form a main circuit, diodes D1 and D4 connected in reverse parallel to the elements, and the bootstrap capacitor C1.
  • a junction of the upper arm output element Q1 and the lower arm output element Q4 is a midpoint terminal OUT of the main circuit, and the junction is connected to the U-OUT terminal 14 of the high-voltage integrated circuit device 100 and also connected to a load (not illustrated), such as a motor.
  • the U-OUT terminal 14 (an OUT terminal) is at intermediate potential and varies between the high potential-side potential VCC2H and the low potential-side potential VCC2L of the high voltage power supply VCC2 as the main circuit power supply.
  • IGBT an IGBT
  • another output element such as a MOSFET (a MOS type field effect transistor), a GTO thyristor (a gate turn-off thyristor), a thyristor, a SIT (a static induction transistor), or a SI (a static induction) thyristor.
  • MOSFET MOS type field effect transistor
  • GTO thyristor a gate turn-off thyristor
  • SIT a static induction transistor
  • SI static induction
  • An upper arm diode D1 (a free-wheeling diode) is connected in reverse parallel to the upper arm output element Q1
  • a lower arm diode D4 (a free-wheeling diode) is connected in reverse parallel to the lower arm output element Q4.
  • an output terminal U-GATE of the upper arm driver GDU-U of the HV gate driver IC is connected to a control electrode of the externally-attached upper arm output element Q1.
  • an output terminal X-GATE of a lower arm driver GDU-X of the HV gate driver IC is connected to a control electrode of the externally-attached lower arm output element Q4.
  • the upper arm driver GDU-U is a high-side circuit located in the floating potential region 34, and the lower arm driver GDU-X is a low-side circuit fixed at a low potential (ground potential).
  • the upper arm driver GDU-U includes an upper arm CMOS inverter, an upper arm buffer amplifier, and an upper arm control logic
  • the lower arm driver GDU-X includes a lower arm CMOS inverter, a lower arm buffer amplifier, and a lower arm control logic
  • the upper arm output element Q1 and the lower arm output element Q4 are driven by the upper arm driver GDU-U and the lower arm driver GDU-X to be each alternately turned ON/OFF.
  • the bootstrap circuit (the bootstrap diode Db and the bootstrap capacitor C1) in the alternate ON/OFF of the upper arm output element Q1 and the lower arm output element Q4
  • the bootstrap capacitor C1 is charged only in a period of time when the upper arm output element Q1 is OFF and the potential of the midpoint terminal OUT is reduced down to the ground potential, as described above.
  • an ON time of a low-side switch (the lower arm output element Q4) (or an OFF time of a high-side switch (the upper arm output element Q1)) needs to be set to long enough to completely replenish charge drawn from the bootstrap capacitor C1 by the upper arm driver GDU-U.
  • the bootstrap diode Db is a pn diode, and the cathode region 7 and the anode region 6 of the Db and the floating region 5 are formed in the epitaxial growth layer 2 above the cavity 3.
  • a thickness of the semiconductor layer obtained by adding the buried layer 50 on the cavity 3 and the epitaxial growth layer 2 is, for example, 14 ⁇ m. If the cavity 3 has a thickness of 6 ⁇ m or more, the weight of the epitaxial growth layer 2 above the cavity 3 can collapse the cavity 3. Thus, the thickness of the cavity 3 is preferably 6 ⁇ m or less.
  • the semiconductor substrate 1 to be used has a specific resistivity of about 250 to 400 ⁇ cm.
  • the buried layer 50 positioned beneath the cavity 3 and used also as a drain drift region of the high voltage n-channel MOSFET 62 is created in such a manner that an epitaxial growth layer having an epi thickness of about 2 to 10 ⁇ m is formed on the semiconductor substrate 1 or a diffusion depth Xj becomes about 2 to 10 ⁇ m from a surface of the semiconductor substrate 1 by performing a high temperature driving process at 1100 to 1200°C.
  • a mask oxide film is formed (thermal oxidation) on the semiconductor substrate 1 as a support substrate including the buried layer 50 formed thereon by the above method; patterning of trench holes is performed; and then trenches are etched by dry etching.
  • the mask oxide film is removed by wet etching, and annealing processing is performed under inert gas atmosphere (for example, hydrogen gas) at a high temperature of 1000 to 1200°C.
  • inert gas atmosphere for example, hydrogen gas
  • porous silicon may be formed by electrolytic etching or the like and annealing processing may be performed under inert gas atmosphere at high temperature to form the cavity 3.
  • the epitaxial growth layer 2 is formed.
  • the epitaxial growth layer 2 has an impurity concentration of about 1 ⁇ 10 14 to 1 ⁇ 10 16 /cm 3 .
  • each of the floating region 5 in contact with the cavity 3 the deep region 4 connected to the GND terminal 11, and the anode region 6 and the cathode region 7 of the bootstrap diode Db above the cavity 3, ion implantation of phosphorus and boron is performed by forming each mask.
  • Amounts of doses are as follows: the dose for the anode region 6 of the bootstrap diode Db is about 1 ⁇ 10 12 to 1 ⁇ 10 14 /cm 2 ; the dose for the cathode region 7 of the bootstrap diode Db is about 1 ⁇ 10 15 /cm 2 ; the dose for the floating region 5 is about 1 ⁇ 10 12 to 5 ⁇ 10 14 /cm 2 ; and the dose for the deep region 4 is 1 ⁇ 10 12 to 5 ⁇ 10 14 /cm 2 .
  • annealing process is performed at about 1100 to 1200°C for about 10 hours after ion implantation.
  • the floating region 5 allows suppression of leakage current by holes that flows from the anode region 6 of the bootstrap diode Db connected to the VDD terminal 12 to the semiconductor substrate 1 connected to the GND terminal 11.
  • the high-side separation layer 51 and the diode separation layer 52 can also be formed by simultaneously processing together with the floating region 5.
  • the anode region 6 and the cathode region 7 of the bootstrap diode Db may be diffused down to the cavity 3.
  • a gap is provided between the anode region 6 of the bootstrap diode Db, the floating region 5, and the deep region 4 so that these regions are not connected to each other.
  • the cap between the anode region 6 and the cathode region 7 of the bootstrap diode Db is set to about 100 ⁇ m
  • the gap between the anode region 6 and the floating region 5 is set to be a gap that is not punched through with a voltage (for example, about 15 V) of the VDD power supply 16.
  • the high voltage n-channel MOSFET 62 includes the source region 55 formed on a surface of the deep region 4, a gate electrode 53a arranged above the deep region 4 via the gate oxide film 37, and the drain contact region 57.
  • the drain drift region of the high voltage n-channel MOSFET 62 includes the epitaxial growth layer 2 between the floating region 5 and the deep region 4, the epitaxial growth layer 2 surrounded by the high-side separation layer 51 and the diode separation layer 52, and the buried layer 50.
  • the buried layer 50 can be used as the drain drift region to allow the high voltage n-channel MOSFET 62 as a level shift device to transmit a sufficient signal to the high-side CMOS circuit 33 (the logic circuit).
  • LOCOS as a field oxide film is formed between the diffusion regions on the surface of the epitaxial growth layer 2.
  • an interlayer insulating film as a silicon oxide film made of TEOS (tetraethoxy silane), BPSG (boron phosphorus glass), or the like and a passivation film as a silicon nitride film.
  • a phosphorus impurity may be injected to form the epitaxial growth layer 2 between the deep region 4 and the floating region 5 that become GNDp regions of FIG. 1 , the epitaxial growth layer 2 between the floating region 5 and the cathode region 7, and the epitaxial growth layer 2 surrounded by the high-side separation layer 51 and the diode separation layer 52.
  • annealing processing is performed at 1100 to 1200°C for about 10 hours to diffuse these n regions down to the depth of the cavity.
  • these n regions have a concentration of about 1 ⁇ 10 14 to 1 ⁇ 10 17 /cm 3 .
  • the deep region 4, the floating region 5, the high-side separation region 51, and the diode separation layer 52 of FIG. 1 are replaced by a p - -type epitaxial growth layer.
  • providing the floating region 5 allows suppression of leakage current by the holes to the semiconductor substrate 1 when charging the externally-attached bootstrap capacitor C1, so that the high-voltage integrated circuit device 100 having the gate driver circuits with small power consumption and high function can be achieved. Additionally, locating the bootstrap diode Db and the high voltage n-channel MOSFET 62 in the upper and lower directions of the cavity 3 can reduce an area for the HV gate driver IC, as well as there can be formed a bootstrap circuit that does not cause mutual influence between these devices and hardly malfunctions.
  • the cavity 3 may be partially formed in an island region (a belt-shaped ring region) of the bootstrap diode Db, so that there is little influence of the cavity 3 on warping of a wafer (the p - -type semiconductor substrate 1).
  • the insulating separation region is the cavity 3 of SON structure.
  • it may be an insulating film of SOI structure.
  • an insulating film of partial SOI structure that becomes an insulating separation region may be formed on the buried layer 50 of the semiconductor substrate 1, and the epitaxial growth layer 2 may be formed on the insulating film.
  • the insulating film of SOI structure as the insulating separation region is formed in the buried layer 50 and an n-type semiconductor layer including the epitaxial growth layer 2.
  • the oxide film needs to have a thickness of about 15 ⁇ m (calculated by assuming that the relative permittivity of the oxide film is 3.9) at a breakdown voltage of about 1500 V.
  • the thickness of the oxide film needs to be 4 times thicker than the cavity 3, production cost increases. Nevertheless, insulation effect is obtained, so that an oxide film may be usable instead of the cavity 3.
  • the cavity 3 can be formed merely by adding a trench hole formation step (mask oxidation, patterning, and trench etching) and a hydrogen annealing step, so that production cost can be reduced as compared to the use of an SOI substrate using an oxide film.
  • a trench hole formation step mask oxidation, patterning, and trench etching
  • a hydrogen annealing step so that production cost can be reduced as compared to the use of an SOI substrate using an oxide film.
  • Ecr represents critical electric field
  • d represents thickness of n - -type semiconductor layer
  • Tox represents thickness of dielectric layer
  • ⁇ si represents relative permittivity of silicon
  • ⁇ ox represents relative permittivity of dielectric
  • a relative permittivity ⁇ cavity of the cavity 3 corresponding to ⁇ ox is 1
  • Ecr is 3 ⁇ 10 5 (V/cm)
  • d is 10 ⁇ m
  • ⁇ si is 11.7.
  • T cavity 4 ⁇ m as a thickness of the cavity 3 corresponding to Tox is substituted
  • Vbr will be 1550 V.
  • the thickness of the cavity 3 becomes about 1/4 of the thickness of an oxide film when an SOI substrate is used.
  • the level shifter LSU and the bootstrap diode Db incorporated in the high-voltage integrated circuit device 100 are required to have a breakdown voltage of about 1500 V at minimum at a rated voltage of 1200 V, when considering specific resistance variation of the n - semiconductor layer (the epitaxial growth layer 2), thickness variation of the cavity 3, actual breakdown voltages of the power transistors Q1 and Q4 as the externally attached components, and the like. From the above formula (1), it can be seen that the breakdown voltage of the dielectric separation type high-voltage integrated circuit device can be raised merely by increasing the film thickness of the n - semiconductor layer (the epitaxial growth layer 2) or the dielectric layer. However, when the dielectric layer is the cavity 3, if the cavity 3 is formed to be thick, the cavity 3 is collapsed by the weight of the semiconductor layer above the cavity 3. Thus, the thickness of the cavity 3 is suitably about 4 to 6 ⁇ m.
  • FIGs. 6A and 6B are diagrams illustrating a depletion layer 90 generated when high voltage is applied to the cathode region 7 and the drain contact region 57 and the flows of carriers (electrons 91 and holes 92) when the high voltage n-channel MOSFET 62 and the bootstrap diode Db are turned ON, in which FIG. 6A is a diagram of the depletion layer, and FIG. 6B is a diagram illustrating the flows of the carriers.
  • a potential of the U-VCC terminal 13 is a potential obtained by adding a potential of the VDD terminal 12 to a potential of the U-OUT terminal 14.
  • the current I is divided into a current I1 that charges the bootstrap capacitor C1 and a current I2 that flows to the drain contact region 57 since the high voltage n-channel MOSFET 62 is ON.
  • the current 12 is small since it flows via the level shift resistor RL, and most of the current I flows as the current I1. Making the amount of the current I1 large allows quick charging of the bootstrap capacitor C1 whose voltage has been reduced due to discharging.
  • Providing the floating region 5, the cavity 3, and the diode separation layer 52 allows the prevention of the holes 92 injected from the anode region 6 from leaking to the semiconductor substrate 1. As a result, leakage current to the semiconductor substrate 1 can be suppressed.
  • the buried layer 50 as the drift region of the high voltage n-channel MOSFET 62 beneath a formation region 35 of the bootstrap diode Db, a part of an area occupied by the high voltage n-channel MOSFET 62 can be allocated to the bootstrap diode Db, so that the area of the bootstrap diode Db can be increased.
  • the large current I1 can be flown through the bootstrap diode Db, whereby the bootstrap capacitor C1 can be quickly charged, as mentioned above. This allows achievement of a high frequency inverter device.
  • the cavity 3 of SON structure is formed as the insulating separation region in the buried layer 50 of the semiconductor substrate 1; the epitaxial growth layer 2 above the cavity 3 is used as the drift region of the bootstrap diode Db; and the buried layer 50 beneath the cavity 3 is used as the drain drift region of the high voltage n-channel MOSFET 62 as the level shift device.
  • the bootstrap diode Db and the high voltage n-channel MOSFET 62 each are element-isolated by the cavity 3 and the p-type diffusion layers (the p-type floating region 5 and the p-type diode separation layer 52), whereby leakage current by the holes to the semiconductor substrate 1 in charging the bootstrap capacitor C1 can be suppressed.
  • the high voltage n-channel MOSFET 62 is located beneath the bootstrap diode Db, it is unnecessary to locate the high voltage n-channel MOSFET 62 also in another region, thus allowing suppression of increase in chip area.
  • a high-voltage integrated circuit device 200 according to a second embodiment of the present invention is different from the high-voltage integrated circuit device 100 according to the first embodiment of the invention in terms of the following structure.
  • the p-type high-side separation layer 51 and the p-type diode separation layer 52 are in the floating state.
  • a p + -type contact region 51a is formed at an upper part of the p-type high-side separation layer 51
  • a p + -type contact region 52a is formed at an upper part of the p-type diode separation layer 52, respectively.
  • the U-OUT terminal 14 is connected to the contact regions 51a and 52a. This structure allows the suppression of malfunction of the CMOS circuit 33 when a negative voltage surge is applied to the U-OUT terminal 14.
  • the holes 92 are injected into the high-side drive circuit (the CMOS circuit 33) from the anode region 6 of the bootstrap diode Db via the p-type high-side separation layer 51 and the p-type diode separation layer 52, whereby the CMOS circuit 33 may malfunction.
  • the p + -type contact region 51a is formed at the upper part of the p-type high-side separation layer 51 and the p + -type contact region 52a is formed at the upper part of the p-type diode separation layer 52. Connecting these contact regions 51a and 52a to the U-OUT terminal 14 allows the holes 92 that have entered the p-type high-side separation layer 51 and the p-type diode separation layer 52, as illustrated in FIG. 7 , to be drawn out from the U-OUT terminal 14 that is at a lower potential than the ground potential.
  • the p-type base region 4a is formed at the upper part of the p-type deep region 4, as illustrated in FIG. 1 .
  • the p-type base region 4a is not formed, and the n + -type source region 55 is formed at the upper part of the deep region 4. Accordingly, there may be cases where the p-type base region 4a is not formed.
  • separately forming the base region 4a and the deep region 4 makes it easier to control the impurity concentration of the backgate of the high voltage n-channel MOSFET 62.
  • a high-voltage integrated circuit device 300 according to a third embodiment of the present invention is different from the high-voltage integrated circuit device 100 according to the first embodiment of the invention described above in terms of the following structure.
  • the n + -type drain contact region 57 of the high voltage n-channel MOSFET 62 is provided in the epitaxial growth layer 2 between the high-side separation layer 51 and the diode separation layer 52, and the cavity 3 is located beneath the high-side separation layer 51 and the floating potential region 34.
  • the high-side separation layer 51 and the diode separation layer 52 are not provided.
  • the structure of a high voltage n-channel MOSFET 63 is different from that of the high voltage n-channel MOSFET 62 of the first embodiment.
  • the cavity 3 is not provided beneath the floating potential region 34.
  • a distance L between the drain contact region 57 and each of the cathode region 7 of the bootstrap diode Db and the n + -type contact region 20 of the p-channel MOSFET 31 is sufficiently extended.
  • the holes 92 injected from the anode region 6 of the bootstrap diode Db when negative surge is applied to the U-OUT terminal 14 are drawn out from the cathode region 7 and the drain contact region 57, thereby suppressing injection of the holes 92 into the floating potential region 34.
  • a resistance value of a parasitic resistance RR1 between the drain contact region 57 and the n + -type contact region 20 needs to be set larger than a resistance value of the level shift resistor RL.
  • the distance between the drain contact region 57 and the n + -type contact region 20 is preferably 100 ⁇ m or more, considering the above-mentioned resistance condition.
  • a p-type diffusion layer may be located in an upper part of the epitaxial growth layer 2 to raise the resistance value of the parasitic resistance RR1.
  • the distance L is set to be larger than a diffusion length of the holes 92 that are injected from the anode region 6 in order not to allow the holes 92 injected from the anode region 6 to enter the cathode region 7 and the drain contact region 57 and then enter the contact region 20 and the p + -type source region 18 on the high-side.
  • the distance L is set to be larger than the diffusion length of the holes 92, the holes 92 as indicated by a dotted line disappear due to recombination, before reaching the contact region 20 and the p + -type source region 18.
  • the diffusion length of the holes 92 is about several 10 ⁇ m.
  • a high-voltage integrated circuit device 400 according to the fourth embodiment of the present invention is different from the high-voltage integrated circuit device 100 of the first embodiment described above in terms of the following structure.
  • the high-voltage integrated circuit device 100 of the first embodiment 100 has the structure in which the high-side separation layer 51 is provided between the drain contact region 57 of the high voltage n-channel MOSFET 62 and the floating potential region 34, and the cavity 3 is located beneath the high-side separation layer 51 and the floating potential region 34.
  • the high-side separation layer 51 is not provided, and the cavity 3 is also not provided beneath the floating potential region 34.
  • the distance L between the drain contact region 57 and the contact region 20 is sufficiently extended. In this manner, sufficiently extending the distance L allows the suppression of malfunction of the level shift circuit.
  • the resistance value of the parasitic resistance RR1 between the drain contact region 57 and the contact region 20 needs to be larger than the resistance value of the level shift resistor RL.
  • the distance between the drain contact region 57 and the contact region 20 is preferably 100 ⁇ m or more, considering the above-mentioned resistance condition.
  • a p-type diffusion layer may be located in an upper part of the epitaxial growth layer 2 to raise the resistance value of the parasitic resistance RR1.
  • the semiconductor devices according to the first to the fourth embodiments of the present invention have been described with reference to the case of using the silicon semiconductor substrate as a semiconductor substrate.
  • the invention is not limited thereto and applicable to semiconductor devices using, for example, a semiconductor substrate made of silicon carbide (SiC), gallium nitride (GaN), or the like.
  • the semiconductor device according to the present invention can suppress leakage current by the holes that flows to a substrate side in forward biasing of the bootstrap diode, and can increase charging current for the bootstrap capacitor, as well as can suppress increase in chip area. Accordingly, the invention is useful for semiconductor devices including a high voltage MOSFET and a bootstrap diode on the same substrate.

Claims (15)

  1. Halbleitervorrichtung umfassend:
    ein p-Halbleitersubstrat (1);
    eine eingebettete n-Schicht (50), die auf dem Halbleitersubstrat (1) gebildet ist;
    eine n-Hableiterschicht (2), die auf der eingebetteten Schicht (50) gebildet ist;
    eine Schwebepotenzialregion (34), die in einem Teil der Halbleiterschicht (2) vorgesehen ist;
    eine erste p-Trennregion (4), die den Teil der Halbleiterschicht (2) umgibt, in dem die Schwebepotenzialregion (34) vorgesehen ist, und die erste Trennregion (4) in Kontakt mit dem Halbleitersubstrat (1) ist und von der Schwebepotenzialregion (34) beabstandet ist, sodass sie in einer ringartigen Form gebildet ist;
    eine Diode (Db); und;
    eine zweite p-Trennregion (5), die von der ersten Trennregion (4) beabstandet ist, sodass sie, in einer ringartigen Form, eine Region umgibt, in der sich die Diode (Db) befindet;
    dadurch gekennzeichnet, dass
    die zweite p-Trennregion (5) von einer Fläche der Halbleiterschicht (2) unter die Halbleiterschicht (2) reicht; und
    dass die Halbleitervorrichtung ferner umfasst:
    ein erste isolierende Trennregion (3), die unter der Halbleiterschicht (2) zwischen der Schwebepotenzialregion (34) und der ersten Trennregion (4) vorgesehen ist, wobei die Diode (Db) über der ersten isolierenden Trennregion (3) gebildet ist; und
    einen Transistor, wobei der Transistor ein n-Kanal-Hochspannungs-MOSFET (62) ist, wobei der n-Kanal-Hochspannungs-MOSFET (62) umfasst:
    eine n-Sourceregion (55), die in einem oberen Teil der ersten Trennregion (4) gebildet ist;
    eine n-Drainkontaktregion (57), die in einem oberen Teil der Halbleiterschicht (2) zwischen einer Kathodenregion (7) der Diode (Db) und der Schwebepotenzialregion (34) gebildet ist; und
    eine Draindriftregion einschließlich der eingebetteten n-Schicht (50) unter der ersten isolierenden Trennregion (3).
  2. Halbleitervorrichtung nach Anspruch 1, wobei die Diode umfasst:
    eine p-Anodenregion (6), die von der zweiten Trennregion (5) beabstandet ist und in einem oberen Teil der Halbleiterschicht (2) über der ersten isolierenden Trennregion (3) gebildet ist; und
    die Kathodenregion (7) vom Typ n, die von der Anodenregion (6) und der Schwebepotenzialregion (34) beabstandet ist, wobei sich die Kathodenregion (7) zwischen der Anodenregion (6) und der Schwebepotenzialregion (34) befindet und in einem oberen Teil der Halbleiterschicht (2) über der ersten isolierenden Trennregion (3) gebildet ist.
  3. Halbleitervorrichtung nach Anspruch 2, wobei der Transistor ferner eine Gateelektrode (53) umfasst, die mittels eines Gateisolierfilms über der ersten Trennregion (4) gebildet ist, die sich zwischen der Sourceregion (55) und der Halbleiterschicht (2) befindet.
  4. Halbleitervorrichtung nach Anspruch 3, wobei eine Logikschaltung (33) in der Schwebepotenzialregion (34) integriert ist.
  5. Halbleitervorrichtung nach Anspruch 3, ferner umfassend eine dritte p-Trennregion (52), welche die erste isolierende Trennregion (3) von einer oberen Fläche der Halbleiterschicht (2) zwischen der Kathodenregion (7) und der Drainkontaktregion (57) erreicht.
  6. Halbleitervorrichtung nach Anspruch 4, ferner umfassend eine zweite isolierende Trennregion (3), die unter der Halbleiterschicht (2) vorgesehen ist, um einen Bereich unter der Logikschaltung (33) abzudecken, und eine vierte p-Trennregion (51), welche die zweite isolierende Trennregion (3) von der Fläche der Halbleiterschicht (2) zwischen der Drainkontaktregion (57) und der Schwebepotenzialregion (34) erreicht.
  7. Halbleitervorrichtung nach Anspruch 5, wobei die dritte Trennregion (52) angepasst ist, mit einer Niedrigpotenzialseite einer Stromversorgung der Logikschaltung (33) elektrisch verbunden werden.
  8. Halbleitervorrichtung nach Anspruch 6, wobei die vierte Trennregion (51) angepasst ist, mit einer Niedrigpotenzialseite einer Stromversorgung der Logikschaltung (33) elektrisch verbunden werden.
  9. Halbleitervorrichtung nach Anspruch 6, ferner umfassend eine dritte p-Trennregion (52), welche die erste isolierende Trennregion (3) von einer oberen Fläche der Halbleiterschicht (2) zwischen der Kathodenregion (7) und der Drainkontaktregion (57) erreicht, wobei die zweite Trennregion (5), die dritte Trennregion (52), die vierte Trennregion (51), die Anodenregion (6) und die Kathodenregion (7) geschlossene ringartige ebene Formen aufweisen.
  10. Halbleitervorrichtung nach Anspruch 6, wobei die zweite isolierende Trennregion (3) ein Hohlraum ist.
  11. Halbleitervorrichtung nach Anspruch 1, wobei die erste isolierende Trennregion (3) ein Hohlraum ist.
  12. Halbleitervorrichtung nach Anspruch 2, wobei ein Abstand zwischen der Drainkontaktregion (57) und der Schwebepotenzialregion (34) länger ist als eine Diffusionslänge von Löchern, wenn sie von der Anodenregion (6) eingeführt werden.
  13. Halbleitervorrichtung nach Anspruch 1, umfassend eine Leiterbahn, welche die Kathodenregion (7) und die Schwebepotenzialregion (34) verbindet.
  14. Halbleitervorrichtung nach Anspruch 1, wobei die eingebettete Schicht (50) eine Diffusionsschicht umfasst, die in einem oberen Teil des Halbleitersubstrats (1) gebildet ist, und die Halbleiterschicht (2) eine Epitaxialwachstumsschicht umfasst, die auf der eingebetteten Schicht (50) gebildet ist.
  15. Halbleitervorrichtung nach Anspruch 1, wobei die eingebettete Schicht (50) eine erste Epitaxialwachstumsschicht umfasst, die auf dem Halbleitersubstrat (1) gebildet ist, und die Halbleiterschicht (2) eine zweite Epitaxialwachstumsschicht umfasst, die auf der ersten Epitaxialwachstumsschicht gebildet ist.
EP14811117.2A 2013-06-14 2014-06-06 Halbleiterbauelement Active EP3010042B1 (de)

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PCT/JP2014/003022 WO2014199608A1 (ja) 2013-06-14 2014-06-06 半導体装置

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US10002961B2 (en) 2018-06-19
CN105074922A (zh) 2015-11-18
JP5994939B2 (ja) 2016-09-21
JPWO2014199608A1 (ja) 2017-02-23
CN105074922B (zh) 2018-07-03
US20160056282A1 (en) 2016-02-25
EP3010042A1 (de) 2016-04-20
WO2014199608A1 (ja) 2014-12-18

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