CN111415932B - 高压自举二极管复合器件结构 - Google Patents

高压自举二极管复合器件结构 Download PDF

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CN111415932B
CN111415932B CN202010236345.2A CN202010236345A CN111415932B CN 111415932 B CN111415932 B CN 111415932B CN 202010236345 A CN202010236345 A CN 202010236345A CN 111415932 B CN111415932 B CN 111415932B
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CN111415932A (zh
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乔明
李贺珈
袁章亦安
张波
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University of Electronic Science and Technology of China
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Abstract

本发明提出一种在节省芯片面积、保证低泄漏电流、不额外添置控制电路的情况下，满足高耐压特性的高压自举二极管复合器件结构，所述复合器件可有效代替高压栅驱动芯片中的自举二极管，实现和优化自举二极管的功能。该复合器件由高压JFET和二极管组成，可用于高压栅驱动电路高侧电路的电平位移模块中，其中JFET源极与二极管阴极通过金属相连，由此形成高压自举二极管复合器件。版图布局方面，该复合器件与用于电平位移的分区RESURF结构或自屏蔽结构的LDMOS组合形成高侧电路环岛，与岛内的高压电路形成高侧电路，共同控制高侧功率晶体管的开启与关断。

Description

高压自举二极管复合器件结构
技术领域
本发明属于功率半导体器件技术领域，涉及一种用于替代高压栅驱动电路自举二极管的复合器件结构。
背景技术
功率半导体器件因其开关速率快、承受耐压高等优良特性，逐渐栖身于电子制造业核心器件的行列，功率场效应晶体管在实现高速开关方面也备受青睐，而该类器件的控制电路，如半桥式栅级驱动电路中，自举模块有效解决了高低压部分电路的兼容问题。该模块由一个自举二极管和自举电容组成，其中自举二极管的性能对于整个驱动电路性能至关重要，单纯的片外连接二极管会增加芯片成本，而片内二极管集成的方案，会产生由阳极到衬底的泄漏电流，增大功耗；目前业界对上述问题的解决方案，主要有基于高压MOSFET同步整流器结构的二极管模拟电路、以及单片集成二极管与结型场效应晶体管的JFET夹断自举二极管方案，不同程度优化了自举功能，而后者相较于前者，由于不需要额外增设控制电路，可以节省一部分芯片面积，但在耐高压方面，前者性能则相对出色。总而言之，目前基于传统自举二极管实现方式提出的优化方案，在泄漏电流(Leakage current)、击穿电压(Breakdown voltage，BV)、器件尺寸、制造成本方面的优化还有很大的上升空间。
发明内容
本发明主要解决上述问题中泄漏电流、高耐压要求等问题，提出一种在节省芯片面积保证低泄漏电流、不额外添置控制电路的情况下，满足高耐压特性的复合器件结构，所述复合器件有效代替高压栅驱动芯片中的自举二极管，实现和优化自举二极管的功能。
为实现上述发明目的，本发明技术方案如下：
一种高压自举二极管复合器件结构，所述复合器件包括高压JFET和二极管器件，高压JFET源极与二极管阴极通过金属相连，由此形成可以替代传统高压自举二极管的复合器件。
作为优选方式，所述复合器件的版图布局，高压JFET器件1和二极管器件2与用于电平位移的分区RESURF结构LDMOS器件4组合成高侧电路环岛，与岛内高压电路3共同构成高侧电路。
作为优选方式，所述复合器件的版图布局，高压JFET器件1和二极管器件2与用于电平位移的自屏蔽结构LDMOS器件5组合成高侧电路环岛，与岛内高压电路3共同构成高侧电路。
作为优选方式，所述高侧电路环岛，除LDMOS所在边以外，均用作高压JFET的版图布局；或只选择某一条或某两条边作为JFET，其余作为隔离结构。
作为优选方式，所述复合器件包含高压JFET器件1和二极管器件2；所述高压JFET器件1中，元胞结构做在P型衬底6上，内部包含N型外延层7，所述N型外延层7包含由JFET漏极注入N+区域101与JFET漏极注入N+区域101上方JFET漏极金属113组成的漏极，JFET源极注入N+区域102与JFET源极注入N+区域102上方JFET源极金属117组成的源极，而在JFET源极注入N+区域102两侧的第二场氧化层104和第三场氧化层105之间，栅氧化层115、栅极多晶硅114以及栅极金属116形成器件栅极，栅极金属116在栅极多晶硅114上方，栅极多晶硅114在栅氧化层115上方；此外，JFET漏极注入N+区域101左侧第一场氧化层103下方由第一P型埋层PBL109、第一P型注入P-TYPE108、第一P型阱区P-WELL107形成对通隔离结构，第三场氧化层105、第四场氧化层106间有第二P型埋层112、第二P型注入P-TYPE111、第二P型阱区P-WELL110形成的对通隔离结构，其中第二P型埋层112延长至第二场氧化层104下方，保证N型外延区域7的夹断；
所述二极管器件2中，元胞结构做在P型衬底6上，内部包含N型外延层7，N型埋层NBL214贯穿P型衬底6和N型外延层7，所述N型外延层7包含阴极、阳极P+区域202、第四P型阱区P-WELL210、阳极，所述阴极由阴极N+区域201与阴极N+区域201上方的JFET源极金属117组成，第四P型阱区P-WELL210包含阳极P+区域202，阳极由第四P型阱区P-WELL210和阳极P+区域202上方的阳极金属215组成，阴极、阳极之间有第七场氧化层205；此外，第五场氧化层203、第六场氧化层204下方由第三P型埋层PBL209、第三P型注入P-TYPE208、第三P型阱区P-WELL207形成对通隔离结构，第八场氧化层206下方也有由第四P型埋层PBL213、第四P型注入P-TYPE212、第五P型阱区P-WELL211形成的对通隔离结构。
作为优选方式，所述高压JFET器件1，由第二P型埋层112、第二P型注入P-TYPE111、第二P型阱区P-WELL110形成的对通隔离结构中，第二P型埋层112部分在Z方向上做成非连续结构，调整JFET夹断电压。
作为优选方式，所述高压JFET器件1，由第二P型埋层112、第二P型注入P-TYPE111、第二P型阱区P-WELL110形成的对通隔离结构种中，第二P型注入P-TYPE111部分在X方向上延伸至与第二P型埋层112末端对齐，调整JFET夹断电压。
作为优选方式，所述高压JFET器件1，由第二P型埋层112、第二P型注入P-TYPE111、第二P型阱区P-WELL110形成的对通隔离结构种中，第二P型埋层112部分在X方向的长度与第二P型阱区P-WELL110一致。
和现有技术相比，本发明的有益效果为：
无需增加额外控制电路，节省芯片空间，又易于应用。复合器件结构能有效减小流向衬底的泄漏电流，降低功耗；此外，复合器件中不同耐压能力的二极管与JFET的组合方式，使该复合器件适用于高、中、低压栅驱动电路。
附图说明：
图1为典型片外连接自举二极管的栅驱动电路示意图；
图2为本发明提出的复合器件与分区(Divided)RESURF结构LDMOS组成的高侧隔离环岛与岛内高压电路区域的关键结构版图布局示意图；
图3为本发明提出的复合器件与自屏蔽(Self Shielded)结构LDMOS组成的高侧隔离环岛与岛内高压电路区域的关键结构版图布局示意图；
图4为实施例1的剖面结构示意图；
图5为实施例2的剖面结构示意图；
图6为实施例3的剖面结构示意图；
其中，1为高压JFET器件，2为二极管器件，3为岛内高压电路，4为分区RESURF结构LDMOS器件，5为自屏蔽结构LDMOS器件，6为P型衬底，7为N型外延层，101为JFET漏极注入N+区域，102为JFET源极注入N+区域，103为第一场氧化层，104为第二场氧化层，105为第三场氧化层，106为第四场氧化层，107为第一P型阱区P-WELL，108为第一P型注入P-TYPE，109为第一P型埋层PBL，110为第二P型阱区P-WELL，111为第二P型注入P-TYPE，112为第二P型埋层，113为JFET漏极金属，114为栅极多晶硅，115为栅氧化层，116为栅极金属，117为JFET源极金属；201为阴极N+区域，202为阳极P+区域，203为第五场氧化层，204为第六场氧化层，205为第七场氧化层，206为第八场氧化层，207为第三P型阱区P-WELL，208为第三P型注入P-TYPE，209为第三P型埋层PBL，210为第四P型阱区P-WELL，211为第五P型阱区P-WELL，212为第四P型注入P-TYPE，213为第四P型埋层PBL，214为N型埋层NBL，215为阳极金属。
具体实施方式：
实施例1：
本实施例提供一种高压自举二极管复合器件结构，所述复合器件包括高压JFET和二极管器件，高压JFET源极与二极管阴极通过金属相连，由此形成可以替代传统高压自举二极管的复合器件。
在版图布局方面，高压JFET器件1被P型隔离P-Isolation包围，使JFET形成类环状结构。同时，为了便于与二极管连接，令JFET外环一侧为JFET源极区域Source，内环一侧为JFET漏极区域Drain。二极管2也由P型隔离包围，阴极Cathode通过金属与JFET1源极相连形成复合器件，该复合器件可与用于电平位移的两个Divided RESURF结构或Self Shielded结构的LDMOS4组合成高侧电路环岛，与岛内的高压电路3共同控制高侧功率晶体管的开启与关断。
所述复合器件的版图布局，高压JFET器件1被P型隔离P-Isolation包围，使JFET形成类环状结构；同时，为了便于与二极管连接，令JFET外环一侧为JFET源极区域Source，内环一侧为JFET漏极区域Drain。二极管2也由P型隔离包围，阴极Cathode通过金属与JFET1源极相连形成复合器件，与用于电平位移的分区RESURF结构LDMOS器件4组合成高侧电路环岛，与岛内高压电路3共同构成高侧电路。此外，分区RESURF结构LDMOS器件4部分可用自屏蔽结构LDMOS器件5替代。
所述高侧电路环岛，除LDMOS所在边以外，均用作高压JFET的版图布局；或只选择某一条或某两条边作为JFET，其余作为隔离结构。
所述高压JFET器件1中，元胞结构做在P型衬底6上，内部包含N型外延层7，所述N型外延层7包含由JFET漏极注入N+区域101与JFET漏极注入N+区域101上方JFET漏极金属113组成的漏极，JFET源极注入N+区域102与JFET源极注入N+区域102上方JFET源极金属117组成的源极，而在JFET源极注入N+区域102两侧的第二场氧化层104和第三场氧化层105之间，栅氧化层115、栅极多晶硅114以及栅极金属116形成器件栅极，栅极金属116在栅极多晶硅114上方，栅极多晶硅114在栅氧化层115上方；此外，JFET漏极注入N+区域101左侧第一场氧化层103下方由第一P型埋层PBL109、第一P型注入P-TYPE108、第一P型阱区P-WELL107形成对通隔离结构，第三场氧化层105、第四场氧化层106间有第二P型埋层112、第二P型注入P-TYPE111、第二P型阱区P-WELL110形成的对通隔离结构，其中第二P型埋层112延长至第二场氧化层104下方，保证N型外延区域7的夹断；
所述二极管器件2中，元胞结构做在P型衬底6上，内部包含N型外延层7，N型埋层NBL214贯穿P型衬底6和N型外延层7，所述N型外延层7包含阴极、阳极P+区域202、第四P型阱区P-WELL210、阳极，所述阴极由阴极N+区域201与阴极N+区域201上方的JFET源极金属117组成，第四P型阱区P-WELL210包含阳极P+区域202，阳极由第四P型阱区P-WELL210和阳极P+区域202上方的阳极金属215组成，阴极、阳极之间有第七场氧化层205；此外，第五场氧化层203、第六场氧化层204下方由第三P型埋层PBL209、第三P型注入P-TYPE208、第三P型阱区P-WELL207形成对通隔离结构，第八场氧化层206下方也有由第四P型埋层PBL213、第四P型注入P-TYPE212、第五P型阱区P-WELL211形成的对通隔离结构。
进一步地，所述高压JFET器件1，由第二P型埋层112、第二P型注入P-TYPE111、第二P型阱区P-WELL110形成的对通隔离结构中，第二P型埋层112部分在Z方向上做成非连续结构，调整JFET夹断电压。
实施例2：
如图5所示，本实施例和实施例1的区别在于：所述高压JFET器件1，由第二P型埋层112、第二P型注入P-TYPE111、第二P型阱区P-WELL110形成的对通隔离结构种中，第二P型注入P-TYPE111部分在X方向上延伸至与第二P型埋层112末端对齐，调整JFET夹断电压。
实施例3：
如图6所示，本实施例和实施例1的区别在于：所述高压JFET器件1，由第二P型埋层112、第二P型注入P-TYPE111、第二P型阱区P-WELL110形成的对通隔离结构种中，第二P型埋层112部分在X方向的长度与第二P型阱区P-WELL110一致。

Claims (6)

1.一种高压自举二极管复合器件结构，其特征在于：所述复合器件包括高压JFET和二极管器件，高压JFET源极与二极管阴极通过金属相连，由此形成可以替代传统高压自举二极管的复合器件；
所述复合器件的版图布局，高压JFET器件（1）和二极管器件（2）与用于电平位移的分区RESURF结构LDMOS器件（4）组合成高侧电路环岛，高侧电路环岛与岛内高压电路（3）共同构成高侧电路；
或者所述复合器件的版图布局，高压JFET器件（1）和二极管器件（2）与用于电平位移的自屏蔽结构LDMOS器件（5）组合成高侧电路环岛，高侧电路环岛与岛内高压电路（3）共同构成高侧电路。
2.根据权利要求1所述的高压自举二极管复合器件结构，其特征在于：所述高侧电路环岛，除LDMOS所在边以外，均用作高压JFET的版图布局；或只选择某一条或某两条边作为JFET，其余作为隔离结构。
3.根据权利要求1所述的高压自举二极管复合器件结构，其特征在于：所述复合器件包含高压JFET器件（1）和二极管器件（2）；
所述高压JFET器件（1）中，元胞结构做在P型衬底（6）上，内部包含N型外延层（7），所述N型外延层（7）包含由JFET漏极注入N+区域（101）与JFET漏极注入N+区域（101）上方JFET漏极金属（113）组成的漏极，JFET源极注入N+区域（102）与JFET源极注入N+区域（102）上方JFET源极金属（117）组成的源极，而在JFET源极注入N+区域（102）两侧的第二场氧化层（104）和第三场氧化层（105）之间，栅氧化层（115）、栅极多晶硅（114）以及栅极金属（116）形成器件栅极，栅极金属（116）在栅极多晶硅（114）上方，栅极多晶硅（114）在栅氧化层（115）上方；此外，JFET漏极注入N+区域（101）左侧第一场氧化层（103）下方由第一P型埋层PBL（109）、第一P型注入P-TYPE（108）、第一P型阱区P-WELL（107）形成对通隔离结构，第三场氧化层（105）、第四场氧化层（106）间有第二P型埋层（112）、第二P型注入P-TYPE（111）、第二P型阱区P-WELL（110）形成的对通隔离结构，其中第二P型埋层（112）延长至第二场氧化层（104）下方，保证N型外延层（7）的夹断；
所述二极管器件（2）中，元胞结构做在P型衬底（6）上，内部包含N型外延层（7），N型埋层NBL（214）贯穿P型衬底（6）和N型外延层（7），所述N型外延层（7）包含阴极、阳极P+区域（202）、第四P型阱区P-WELL（210）、阳极，所述阴极由阴极N+区域（201）与阴极N+区域（201）上方的JFET源极金属（117）组成，第四P型阱区P-WELL（210）包含阳极P+区域（202），阳极由第四P型阱区P-WELL（210）和阳极P+区域（202）上方的阳极金属（215）组成，阴极、阳极之间有第七场氧化层（205）；此外，第五场氧化层（203）、第六场氧化层（204）下方由第三P型埋层PBL（209）、第三P型注入P-TYPE（208）、第三P型阱区P-WELL（207）形成对通隔离结构，第八场氧化层（206）下方也有由第四P型埋层PBL（213）、第四P型注入P-TYPE（212）、第五P型阱区P-WELL（211）形成的对通隔离结构。
4.根据权利要求3所述的高压自举二极管复合器件结构，其特征在于：所述高压JFET器件（1），由第二P型埋层（112）、第二P型注入P-TYPE（111）、第二P型阱区P-WELL（110）形成的对通隔离结构中，第二P型埋层（112）部分在Z方向上做成非连续结构，调整JFET夹断电压。
5.根据权利要求3所述的高压自举二极管复合器件结构，其特征在于：所述高压JFET器件（1），由第二P型埋层（112）、第二P型注入P-TYPE（111）、第二P型阱区P-WELL（110）形成的对通隔离结构种中，第二P型注入P-TYPE（111）部分在X方向上延伸至与第二P型埋层（112）末端对齐，调整JFET夹断电压。
6.根据权利要求3所述的高压自举二极管复合器件结构，其特征在于：所述高压JFET器件（1），由第二P型埋层（112）、第二P型注入P-TYPE（111）、第二P型阱区P-WELL（110）形成的对通隔离结构种中，第二P型埋层（112）部分在X方向的长度与第二P型阱区P-WELL（110）一致。
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