JP2022043141A - P-nバイモーダルパワーデバイスのための統合されたハイサイドドライバ - Google Patents
P-nバイモーダルパワーデバイスのための統合されたハイサイドドライバ Download PDFInfo
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- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 9
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 238000009792 diffusion process Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 4
- 102000004129 N-Type Calcium Channels Human genes 0.000 abstract description 2
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- 239000007943 implant Substances 0.000 description 7
- 230000008901 benefit Effects 0.000 description 6
- FAPWRFPIFSIZLT-UHFFFAOYSA-M Sodium chloride Chemical compound [Na+].[Cl-] FAPWRFPIFSIZLT-UHFFFAOYSA-M 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 108091006146 Channels Proteins 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
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- 238000011960 computer-aided design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000001802 infusion Methods 0.000 description 1
- 238000013101 initial test Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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Abstract
Description
Claims (19)
- 集積回路(IC)チップであって、
バイモーダル(bimodal)パワーN-P-横方向拡散金属酸化物半導体(LDMOS)デバイスであって、前記N-P-LDMOSデバイスのNゲートが、入力信号を受け取るように結合される、前記N-P-LDMOSデバイス、及び
前記入力信号を受け取り、制御信号を前記N-P-LDMOSデバイスのP-ゲートドライバに提供するように結合される、レベルシフタ、
を含む、ICチップ。 - 請求項1に記載のICチップであって、
前記入力信号が低電圧信号であり、前記制御信号が高電圧信号である、ICチップ。 - 請求項2に記載のICチップであって、
前記P-ゲートドライバが、前記N-P-LDMOSデバイスのドレインボンドパッド領域において集積される、ICチップ。 - 請求項3に記載のICチップであって、
前記レベルシフタが、第1の制御信号を受け取るように結合されるゲートを有するN-LDMOSトランジスタを含む、ICチップ。 - 請求項4に記載のICチップであって、
前記P-ゲートドライバが、
前記N-LDMOSトランジスタの前記ドレインと前記N-P-LDMOSデバイスのドレインとの間に結合される抵抗器、及び
前記抵抗器の第1及び第2の端子間に結合されるダイオード、
を含む、ICチップ。 - 請求項5に記載のICチップであって、
前記N-P-LDMOSデバイスのPゲートが、前記抵抗器と前記N-LDMOSトランジスタとの間のポイントに結合される、ICチップ。 - 請求項6に記載のICチップであって、
電流源が、前記N-LDMOSトランジスタのソースとVSSとの間に結合される、ICチップ。 - 請求項7に記載のICチップであって、
前記電流源がオフチップである、ICチップ。 - 請求項7に記載のICチップであって、
VSSが負の電圧である、ICチップ。 - 請求項6に記載のICチップであって、
前記N-LDMOSトランジスタが、前記バイモーダルパワーN-P-LDMOSデバイスに埋め込まれ、前記バイモーダルパワーN-P-LDMOSデバイスから所与の電圧だけ絶縁される、ICチップ。 - 請求項10に記載のICチップであって、
前記所定の電圧が20ボルトである、ICチップ。 - 単一チップ上に形成される、N-P横方向ダブル拡散金属酸化物半導体(LDMOS)デバイス及び制御回路であって、前記N-P-LDMOSデバイス及び制御回路が、
外側ループを形成する、前記N-P-LDMOSデバイスのためのソース及びN-ゲートであって、前記外側ループが、前記外側ループから内方に延びる第1のフィンガー、及び前記外側ループの第1及び第2の端部間の第1のギャップを含み、前記第1のギャップが前記第1のフィンガーとは反対に置かれる、前記ソース及び前記N-ゲート、
前記外側ループ内に囲まれる内側ループを形成する、前記N-P-LDMOSデバイス
のためのドレイン及びP-ゲートであって、前記内側ループが、前記内側ループから外方に延在し、前記内側ループの第2のフィンガーと前記外側ループの前記第1のフィンガーとの間の導通チャネルを形成する前記第2のフィンガーを含み、前記内側ループが更に、前記内側ループの第1及び第2の端部間の第2のギャップを含み、前記第2のギャップが前記第2のフィンガーとは反対に置かれる、前記ドレイン及び前記P-ゲート、及び
前記第1のギャップに位置するソース及びN-ゲートと前記第2のギャップに位置するドレインとを含むN-LDMOSトランジスタ、
を含み、
前記N-LDMOSトランジスタのドレインが、前記内側ループ内に位置する前記N-P-LDMOSデバイスのP-ゲートパッドに結合され、前記N-LDMOSトランジスタのゲートが、前記N-P-LDMOSデバイスの前記N-ゲートを制御するため信号入力を受け取るように結合され、前記N-LDMOSトランジスタのソースが、下側レール及び負の電圧の一方に結合される、N-P-LDMOSデバイス及び制御回路。 - 請求項12に記載のN-P-LDMOSデバイス及び制御回路であって、
前記P-ゲートパッドが更に、前記内側ループ内に形成される抵抗器を介して前記N-P-LDMOSデバイスのドレインパッドに結合される、N-P-LDMOSデバイス及び制御回路。 - 請求項13に記載のN-P-LDMOSデバイス及び制御回路であって、
前記P-ゲートパッドが更に、前記内側ループ内に形成されるダイオードを介して前記N-P-LDMOSデバイスの前記ドレインパッドに結合される、N-P-LDMOSデバイス及び制御回路。 - 請求項14に記載のN-P-LDMOSデバイス及び制御回路であって、
前記N-LDMOSトランジスタの前記ソースが、電流源を介して前記下側レール及び前記負の電圧の前記一方に結合される、N-P-LDMOSデバイス及び制御回路。 - 単一チップ上に形成される、N-P横方向ダブル拡散金属酸化物半導体(LDMOS)デバイス及び制御回路であって、前記N-P-LDMOSデバイス及び制御回路が、
p型基板上に形成される底部n型領域、
前記底部n型領域に重なる頂部n型領域であって、前記底部n型領域の一部と前記頂部n型領域とが、埋め込みp型領域により分離され、
前記頂部n型領域に部分的に重なる第2のp型領域、
前記第2のp型領域の第1の端部、及び前記頂部n型領域に近接して形成されるn型ウェルであって、前記n型ウェルが、第1の重くドープされたn型領域及び第1の重くドープされたp型領域を含み、前記第1の重くドープされたn型領域及び前記第1の重くドープされたp型領域が、前記N-P-LDMOSデバイスのドレイン電極に結合される、前記n型ウェル、
前記第2のp型領域の第2の端部、及び前記頂部n型領域に近接して形成されるp型ウェルであって、前記p型ウェルが、第2の重くドープされたn型領域及び第2の重くドープされたp型領域を含み、前記第2の重くドープされたn型領域及び前記第2の重くドープされたp型領域が、前記N-P-LDMOSデバイスのソース電極に結合される、前記p型ウェル、
前記第1の重くドープされたp型領域の一部、前記n型ウェル、及び前記第2のp型領域の一部に重なる、p-ゲート、及び
前記第2の重くドープされたn型領域の一部、前記p型ウェル、及び前記第2のp型領域の一部に重なる、n-ゲート、
を含み、
前記ドレイン電極が、N-LDMOSトランジスタのドレインに結合され、前記N-L
DMOSトランジスタが、前記N-P-LDMOSデバイスのnゲートを制御する信号を受け取るように結合されるゲートと、下側レール及び負の電圧の一方に結合されるソースとを含む、N-P-LDMOSデバイス及び制御回路。 - 請求項16に記載のN-P-LDMOSデバイス及び制御回路であって、
前記ドレイン電極が、抵抗器を介して前記N-LDMOSトランジスタの前記ドレインに結合される、N-P-LDMOSデバイス及び制御回路。 - 請求項17に記載のN-P-LDMOSデバイス及び制御回路であって、
前記ドレイン電極が更に、ダイオードを介して前記N-LDMOSトランジスタの前記ドレインに結合される、N-P-LDMOSデバイス及び制御回路。 - 請求項16に記載のN-P-LDMOSデバイス及び制御回路であって、
前記ドレイン電極が、デプリーションモードPMOSトランジスタのソース及びゲートに結合され、前記デプリーションモードPMOSトランジスタが、N-LDMOSトランジスタの前記ドレインに結合されるドレインを有する、N-P-LDMOSデバイス及び制御回路。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/067,928 | 2016-03-11 | ||
US15/067,928 US9843322B2 (en) | 2016-03-11 | 2016-03-11 | Integrated high-side driver for P-N bimodal power device |
PCT/US2017/022183 WO2017156540A1 (en) | 2016-03-11 | 2017-03-13 | Integrated high-side driver for p-n bimodal power device |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008288802A (ja) * | 2007-05-16 | 2008-11-27 | Hitachi Ltd | 半導体回路 |
JP2012191454A (ja) * | 2011-03-10 | 2012-10-04 | Toshiba Corp | 窒化物半導体装置 |
WO2015125492A1 (ja) * | 2014-02-24 | 2015-08-27 | パナソニック株式会社 | 半導体装置 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4947192A (en) | 1988-03-07 | 1990-08-07 | Xerox Corporation | Monolithic silicon integrated circuit chip for a thermal ink jet printer |
US5156989A (en) | 1988-11-08 | 1992-10-20 | Siliconix, Incorporated | Complementary, isolated DMOS IC technology |
US6800903B2 (en) * | 1996-11-05 | 2004-10-05 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
JP2001085981A (ja) * | 1999-09-14 | 2001-03-30 | Matsushita Electric Ind Co Ltd | 高電圧アナログスイッチ回路 |
JP2002270830A (ja) * | 2001-03-12 | 2002-09-20 | Fuji Electric Co Ltd | 半導体装置 |
US6855985B2 (en) * | 2002-09-29 | 2005-02-15 | Advanced Analogic Technologies, Inc. | Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology |
US7215189B2 (en) * | 2003-11-12 | 2007-05-08 | International Rectifier Corporation | Bootstrap diode emulator with dynamic back-gate biasing |
US7163856B2 (en) * | 2003-11-13 | 2007-01-16 | Volterra Semiconductor Corporation | Method of fabricating a lateral double-diffused mosfet (LDMOS) transistor and a conventional CMOS transistor |
US8253197B2 (en) * | 2004-01-29 | 2012-08-28 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
US7015544B2 (en) | 2004-08-23 | 2006-03-21 | Enpirion, Inc. | Intergrated circuit employable with a power converter |
JP4938307B2 (ja) * | 2005-12-28 | 2012-05-23 | パナソニック株式会社 | スイッチ回路、ダイオード |
CN101521203B (zh) * | 2009-04-07 | 2010-08-04 | 电子科技大学 | 一种半导体横向器件和高压器件 |
US8138049B2 (en) | 2009-05-29 | 2012-03-20 | Silergy Technology | Fabrication of lateral double-diffused metal oxide semiconductor (LDMOS) devices |
JP5431992B2 (ja) * | 2010-02-09 | 2014-03-05 | セイコーインスツル株式会社 | トランスミッションゲート及び半導体装置 |
US9362388B1 (en) * | 2010-08-13 | 2016-06-07 | Volterra Semiconductor LLC | Testing of LDMOS device |
US8786371B2 (en) * | 2011-11-18 | 2014-07-22 | Skyworks Solutions, Inc. | Apparatus and methods for voltage converters |
US9443839B2 (en) | 2012-11-30 | 2016-09-13 | Enpirion, Inc. | Semiconductor device including gate drivers around a periphery thereof |
KR20140072434A (ko) * | 2012-12-04 | 2014-06-13 | 에스케이하이닉스 주식회사 | 반도체 메모리 소자 및 이의 제조방법 |
US9413375B2 (en) * | 2014-01-03 | 2016-08-09 | Broadcom Corporation | Analog and audio mixed-signal front end for 4G/LTE cellular system-on-chip |
US9843322B2 (en) * | 2016-03-11 | 2017-12-12 | Texas Instruments Incorporated | Integrated high-side driver for P-N bimodal power device |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008288802A (ja) * | 2007-05-16 | 2008-11-27 | Hitachi Ltd | 半導体回路 |
JP2012191454A (ja) * | 2011-03-10 | 2012-10-04 | Toshiba Corp | 窒化物半導体装置 |
WO2015125492A1 (ja) * | 2014-02-24 | 2015-08-27 | パナソニック株式会社 | 半導体装置 |
Non-Patent Citations (1)
Title |
---|
"A RESURF P-N Bimodal LDMOS Suitable for High Voltage Power Switching Applications", PROCEEDINGS OF THE 27TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICE & IC'S, JPN7023001096, 10 May 2015 (2015-05-10), ISSN: 0005017107 * |
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EP3427301A1 (en) | 2019-01-16 |
WO2017156540A1 (en) | 2017-09-14 |
JP7043699B2 (ja) | 2022-03-30 |
CN108780810B (zh) | 2023-01-24 |
CN115882840A (zh) | 2023-03-31 |
EP3427301A4 (en) | 2019-08-14 |
CN108780810A (zh) | 2018-11-09 |
US9843322B2 (en) | 2017-12-12 |
US20170264289A1 (en) | 2017-09-14 |
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