Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
  • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
  • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
  • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
  • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
  • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
  • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
  • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer

Definitions

• the invention relates to a method according to claim 1 and a
• Apparatus according to claim 13 or 14 for treating a temporarily bonded product wafer Apparatus according to claim 13 or 14 for treating a temporarily bonded product wafer.
• Novel, three-dimensional integrated circuits require reliable methods of handling thin wafers in order to be able to successfully transport the thin wafers through the necessary manufacturing processes on the back of the wafer.
• the method of temporary bonding has become established for this purpose.
• the product wafer is mounted with a completely or partially finished first main surface by means of a suitable method, in particular by means of adhesive technology on a carrier wafer.
• this first main surface points in the direction of the carrier wafer.
• the product wafer is then thinned using known grinding techniques. After this thinning process Further manufacturing steps are carried out on the back side of the thin wafer.
• processes in which high thermal stresses were generated in the wafer, such as abrupt heating and / or cooling have led to problems.
• the wafer has dents (English, dimples) get that have made further processing impossible. These dents are at the same time also places where the adhesive used to fix the thin wafer flows and thus the adhesive thickness is uneven.
• the wafer is known to thin on backgrind tapes (BG tape), so no stable carrier substrates.
• BG tape backgrind tapes
• the wafer is usually thinned by grinding only. There is no further processing on the wafer back more. At least in this case, complex structures such as wiring lines or the like are no longer manufactured.
• it is common to thin the wafers by a series of coarse and fine grinding processes. However, these grinding processes usually leave damage to the
• the second relevant area is the range of thin wafers mounted on rigid carrier substrates. In this area, the wafers are also using coarse and fine grinding on the
• target thickness thinned typically, target thicknesses of less than 100 ⁇ are desired.
• wafers are preferably thinned to 75 ⁇ or 50 ⁇ . In the future, it is expected that the wafers will be thinned even more to 30, 20 or even ⁇ ⁇ .
• the detailed process sequence when thinly wafers were usually determined by the required surface finish.
• the re-thinning process has ended with the use of the fine grinding process using the Polygrind grinding wheel. To this day, no consciously chosen processes have been used to improve the surface quality for further processing, especially in thermal applications. Partly because the rigid support was considered as a sufficient means to adequately support and hold the thin wafer during the subsequent process.
• the invention relates to a method of avoiding the above-mentioned dents when wafers are thinned and thus to ensure the quality of the temporarily bonded wafers during the process flow. If the surface defects were not avoided, the further processing would lead to the technical problems described above.
• Dellenbi ldung arise when, as the thickness of the wafer, they also have on the front of an increasing topography, which are to be embedded in the, located between the carrier and product wafer adhesive.
• This topography is for wafer with low topography less than ⁇ ⁇ , typically less than 20 ⁇ , which in this case has adhesive thicknesses of 10 to 30 ⁇ result. It should be noted here that usually the adhesive thickness is selected to be about ⁇ ⁇ stronger than the height of the topography.
• topographical heights of> 30 ⁇ often with> 50 ⁇ but typically with> 70 ⁇ and in many cases with> 100 ⁇ expected.
• the higher adhesive thickness in conjunction with the very thin wafers means that even slight stress in the wafer is sufficient to cause dents. This is a phenomenon that mainly occurs for thermoplastic adhesives which lose viscosity at elevated temperature. This represents requirements that are not found in the case of the usual (prior art) backgrind on BG tape.
• the higher adhesive thickness allows for easier flow of the adhesive, which is associated with the very low inherent stiffness of the product wafer
• the above-mentioned invention makes it possible to extend the temperature range in which the wafers can be processed. Especially at PECVD
• Ultrathin wafers with this kind of stacked structures are usually processed above 50 ° C, in particular above 75 ° C and in particular above 100 ° C, whereby said invention is indispensable to prevent dents.
• the invention is therefore based on the idea to set the voltage of the thin wafer after grinding targeted.
• the thin wafer is mounted by means of known methods on a support.
• This carrier wafer can basically consist of any Matertal with corresponding mechanical properties. However, silicon, glass and certain ceramic materials are preferably used. A main focus here is that the carrier wafers have a thermal
• thermoplastic or at least predominantly thermoplastic adhesive As an example of such adhesives, the HT 10.10 material from Brewer Science Inc., Rolla,
• Thinning process thinned This thin process takes place from a
• Damaged crystal structure either completely or partially controlled to remove. It is further pointed out that the crystal structure can be defective not only on the surface but also up to a few micrometers below the surface, therefore the defects over a large depth, in particular lower than 0.5 ⁇ m, 1 ⁇ m, 3 ⁇ m 5 ⁇ m and even to ⁇ ⁇ , are present. By means of reducing the defects
• Residual stress is removed a layer thickness S whose value can be determined depending on the product wafer thickness D of the product wafer after thinning or grinding of the product wafer.
• the ratio of the layer thickness S to the product wafer thickness D lies between 1 to 300 and 1 to 10, in particular between 1 to 15 and 1 to 20, preferably between 1 to 100 and 1 to 30. It is therefore not sufficient, only a few
• the wafer In the partial removal, it is possible to specifically set the stress of the wafer, and thus any residual stresses of the wafer, for example due to the active side layer could be available to compensate. As a result, the wafer no longer warps during subsequent processes with high thermal stress.
• Suitable processes for removing this damaged layer are:
• the invention consists in a process flow, characterized in that
• CMP Cleaning and mechanical chemical polishing
• Structure wafer is prevented in the underlying adhesive layer, especially at higher temperatures.
• Structure wafer is extremely increased.
• the controlling factor 0.5 ⁇ , ⁇ ⁇ , 3 ⁇ , 5 ⁇ and ⁇ ⁇ ⁇
• the voltages are adjusted so that a future occurring stress, caused by layers that are later applied to the wafer, already in the adjustment of stress with
• the voltage is adjusted so that the wafer preferably during the thermal process for
• Carrier wafer bulges out, and thus counteract delamination.
• silicone-like adhesives which crosslink either thermally or by UV light exposure, are used.
• the process can be used for all thermosetting adhesives.
• the method proves to be particularly advantageous in combination with thermoplastic adhesives whose viscosity increases with increasing
• Waferstapel is introduced mainly via heat conduction.
• the temperature of the Chucks used moves in the range of 1 00 to 400 ° C, but especially in the range of 150 to 300 ° C and preferably in the range of 1 80 to 250 ° C, where the heat transfer by heat radiation is not so important role plays. Therefore, the wafer stack in this case is heated particularly abruptly within a short time, starting on contact of the wafer stack with the chuck. Since the wafer is never in full contact with the chuck, the heat transfer is preferably at those points where contact prevails.
• FIG. 2 shows a surface of a temporarily bonded product wafer after a treatment according to the present invention (C-SAM uptake).
• FIG. 1 shows that the product wafer according to FIG. 1 has distinct dents
• FIG. 2 shows that a wafer treated according to the invention has a substantially more homogeneous surface structure. Accordingly, the wafer according to FIG. 2 has less

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Mechanical Treatment Of Semiconductor (AREA)
• Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=44169003

Family Applications (1)

Country Status (9)

Citations (6)

Family Cites Families (19)

• 2010
  • 2010-02-05 DE DE102010007127A patent/DE102010007127A1/de not_active Ceased
  • 2010-11-23 CN CN201080063106.6A patent/CN102725838B/zh active Active
  • 2010-11-23 US US13/575,316 patent/US9362154B2/en active Active
  • 2010-11-23 WO PCT/EP2010/007098 patent/WO2011095189A1/de active Application Filing
  • 2010-11-23 KR KR1020127017583A patent/KR101822669B1/ko active IP Right Grant
  • 2010-11-23 JP JP2012551501A patent/JP2013519218A/ja active Pending
  • 2010-11-23 SG SG2012054839A patent/SG182703A1/en unknown
  • 2010-11-23 EP EP10787688A patent/EP2532024A1/de not_active Ceased
• 2011
  • 2011-02-01 TW TW100104032A patent/TWI525677B/zh active

Patent Citations (6)

Non-Patent Citations (2)

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