WO2011095189A1 - Verfahren zur behandlung eines temporär gebondeten produktwafers - Google Patents
Verfahren zur behandlung eines temporär gebondeten produktwafers Download PDFInfo
- Publication number
- WO2011095189A1 WO2011095189A1 PCT/EP2010/007098 EP2010007098W WO2011095189A1 WO 2011095189 A1 WO2011095189 A1 WO 2011095189A1 EP 2010007098 W EP2010007098 W EP 2010007098W WO 2011095189 A1 WO2011095189 A1 WO 2011095189A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- wafer
- product wafer
- residual stress
- flat side
- thinning
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 63
- 238000000227 grinding Methods 0.000 claims abstract description 21
- 239000000853 adhesive Substances 0.000 claims description 21
- 230000001070 adhesive effect Effects 0.000 claims description 21
- 229920001169 thermoplastic Polymers 0.000 claims description 6
- 239000004416 thermosoftening plastic Substances 0.000 claims description 6
- 238000012876 topography Methods 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 5
- 238000004381 surface treatment Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 85
- 239000000047 product Substances 0.000 description 19
- 230000035882 stress Effects 0.000 description 17
- 239000010410 layer Substances 0.000 description 8
- 230000007547 defect Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 4
- 241001050985 Disco Species 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000007847 structural defect Effects 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
Definitions
- the second relevant area is the range of thin wafers mounted on rigid carrier substrates. In this area, the wafers are also using coarse and fine grinding on the
- target thickness thinned typically, target thicknesses of less than 100 ⁇ are desired.
- wafers are preferably thinned to 75 ⁇ or 50 ⁇ . In the future, it is expected that the wafers will be thinned even more to 30, 20 or even ⁇ ⁇ .
- the detailed process sequence when thinly wafers were usually determined by the required surface finish.
- the re-thinning process has ended with the use of the fine grinding process using the Polygrind grinding wheel. To this day, no consciously chosen processes have been used to improve the surface quality for further processing, especially in thermal applications. Partly because the rigid support was considered as a sufficient means to adequately support and hold the thin wafer during the subsequent process.
- the voltages are adjusted so that a future occurring stress, caused by layers that are later applied to the wafer, already in the adjustment of stress with
- silicone-like adhesives which crosslink either thermally or by UV light exposure, are used.
- the process can be used for all thermosetting adhesives.
- the method proves to be particularly advantageous in combination with thermoplastic adhesives whose viscosity increases with increasing
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP10787688A EP2532024A1 (de) | 2010-02-05 | 2010-11-23 | Verfahren zur behandlung eines temporär gebondeten produktwafers |
SG2012054839A SG182703A1 (en) | 2010-02-05 | 2010-11-23 | Method for treatment of a temporarily bonded product wafer |
JP2012551501A JP2013519218A (ja) | 2010-02-05 | 2010-11-23 | 一時的にボンディングされた製品ウェハの処理方法 |
KR1020127017583A KR101822669B1 (ko) | 2010-02-05 | 2010-11-23 | 임시 결합된 제품 웨이퍼의 처리 방법 |
US13/575,316 US9362154B2 (en) | 2010-02-05 | 2010-11-23 | Method for treatment of a temporarily bonded product wafer |
CN201080063106.6A CN102725838B (zh) | 2010-02-05 | 2010-11-23 | 用于处理暂时接合的产品晶片的方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102010007127.7 | 2010-02-05 | ||
DE102010007127A DE102010007127A1 (de) | 2010-02-05 | 2010-02-05 | Verfahren zur Behandlung eines temporär gebondeten Produktwafers |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2011095189A1 true WO2011095189A1 (de) | 2011-08-11 |
Family
ID=44169003
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2010/007098 WO2011095189A1 (de) | 2010-02-05 | 2010-11-23 | Verfahren zur behandlung eines temporär gebondeten produktwafers |
Country Status (9)
Country | Link |
---|---|
US (1) | US9362154B2 (de) |
EP (1) | EP2532024A1 (de) |
JP (1) | JP2013519218A (de) |
KR (1) | KR101822669B1 (de) |
CN (1) | CN102725838B (de) |
DE (1) | DE102010007127A1 (de) |
SG (1) | SG182703A1 (de) |
TW (1) | TWI525677B (de) |
WO (1) | WO2011095189A1 (de) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004186522A (ja) * | 2002-12-05 | 2004-07-02 | Renesas Technology Corp | 半導体装置の製造方法 |
US20060284285A1 (en) * | 2005-06-17 | 2006-12-21 | Seiko Epson Corporation | Manufacturing method for a semiconductor device, semiconductor device, circuit substrate and electronic device |
US20080318362A1 (en) * | 2004-07-16 | 2008-12-25 | Chuichi Miyazaki | Manufacturing Method of Semiconductor Integrated Circuit Device |
US20090199957A1 (en) * | 2006-07-28 | 2009-08-13 | Tokyo Ohka Kogyo Co., Ltd. | Method of bonding, thinning, and releasing wafer |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1064920A (ja) | 1996-08-19 | 1998-03-06 | Dainippon Screen Mfg Co Ltd | 基板加熱装置 |
JP3768069B2 (ja) * | 2000-05-16 | 2006-04-19 | 信越半導体株式会社 | 半導体ウエーハの薄型化方法 |
DE10121556A1 (de) | 2001-05-03 | 2002-11-14 | Infineon Technologies Ag | Verfahren zum Rückseitenschleifen von Wafern |
TWI226084B (en) | 2002-03-28 | 2005-01-01 | Mitsui Chemicals Inc | Adhesive film for protection of semiconductor wafer surface and method of protecting semiconductor wafer with the adhesive film |
JP2004079889A (ja) | 2002-08-21 | 2004-03-11 | Disco Abrasive Syst Ltd | 半導体ウェーハの製造方法 |
DE10256247A1 (de) * | 2002-11-29 | 2004-06-09 | Andreas Jakob | Schichtverbund aus einer Trennschicht und einer Schutzschicht zum Schutze und zum Handling eines Wafers beim Dünnen, bei der Rückseitenbeschichtung und beim Vereinzeln |
US7354798B2 (en) * | 2002-12-20 | 2008-04-08 | International Business Machines Corporation | Three-dimensional device fabrication method |
US6940181B2 (en) * | 2003-10-21 | 2005-09-06 | Micron Technology, Inc. | Thinned, strengthened semiconductor substrates and packages including same |
JP4232605B2 (ja) * | 2003-10-30 | 2009-03-04 | 住友電気工業株式会社 | 窒化物半導体基板の製造方法と窒化物半導体基板 |
US7186629B2 (en) * | 2003-11-19 | 2007-03-06 | Advanced Materials Sciences, Inc. | Protecting thin semiconductor wafers during back-grinding in high-volume production |
JP4405246B2 (ja) * | 2003-11-27 | 2010-01-27 | スリーエム イノベイティブ プロパティズ カンパニー | 半導体チップの製造方法 |
JP2006135272A (ja) * | 2003-12-01 | 2006-05-25 | Tokyo Ohka Kogyo Co Ltd | 基板のサポートプレート及びサポートプレートの剥離方法 |
JPWO2006090650A1 (ja) | 2005-02-23 | 2008-07-24 | Jsr株式会社 | ウェハ加工方法 |
JP4897312B2 (ja) | 2006-03-06 | 2012-03-14 | 信越ポリマー株式会社 | 固定キャリア |
JP4698517B2 (ja) * | 2006-04-18 | 2011-06-08 | 日東電工株式会社 | 保護テープ剥離方法およびこれを用いた装置 |
US7608526B2 (en) * | 2006-07-24 | 2009-10-27 | Asm America, Inc. | Strained layers within semiconductor buffer structures |
US20080200011A1 (en) * | 2006-10-06 | 2008-08-21 | Pillalamarri Sunil K | High-temperature, spin-on, bonding compositions for temporary wafer bonding using sliding approach |
JP5250968B2 (ja) | 2006-11-30 | 2013-07-31 | 株式会社Sumco | エピタキシャルシリコンウェーハ及びその製造方法並びにエピタキシャル成長用シリコンウェーハ。 |
JP2009302163A (ja) | 2008-06-11 | 2009-12-24 | Sumco Corp | シリコンウェーハ及びそれを用いたエピタキシャルシリコンウェーハ及び貼り合わせsoiウェーハ並びにそれらの製造方法。 |
US8692260B2 (en) * | 2008-09-26 | 2014-04-08 | Soitec | Method of forming a composite laser substrate |
US8456073B2 (en) * | 2009-05-29 | 2013-06-04 | Massachusetts Institute Of Technology | Field emission devices including nanotubes or other nanoscale articles |
-
2010
- 2010-02-05 DE DE102010007127A patent/DE102010007127A1/de not_active Ceased
- 2010-11-23 CN CN201080063106.6A patent/CN102725838B/zh active Active
- 2010-11-23 WO PCT/EP2010/007098 patent/WO2011095189A1/de active Application Filing
- 2010-11-23 SG SG2012054839A patent/SG182703A1/en unknown
- 2010-11-23 JP JP2012551501A patent/JP2013519218A/ja active Pending
- 2010-11-23 EP EP10787688A patent/EP2532024A1/de not_active Ceased
- 2010-11-23 KR KR1020127017583A patent/KR101822669B1/ko active IP Right Grant
- 2010-11-23 US US13/575,316 patent/US9362154B2/en active Active
-
2011
- 2011-02-01 TW TW100104032A patent/TWI525677B/zh active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004186522A (ja) * | 2002-12-05 | 2004-07-02 | Renesas Technology Corp | 半導体装置の製造方法 |
US20080318362A1 (en) * | 2004-07-16 | 2008-12-25 | Chuichi Miyazaki | Manufacturing Method of Semiconductor Integrated Circuit Device |
US20060284285A1 (en) * | 2005-06-17 | 2006-12-21 | Seiko Epson Corporation | Manufacturing method for a semiconductor device, semiconductor device, circuit substrate and electronic device |
US20090199957A1 (en) * | 2006-07-28 | 2009-08-13 | Tokyo Ohka Kogyo Co., Ltd. | Method of bonding, thinning, and releasing wafer |
Also Published As
Publication number | Publication date |
---|---|
TW201145373A (en) | 2011-12-16 |
US20120292288A1 (en) | 2012-11-22 |
DE102010007127A1 (de) | 2011-08-11 |
TWI525677B (zh) | 2016-03-11 |
KR20120120198A (ko) | 2012-11-01 |
US9362154B2 (en) | 2016-06-07 |
SG182703A1 (en) | 2012-08-30 |
CN102725838A (zh) | 2012-10-10 |
CN102725838B (zh) | 2016-03-02 |
KR101822669B1 (ko) | 2018-03-08 |
JP2013519218A (ja) | 2013-05-23 |
EP2532024A1 (de) | 2012-12-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP2382656B1 (de) | Trennverfahren für ein schichtsystem umfassend einen wafer | |
DE102015002542B4 (de) | Waferteilungsverfahren | |
DE102011002546B4 (de) | Verfahren zum Herstellen einer mehrschichtigen Struktur mit Trimmen nach dem Schleifen | |
DE102016224214B4 (de) | Bearbeitungsverfahren für einen Wafer | |
DE10312662B4 (de) | Halbleitereinrichtungsherstellungsanordnung und Halbleitereinrichtungsherstellungsverfahren zum Bilden von Halbleiterchips durch Teilen von Halbleiterwafern | |
EP1568071B1 (de) | Wafer mit trennschicht und trägerschicht und dessen herstellungsverfahren | |
DE102011084525B4 (de) | Verfahren zur Herstellung einer Halbleitervorrichtung | |
DE102007049811B4 (de) | Läuferscheibe, Verfahren zur Beschichtung einer Läuferscheibe sowie Verfahren zur gleichzeitigen beidseitigen Material abtragenden Bearbeitung von Halbleiterscheiben | |
DE102013205126B4 (de) | Verfahren zur Herstellung einer Halbleitervorrichtung | |
DE112011102435B4 (de) | Verfahren und Vorrichtung zum Zusammenbonden von zwei Wafern durch Molekularadhäsion | |
JP5545667B2 (ja) | ダイシング・ダイボンディングフィルム及びダイシング方法 | |
EP1384255B1 (de) | Verfahren zum rückseitenschleifen von wafern | |
DE102013111016A1 (de) | Vereinzelungsverfahren | |
DE102009030294A1 (de) | Verfahren zur Politur der Kante einer Halbleiterscheibe | |
DE102016222005B4 (de) | Verfahren der Fertigung einer Halbleitervorrichtung | |
DE102012223093B4 (de) | Verfahren zur Herstellung einer Halbleitervorrichtung | |
DE112014005614T5 (de) | Verfahren zur Herstellung einer Halbleitervorrichtung | |
DE102019101142B4 (de) | Verfahren zum Herstellen einer mehrschichtigen monokristallinen Siliziumfolie | |
DE112017007552T5 (de) | Schutzabdeckung für eine Verwendung bei einer Bearbeitung eines Wafers, Handhabungssystem für einen Wafer und eine Kombination aus einem Wafer und einer Schutzabdeckung | |
DE102005011107A1 (de) | Verfahren und Vorrichtung zum Bearbeiten von Wafern auf Montageträgern | |
EP2852972A1 (de) | Vorrichtung und verfahren zum ausrichten von substraten | |
WO2012097830A1 (de) | Verfahren zum ablösen eines produktsubstrats von einem trägersubstrat | |
WO2011095189A1 (de) | Verfahren zur behandlung eines temporär gebondeten produktwafers | |
DE102014227005B4 (de) | Verfahren zum Aufteilen eines Wafers in Chips | |
WO2013185804A1 (de) | Substrat-produktsubstrat-kombination sowie vorrichtung und verfahren zur herstellung einer substrat-produktsubstrat-kombination |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 201080063106.6 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 10787688 Country of ref document: EP Kind code of ref document: A1 |
|
REEP | Request for entry into the european phase |
Ref document number: 2010787688 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2010787688 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref document number: 20127017583 Country of ref document: KR Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13575316 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2012551501 Country of ref document: JP |
|
NENP | Non-entry into the national phase |
Ref country code: DE |