TWI525677B - 處理暫時接合產物晶圓的方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims description 53
- 230000008569 process Effects 0.000 claims description 23
- 238000000227 grinding Methods 0.000 claims description 20
- 239000000853 adhesive Substances 0.000 claims description 11
- 230000001070 adhesive effect Effects 0.000 claims description 11
- 238000012545 processing Methods 0.000 claims description 11
- 239000013078 crystal Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 229920001169 thermoplastic Polymers 0.000 claims description 5
- 239000004416 thermosoftening plastic Substances 0.000 claims description 5
- 238000012876 topography Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000004381 surface treatment Methods 0.000 claims 2
- 239000000919 ceramic Substances 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 238000001312 dry etching Methods 0.000 claims 1
- 229910052715 tantalum Inorganic materials 0.000 claims 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 78
- 230000035882 stress Effects 0.000 description 17
- 239000000047 product Substances 0.000 description 11
- 230000007547 defect Effects 0.000 description 9
- 239000011230 binding agent Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000007517 polishing process Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 3
- 241001050985 Disco Species 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 238000012805 post-processing Methods 0.000 description 2
- 230000007847 structural defect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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Description
本發明係關於一種技術方案1之方法及一種技術方案13或14之用於處理一暫時接合晶圓之裝置。
新穎的三維積體電路需要處置薄晶圓以便能夠將該等薄晶圓成功地傳輸通過晶圓背側上之所需生產製程的可靠方法。在過去數年，已建立該暫時接合方法。在該方法中，藉助於一適合的方法、尤其藉助於黏合技術將具有一完全或局部已加工第一主表面之產物晶圓安裝於一載體上。此處，此第一主表面指向該載體晶圓之方向。接著藉助於已知研磨技術薄化該產物晶圓。在此薄化製程之後，在該薄晶圓之背側上實施其他生產步驟。在過去，其中在晶圓中產生高的熱應力之製程(諸如例如，突然加熱及/或冷卻)導致若干個問題。常常，晶圓獲得使得進一步處理不可行之微凹。該等微凹同時出現在用於固定薄晶圓之黏合劑在其上運行之位點處且因此黏合劑厚度不均勻。
已知存在背磨膠帶(BG膠帶)上之晶圓薄化，因此係非穩定載體基板。此處，通常僅藉助於研磨方法薄化晶圓。在晶圓背側上不存在進一步工作。至少在此情形下，不再產生複雜結構，例如佈線線路或類似結構。在此區域中，習用上藉助於一系列粗糙及精細研磨製程薄化晶圓。然而，該等研磨製程通常使地面晶圓表面上之晶體結構受損。此受損導致應力。因此，在此領域中，在最近幾年中，已研究消除此受損層之可能性。結果係所謂的「應力消除過程」。但為能夠繞過該等過程，研磨系統及研磨工具之製造商(諸如例如，日本的迪斯科(Disco)公司)亦已研製消除應力消除之必要性之磨輪。在此領域中，一種極普遍的產物係(例如)使得可在薄化後立即鋸切晶圓並將其等遞送至最終晶片封裝(在工業中稱為「封裝」)中之所謂的聚磨(Polygrind)磨輪。
第二相關領域係薄化安裝於剛性載體基板上之晶圓之領域。在此領域中，藉助於粗糙及精細研磨方法將晶圓同樣薄化至所期望目標厚度。通常，期望小於100 μm之目標厚度。但近來，較佳將晶圓薄化至75或50 μm。將來期盼，將更在根本上將晶圓薄化至30、20或甚至10 μm。在此範圍中，已按慣例藉由所需表面品質確定了晶圓薄化中之詳細製程順序。常常，背薄化製程藉助使用採用聚磨磨輪之精細研磨製程結束。在此領域中，到目前為止故意尚未將所選製程用於改良表面品質以用於進一步工作，尤其係在熱應用中。此尤其亦係該情形，乃因剛性載體被視為用以在隨後製程期間適當支撐薄晶圓並保持薄晶圓平坦之一充分構件。
因此，本發明之目標係設計藉此藉助越來越薄的暫時固定產物晶圓促進或實現進一步處置，尤其用於隨後化學製程之一裝置及一方法。
此目標係藉助技術方案1、13及14之特徵達成。在從屬技術方案中給出本發明之有利進展。在說明書、申請專利範圍及/或圖中所給出的至少兩個特徵之所有組合亦歸屬於本發明之框架內。在給定值範圍處，在所指示限制內之值亦將經揭示為邊界值且將在任一組合中主張。
本發明係關於一種用於避免晶圓薄化中之上述微凹，且因此在製程流程期間確保暫時接合晶圓之品質的方法。若未避免該等表面缺陷，則在進一步處理中將引起問題。
在說明書、申請專利範圍及/或圖中所給出的至少兩個特徵之所有組合亦歸屬於本發明之框架內。在給定值範圍處，在所指示限制內之值亦將揭示為邊界值且將在任一組合中主張。
本發明之其他優點、特徵及細節將自對較佳實例性實施例之以上闡述且使用該等圖式而變得顯而易見。
該等圖顯示如圖1中所示之產物晶圓具有明顯微凹，而圖2中所示之產物晶圓幾乎不具有微凹。
就在不遠的過去，微凹現象已成為一嚴重的問題。其主要原因應係薄晶圓現在僅期望極小目標厚度(見上文)之環境。若晶圓變得更薄，則薄晶圓之固有剛度減小，因此根據申請人之調查結果因晶體缺陷而引起之應力(本質應力)繼續僅藉助一較不穩定晶圓抵消。而是，此厚度範圍中之晶圓極柔韌且具有撓性。
經指出，只在最近才將用於處理超薄晶圓之此種類型之載體技術用於主要生產堆疊式晶粒或所謂的「3D封裝」。
結合微凹形成之尤其不利條件出現在隨著晶圓厚度的減小，該等晶圓在正面上亦具有增加之形貌且將被嵌入於位於載體與產物晶圓之間的黏合劑中時。具有小形貌之晶圓之此形貌係小於10 μm、通常小於20 μm；在此情形下，此導致自10 μm至30 μm之黏合劑厚度。此處，應注意，按慣例將黏合劑厚度選擇為大致較該形貌之高度厚10 μm。對於具有高形貌之晶圓，可期盼>30 μm、常常>50 μm、但通常>70 μm、且在許多情形下>100 μm之形貌高度。
較高黏合劑厚度結合極薄晶圓導致晶圓中之甚至微小應力便足以引起微凹。此係主要針對在升高溫度下失去黏性之熱塑性黏合劑發生之一現象。此表示在BG膠帶上之習用(先前技術)背磨情形下無法找到之要求。較高黏合劑厚度實現黏合劑之較易流動；此與產物晶圓之極低固有剛度相關聯促進微凹形成。
新發明之優點在於可完全避免暫時接合晶圓之背薄化中之表面缺陷；此係最終產物品質中之一顯著改良。此外，此係與生產製程之一效能改良相關聯，乃因該等微凹甚至在晶圓在生產製程中通常將經受之較高溫度下不再出現。
由於微凹形成亦相依於溫度(由於隨著溫度的上升，熱塑性黏合劑之黏性減小)，因此可藉由此發明加寬其中可處理晶圓之溫度範圍。主要在其中使用較高溫度及其中藉由電漿的作用將額外熱量遞送至晶圓中之PECVD製程中，必須使微凹形成完全停止。已證明，此發明實際上使微凹形成停止。具有此種類型之堆疊式結構之超薄晶圓通常在高於50℃、尤其高於75℃且特定而言高於100℃之情形下處理，藉此所指示之發明變得為避免微凹形成所必不可少。
因此，本發明係基於在以一專用方式研磨之後設定薄晶圓之應力之構想。此處，薄晶圓係藉助於已知方法安裝於一載體上。此載體晶圓可在根本上由具有對應機械性質之任何材料組成。但較佳使用矽、玻璃及某些陶瓷材料。此處，一個主要特徵係基於具有一熱膨脹係數之載體，該熱膨脹係數在地點上且亦相對於係數在溫度範圍內之特性兩者匹配/盡可能相同於產物晶圓(例如，矽)之熱膨脹係數。此處，應提及使用一熱塑性或至少大部分熱塑性黏合劑將具有已處理側之產物晶圓黏合至載體晶圓上之一較佳版本。此黏合劑之一個實例係來自美國密蘇裏州羅拉之布魯爾科技有限公司之HT 10.10材料。接著藉助於研磨方法薄化晶圓。此薄化製程因粗糙與精細研磨製程的相互作用而發生。本發明之決定性部分係使晶圓經受使得可以一受控方式完全或部分移除具有受損晶體結構之層之一進一步適合的製程。此外，有人指出，該晶體結構可不僅在表面上且亦至表面下方數μm處有缺陷，因此該等缺陷存在於一大深度上方、尤其深於0.5 μm、1 μm、3 μm、5 μm且甚至10 μm。
因此，僅移除數層原子以移除表面附近之缺陷並不夠。
在局部移除中，可以一專用方式設定晶圓之應力且因此補償可(例如)因作用側上之層而存在之晶圓之可能本質應力。因此，該晶圓不再在後續製程期間藉助一高的熱應力拱起。
用於移除此受損層之適合的製程係：
- 拋光製程-例如來自迪斯科之「乾式拋光製程」，
- 藉助於適合的化學品實施濕式蝕刻製程，
- 乾燥製程，
- 該等上述製程之一組合。
本發明在於一製程流程，其特徵在於
- 經由一黏合材料將一載體晶圓暫時接合至一結構晶圓
- 後處理該結構晶圓在背薄化之後發生
- 後處理該結構晶圓係清潔與化學機械拋光(CMP)之一組合，其特徵在於：在CMP中減小或完全消除因脆性斷裂產生之表面粗糙度、裂紋及內置本質應力
- 因所產生之較平滑表面而存在較少結構缺陷，該等結構缺陷在較高溫度下最終用作上述表面缺陷(微凹)之一起始點
- 因CMP，結構晶圓中之本質應力大大小於已藉由研磨薄化之結構晶圓中之本質應力
- 因較低本質應力，主要在較高溫度下防止極薄結構晶圓至下伏黏合層中之一局部彈性彎折及/或塑性形變
- 在無該等表面缺陷(微凹)之情形下，極其增強結構晶圓之品質
- 控制因數0.5 μm、1 μm、5 μm及10 μm。
本發明在於一製程流程，其特徵在於
- 經由一黏合材料將一載體晶圓暫時接合至一結構晶圓
- 後處理該結構晶圓在背薄化之後發生
- 後處理該結構晶圓係清潔與化學機械拋光(CMP)之一組合，其特徵在於：在CMP中減小或完全消除因脆性斷裂產生之表面粗糙度、裂紋及內置本質應力
- 因所產生之較平滑表面而存在較少結構缺陷，該等結構缺陷在較高溫度下最終用作上述表面缺陷(微凹)之一起始點
- 因CMP，結構晶圓中之本質應力大大小於已藉由研磨薄化之結構晶圓中之本質應力
- 因較低本質應力，主要在較高溫度下防止極薄結構晶圓至下伏黏合層中之一局部彈性彎折及/或塑性形變
- 在無該等表面缺陷(微凹)之情形下，極其增強結構晶圓之品質
- 控制因數0.5 μm、1 μm、3 μm、5 μm及10 μm。
圖1顯示在根據先前技術之一研磨製程之後一暫時接合產物晶圓之一表面(C-SAM像片)；及
圖2顯示在根據此發明之處理之後一暫時接合產物晶圓之一表面(C-SAM像片)。
(無元件符號說明)
Claims (16)
- 一種藉助以下步驟處理暫時接合於剛性載體晶圓上之產物晶圓的方法：提供剛性載體晶圓，其具有表面及位於該表面上之黏合劑，將產物晶圓之已處理側固定至位於該剛性載體晶圓之該表面上的黏合劑，將背對該剛性載體晶圓之該表面的扁平側上之該產物晶圓研磨及/或背薄化至<150μm之產物晶圓厚度D，藉助用於減小該產物晶圓之結構性本質應力之手段表面處理該扁平側，設定該產物晶圓之該本質應力之該手段使得該產物晶圓在隨後熱製程期間朝向該剛性載體晶圓拱起。
- 如請求項1之方法，其中表面處理步驟發生於一位置，其在空間上與背薄化步驟之位置係分離的。
- 如請求項1之方法，其中用於減小該本質應力之該等手段的特徵在於以下特徵中之至少一者：乾式拋光該扁平側，濕式蝕刻該扁平側，及乾式蝕刻該扁平側。
- 如請求項1之方法，其中該產物晶圓厚度D係小於30μm。
- 如請求項1之方法，其中該剛性載體晶圓具有與該產物晶圓之膨脹係數相同之膨脹係數。
- 如請求項1之方法，其中使用熱塑性黏合劑將該產物晶圓之與該扁平側相對之接觸側暫時連接至該剛性載體晶圓。
- 如請求項1之方法，其中用於減小該本質應力之該等手段包括至少部分地移除該扁平側之因研磨及/或背薄化而已受損之晶體結構之所界定之層厚度S。
- 如請求項1之方法，其中在表面處理之後，隨即在大於100℃之溫度下進行一熱製程步驟。
- 如請求項6之方法，其中該產物晶圓之該接觸側具有嵌入至該黏合劑中之形貌。
- 如請求項1之方法，其中在表面處理之後，隨即在>50℃之溫度下進行熱製程步驟。
- 如請求項10之方法，其中該熱製程步驟係化學氣相沈積方法。
- 如請求項7之方法，其中該層厚度S<10μm。
- 如請求項7之方法，其中該層厚度S小於1μm。
- 如請求項7之方法，其中該層厚度S小於0.5μm。
- 如請求項1之方法，其中該剛性載體晶圓包含一或多種下列材料：矽、玻璃或陶瓷。
- 一種用於處理暫時接合於剛性載體晶圓上之產物晶圓的裝置，其具有以下特徵：用於研磨及/或背薄化該產物晶圓之構件，用於減小該產物晶圓之尤其結構性本質應力之構件，其中藉由用於減小該本質應力之手段設定該產物晶圓之 該本質應力，以使得該產物晶圓在隨後熱製程期間朝向該剛性載體晶圓拱起。
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102010007127A DE102010007127A1 (de) | 2010-02-05 | 2010-02-05 | Verfahren zur Behandlung eines temporär gebondeten Produktwafers |
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| TW201145373A TW201145373A (en) | 2011-12-16 |
| TWI525677B true TWI525677B (zh) | 2016-03-11 |
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| US (1) | US9362154B2 (zh) |
| EP (1) | EP2532024A1 (zh) |
| JP (1) | JP2013519218A (zh) |
| KR (1) | KR101822669B1 (zh) |
| CN (1) | CN102725838B (zh) |
| DE (1) | DE102010007127A1 (zh) |
| SG (1) | SG182703A1 (zh) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH1064920A (ja) | 1996-08-19 | 1998-03-06 | Dainippon Screen Mfg Co Ltd | 基板加熱装置 |
| JP3768069B2 (ja) * | 2000-05-16 | 2006-04-19 | 信越半導体株式会社 | 半導体ウエーハの薄型化方法 |
| DE10121556A1 (de) | 2001-05-03 | 2002-11-14 | Infineon Technologies Ag | Verfahren zum Rückseitenschleifen von Wafern |
| TWI226084B (en) | 2002-03-28 | 2005-01-01 | Mitsui Chemicals Inc | Adhesive film for protection of semiconductor wafer surface and method of protecting semiconductor wafer with the adhesive film |
| JP2004079889A (ja) | 2002-08-21 | 2004-03-11 | Disco Abrasive Syst Ltd | 半導体ウェーハの製造方法 |
| DE10256247A1 (de) * | 2002-11-29 | 2004-06-09 | Andreas Jakob | Schichtverbund aus einer Trennschicht und einer Schutzschicht zum Schutze und zum Handling eines Wafers beim Dünnen, bei der Rückseitenbeschichtung und beim Vereinzeln |
| JP2004186522A (ja) * | 2002-12-05 | 2004-07-02 | Renesas Technology Corp | 半導体装置の製造方法 |
| US7354798B2 (en) * | 2002-12-20 | 2008-04-08 | International Business Machines Corporation | Three-dimensional device fabrication method |
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| WO2006008824A1 (ja) * | 2004-07-16 | 2006-01-26 | Renesas Technology Corp. | 半導体集積回路装置の製造方法 |
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| US20080200011A1 (en) * | 2006-10-06 | 2008-08-21 | Pillalamarri Sunil K | High-temperature, spin-on, bonding compositions for temporary wafer bonding using sliding approach |
| JP5250968B2 (ja) | 2006-11-30 | 2013-07-31 | 株式会社Ｓｕｍｃｏ | エピタキシャルシリコンウェーハ及びその製造方法並びにエピタキシャル成長用シリコンウェーハ。 |
| JP2009302163A (ja) | 2008-06-11 | 2009-12-24 | Sumco Corp | シリコンウェーハ及びそれを用いたエピタキシャルシリコンウェーハ及び貼り合わせｓｏｉウェーハ並びにそれらの製造方法。 |
| WO2010036602A1 (en) * | 2008-09-26 | 2010-04-01 | S.O.I.Tec Silicon On Insulator Technologies | Method of forming a composite laser substrate |
| US8456073B2 (en) * | 2009-05-29 | 2013-06-04 | Massachusetts Institute Of Technology | Field emission devices including nanotubes or other nanoscale articles |
-
2010
- 2010-02-05 DE DE102010007127A patent/DE102010007127A1/de not_active Ceased
- 2010-11-23 SG SG2012054839A patent/SG182703A1/en unknown
- 2010-11-23 KR KR1020127017583A patent/KR101822669B1/ko active IP Right Grant
- 2010-11-23 US US13/575,316 patent/US9362154B2/en active Active
- 2010-11-23 JP JP2012551501A patent/JP2013519218A/ja active Pending
- 2010-11-23 EP EP10787688A patent/EP2532024A1/de not_active Ceased
- 2010-11-23 CN CN201080063106.6A patent/CN102725838B/zh active Active
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| Publication number | Publication date |
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| CN102725838A (zh) | 2012-10-10 |
| EP2532024A1 (de) | 2012-12-12 |
| US20120292288A1 (en) | 2012-11-22 |
| US9362154B2 (en) | 2016-06-07 |
| SG182703A1 (en) | 2012-08-30 |
| CN102725838B (zh) | 2016-03-02 |
| JP2013519218A (ja) | 2013-05-23 |
| DE102010007127A1 (de) | 2011-08-11 |
| WO2011095189A1 (de) | 2011-08-11 |
| KR20120120198A (ko) | 2012-11-01 |
| TW201145373A (en) | 2011-12-16 |
| KR101822669B1 (ko) | 2018-03-08 |
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