CN110534404B - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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CN110534404B
CN110534404B CN201811568837.0A CN201811568837A CN110534404B CN 110534404 B CN110534404 B CN 110534404B CN 201811568837 A CN201811568837 A CN 201811568837A CN 110534404 B CN110534404 B CN 110534404B
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semiconductor substrate
polishing
substrate
adhesive layer
semiconductor
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CN110534404A (zh
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白野贵士
高野英治
丰田现
秦荣一
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Kioxia Corp
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Kioxia Corp
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

实施方式提供一种提高了衬底接合的可靠性的半导体装置的制造方法。实施方式的半导体装置的制造方法包括如下步骤：将支撑衬底与半导体衬底的第一面经由粘接层而粘接；对半导体衬底的第一面及相反侧的第二面进行加工，而将半导体衬底薄膜化；第一研磨步骤，在半导体衬底的薄膜化之后，将形成在支撑衬底或半导体衬底的斜面部的粘接层的一部分利用第一研磨面进行研磨而去除；及第二研磨步骤，在第一研磨步骤之后，将残存于支撑衬底或半导体衬底的斜面部的粘接层利用与第一研磨面不同的第二研磨面进行研磨而去除。

Description

半导体装置的制造方法
[相关申请]
本申请享有以日本专利申请2018-99668号(申请日：2018年5月24日)作为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置的制造方法。
背景技术
在背面照射型CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)传感器或利用TSV(Through-Silicon Via，硅穿孔)的积层型半导体装置的制造步骤中，存在为了半导体衬底的薄膜化而将支撑衬底与半导体衬底经由粘接层贴合的制造步骤。在衬底贴合时，存在粘接层伸出到衬底的斜面部的情况，但在粘接层中使用有导电性材料的情况下，存在于干式蚀刻、溅镀、CVD(Chemical Vapor Deposition，化学气相沉积)等使用等离子体的半导体制造的过程中产生电弧击穿，而导致衬底破坏的情况。
发明内容
实施方式提供一种提高了衬底接合的可靠性的半导体装置的制造方法。
实施方式的半导体装置的制造方法包括如下步骤：将支撑衬底与半导体衬底的第一面经由粘接层粘接；对半导体衬底的第一面及相反侧的第二面进行加工，而将半导体衬底薄膜化；第一研磨步骤，在半导体衬底的薄膜化之后，将形成于支撑衬底或半导体衬底的斜面部的粘接层的一部分利用第一研磨面进行研磨而去除；及第二研磨步骤，在第一研磨步骤之后，将残存于支撑衬底或半导体衬底的斜面部的粘接层利用与第一研磨面不同的第二研磨面进行研磨而去除。
附图说明
图1(a)～(d)是对实施方式1的半导体装置的制造方法进行说明的图。
图2(a)及(b)是对实施方式2的半导体装置的制造方法进行说明的图。
图3是对实施方式2的半导体装置的制造方法进行说明的图。
具体实施方式
以下，对用来实施发明的实施方式进行说明。
(实施方式1)
参照图1对实施方式1的半导体装置的制造方法进行说明。此外，在以下的附图的记载中，相同的部分是以相同的符号表示。但，附图是厚度与平面尺寸的关系、比率等与实物不同的示意性图。
图1是表示本实施方式的半导体装置的制造方法的步骤剖视图，且为表示半导体衬底的边缘部周边的图。
如图1(a)所示，将支撑衬底1与半导体衬底3利用粘接层2粘接。具体来说，首先，准备以石英玻璃或硅作为主材料的支撑衬底1。支撑衬底1的与半导体衬底3对向的面(正面)为平坦，但侧面不平坦且朝向外侧成为凸形状。接着，通过CVD法、涂布法或溅镀法，在支撑衬底1上形成粘接层2。粘接层2使用丙烯酸系树脂等UV(Ultraviolet，紫外线)硬化性树脂或热固性树脂。进而，通过使半导体衬底3接触在粘接层2上，并对粘接层2进行UV照射或加热，而将半导体衬底3粘接在支撑衬底1上。半导体衬底3为与支撑衬底1大致相同的尺寸，且与支撑衬底1同样地侧面不平坦且朝向外侧为凸形状。半导体衬底3是以使形成有晶体管等半导体元件的面与粘接层2对向的方式粘接。此外，也可以通过将粘接层2形成在半导体衬底3上而并非支撑衬底1上，然后使半导体衬底3粘接在支撑衬底1，而使支撑衬底1与半导体衬底3粘接。
粘接层2存在以伸出到比它与半导体衬底3的粘接面更靠外侧的方式形成在支撑衬底1的斜面部的情况。粘接层2是伸出到支撑衬底1的平坦的正面的外侧、也就是支撑衬底1侧面的凸部表面而形成。粘接层2根据向支撑衬底1上的涂布成膜条件或半导体衬底3的粘接时的按压条件而形成部位不同。粘接层2还存在不仅形成在支撑衬底1的斜面部，而且也形成在半导体衬底3的斜面部表面的情况。
在该情况下，接触层2是伸出到与支撑衬底1的正面对向的半导体衬底3的平坦面的外侧、也就是半导体衬底3侧面的凸部表面而形成。
接着，如图1(b)所示，将半导体衬底3的和它与粘接层2的粘接面相反的面面(背面)通过修整或带等机械地进行研磨，而将半导体衬底3薄膜化。此处，通过半导体衬底3的薄膜化，衬底侧面的凸部尖锐化，成为所谓的刀刃构造。
接下来，通过利用图1(c)的两条虚线4、5所示的两个研磨面，将伸出到支撑衬底1或半导体衬底3的斜面部的粘接层2分两个阶段进行研磨而去除。所谓斜面部是从衬底侧面朝向中心到达至固定距离、例如0.5mm左右为止的区域。此处，将垂直于支撑衬底1与半导体衬底3相互对向的平坦的正面的方向A-A'和虚线4所成的角度(劣角)θ1设为大于该方向A-A'与虚线5所成的角度(劣角)θ2，例如将θ1设为50°以上且未达90°，将θ2设为大于0°且为70°以下。
在第一研磨中，利用虚线4所示的研磨面，从半导体衬底3的背面研磨到支撑衬底1为止，而逐渐将粘接层2去除。在第一研磨中，不仅粘接层2被去除，半导体衬底3及支撑衬底1的一部分也被去除。通过第一研磨，能够将粘接层2的伸出到比它与半导体衬底3的粘接面靠外侧的部分去除，但必须在中途停止研磨，以防止因半导体衬底3的过度研磨而导致半导体元件或功能电路损伤。因为研磨角度(劣角)θ1较大，所以如果想要通过第一研磨将粘接层2完全去除，那么会产生损伤形成在半导体衬底3的半导体元件或功能电路的可能性。因此，在第一研磨之后，在支撑衬底1的斜面表面、尤其是侧面残存粘接层2。
因此，在第一研磨之后，通过第二研磨将残存于支撑衬底1表面的粘接层2去除。在第二研磨中，利用虚线5所示的研磨面将支撑衬底1的斜面部上的粘接层2研磨去除。如图1(d)所示，在已去除粘接层2的时点结束第二研磨。此处，因为第二研磨时的角度(劣角)θ2小于第一研磨时的角度(劣角)θ1，所以在第二研磨中，不会过度研磨到形成在半导体衬底3的半导体元件或功能电路，而能够避免它们的损伤。根据本实施方式的半导体装置的制造方法，能够一边避免设置在半导体衬底3上的半导体元件的损伤，一边将从支撑衬底1与半导体衬底3的粘接面伸出的粘接层2研磨去除。能够防止因粘接层2残存于斜面部而产生的电弧击穿。
另外，根据本实施方式的半导体装置的制造方法，在实施第一研磨之后实施第二研磨，但也可以使顺序相反，在通过第二研磨将支撑衬底1或半导体衬底3的斜面端部表面的粘接层2局部地去除之后，通过第一研磨将残存于支撑衬底1或半导体衬底3的斜面表面的粘接层2去除。
(实施方式2)
接下来，参照图2及图3，对实施方式2的半导体装置的制造方法进行说明。此外，在以下的附图的记载中，相同的部分是以相同的符号表示。但，附图是厚度与平面尺寸的关系、比率等与实物不同的示意性图。
图2是表示实施方式2的半导体装置的制造方法的步骤剖视图，且为表示半导体衬底的边缘部周边的图。实施方式2的半导体装置的制造方法在为了避免实施方式1中图1(b)所示的半导体衬底的刀刃构造，而在粘接层的研磨步骤之前预先对半导体衬底的斜面部进行切割或修整的方面与实施方式1的半导体装置的制造方法不同。关于其它方面相同，并省略说明。
在本实施方式的半导体装置的制造方法中，在如图1(a)所示那样将支撑衬底1与半导体衬底3利用粘接层2粘接之后，如图2(a)所示那样将半导体衬底3的斜面部使用切割刀片等进行切割而去除。进行切割的部位为半导体衬底3的与粘接层2的粘接区域的外侧的斜面部、例如为从半导体衬底侧面朝衬底中心方向遍及400μm以上的区域。此外，只要能够避免半导体元件或功能电路形成部的切割，也可以切割到半导体衬底3的与粘接层2的粘接面上的区域。
接着，如图2(b)所示那样从半导体衬底3的背面将半导体衬底3进行研磨而薄膜化。在本实施方式中，半导体衬底3的边缘部不会尖锐化，而不会变为刀刃构造。在实施方式1所示的方法中，随着背面研磨，半导体衬底3的边缘部的厚度变小而尖锐化。尖锐化后的边缘部的机械强度下降，因此在之后的粘接层2的研磨步骤中，存在因对尖锐化后的边缘部施加研磨压力而产生龟裂，从而边缘部缺损的可能性。存在因半导体衬底的边缘部的碎片接触于设置在粘接层2或半导体衬底3的半导体元件或功能电路而招致损伤的可能性。另外，也存在边缘部的碎片成为电弧击穿的原因的情况。
另一方面，在本实施方式的半导体装置的制造方法中，半导体衬底3的斜面部、尤其是半导体衬底3侧面的凸部在背面研磨之前被切割。因此，能够防止粘接层的研磨中的半导体衬底3的边缘部的龟裂或缺损。以后的制造步骤与实施方式1的半导体装置的制造方法相同，如图1(c)及(d)所示那样，利用不同的研磨面分两个阶段实施研磨而将粘接层2去除。此外，在图2(a)中，对半导体衬底3侧面的凸部整体进行了切割，但也可以如图3所示那样只将半导体衬底3侧面的凸部之中粘接层2侧的一部分利用研磨带等进行修整。即，也可以对半导体衬底3的斜面部之中、自粘接层侧的下表面起朝上方到固定距离为止的部分区域进行修整。然后，在图2(b)所示的半导体衬底3的利用背面研磨所进行的薄膜化时，将残存于半导体衬底3侧面的凸部去除。由此，能够在去除半导体衬底3的刀刃构造之后将粘接层2研磨去除，能够防止半导体衬底3的边缘部的龟裂或缺损。
以上，对本发明的实施方式进行了说明，但本实施方式是作为示例而提出的，并不意图限定发明的范围。新颖的实施方式能以其它各种方式实施，可在不脱离发明的主旨的范围内进行各种省略、替换及变更。这些实施方式或其变化包含在发明的范围或主旨内，并且包含在权利要求书所记载的发明及其均等的范围内。
[符号的说明]
1 支撑衬底
2 粘接层
3 半导体衬底
4 第一研磨面
5 第二研磨面
θ1 第一角度
θ2 第二角度

Claims (5)

1.一种半导体装置的制造方法，其包括如下步骤：
将支撑衬底与半导体衬底的第一面经由粘接层而粘接；
对所述半导体衬底的所述第一面及相反侧的第二面进行加工，而将所述半导体衬底薄膜化；
第一研磨步骤，在所述半导体衬底的薄膜化之后，将形成在所述支撑衬底或所述半导体衬底的斜面部的所述粘接层的一部分、所述半导体衬底及所述支撑衬底利用第一研磨面进行研磨而去除；及
第二研磨步骤，在所述第一研磨步骤之后，将残存于所述支撑衬底或所述半导体衬底的斜面部的所述粘接层利用与所述第一研磨面不同的第二研磨面进行研磨而去除；且
平行于所述半导体衬底的所述第一面的方向与所述第一研磨面所成的劣角大于0°且为40°以下；
平行于所述半导体衬底的所述第一面的方向与所述第二研磨面所成的劣角为20°以上且未达90°，且大于平行于所述半导体衬底的所述第一面的方向与所述第一研磨面所成的劣角。
2.根据权利要求1所述的半导体装置的制造方法，其特征在于还包括如下步骤：在所述半导体衬底的薄膜化之前，将所述半导体衬底侧面的凸部的至少一部分去除。
3.根据权利要求1或2所述的半导体装置的制造方法，其特征在于，
垂直于所述半导体衬底的所述第一面的方向与所述第一研磨面所成的劣角大于垂直于所述半导体衬底的所述第一面的方向与所述第二研磨面所成的劣角。
4.一种半导体装置的制造方法，其包括如下步骤：
将支撑衬底与半导体衬底的第一面经由粘接层而粘接；
对所述半导体衬底的所述第一面及相反侧的第二面进行加工，而将所述半导体衬底薄膜化；
第一研磨步骤，在所述半导体衬底的薄膜化之后，将形成在所述支撑衬底或所述半导体衬底的斜面部的所述粘接层的一部分利用第一研磨面进行研磨而去除；及
第二研磨步骤，在所述第一研磨步骤之后，将残存于所述支撑衬底或所述半导体衬底的斜面部的所述粘接层利用与所述第一研磨面不同的第二研磨面进行研磨而去除；且
垂直于所述半导体衬底的所述第一面的方向与所述第一研磨面所成的劣角为50°以上且未达90°。
5.根据权利要求4所述的半导体装置的制造方法，其特征在于，
垂直于所述半导体衬底的所述第一面的方向与所述第二研磨面所成的劣角大于0°且为70°以下。
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