JP7237464B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

Info

Publication number
JP7237464B2
JP7237464B2 JP2018099668A JP2018099668A JP7237464B2 JP 7237464 B2 JP7237464 B2 JP 7237464B2 JP 2018099668 A JP2018099668 A JP 2018099668A JP 2018099668 A JP2018099668 A JP 2018099668A JP 7237464 B2 JP7237464 B2 JP 7237464B2
Authority
JP
Japan
Prior art keywords
semiconductor substrate
polishing
adhesive layer
substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018099668A
Other languages
English (en)
Other versions
JP2019204893A (ja
Inventor
貴士 白野
英治 高野
現 豊田
栄一 秦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Kioxia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kioxia Corp filed Critical Kioxia Corp
Priority to JP2018099668A priority Critical patent/JP7237464B2/ja
Priority to CN201811568837.0A priority patent/CN110534404B/zh
Priority to US16/273,123 priority patent/US10818501B2/en
Publication of JP2019204893A publication Critical patent/JP2019204893A/ja
Application granted granted Critical
Publication of JP7237464B2 publication Critical patent/JP7237464B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02013—Grinding, lapping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/27444—Manufacturing methods by blanket deposition of the material of the layer connector in gaseous form
    • H01L2224/27452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29016—Shape in side view
    • H01L2224/29017—Shape in side view being non uniform along the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32013—Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83874—Ultraviolet [UV] curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/8393—Reshaping
    • H01L2224/83947—Reshaping by mechanical means, e.g. "pull-and-cut", pressing, stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10156—Shape being other than a cuboid at the periphery

Description

本発明の実施形態は半導体装置の製造方法に関する。
裏面照射型ＣＭＯＳセンサやＴＳＶを利用した積層型半導体装置の製造工程では、半導体
基板の薄膜化のために、支持基板と半導体基板とを接着層を介して貼り合わせる製造工程
がある。基板貼り合わせの際に接着層が基板のベベル部にはみ出すことがあるが、接着層
に導電性材料が用いられる場合、ドライエッチング、スパッタリング、ＣＶＤ等のプラズ
マを用いた半導体製造の過程でアーキングが発生し、基板破壊に及ぶことがある。
特開２０１４－１２０５８３号公報
本実施形態が解決しようとする課題は、基板接合の信頼性を高めた半導体装置の製造方法
を提供する。
本実施形態における半導体装置の製造方法は、支持基板と半導体基板の第一の面とを接着層を介して接着する工程と、半導体基板の第一の面と反対側の第二の面を加工して半導体基板を薄膜化する工程と、半導体基板の薄膜化後、支持基板または半導体基板のベベル部に形成された接着層の一部と、前記半導体基板と、前記支持基板と、を第一の研磨面で研磨して除去する第一の研磨工程と、第一の研磨工程後、支持基板または半導体基板のベベル部に残存する接着層を、第一の研磨面と異なる第二の研磨面で研磨して除去する第二の研磨工程と、を含み、半導体基板の第一の面に平行な方向と第一の研磨面とがなす劣角が、０°より大きくかつ４０°以下であり、半導体基板の第１の面に平行な方向と第二の研磨面とがなす劣角が、２０°以上かつ９０°未満であり、かつ半導体基板の第一の面に平行な方向と第一の研磨面とがなす劣角より大きい。
実施形態１に係る半導体装置の製造方法の説明図である。 実施形態２に係る半導体装置の製造方法を説明図である。 実施形態２に係る半導体装置の製造方法を説明図である。
以下、発明を実施するための実施形態について説明する。
（実施形態１） 実施形態１に係る半導体装置の製造方法について、図１を参照して説明
する。なお、以下の図面の記載において、同一部分は同一符号で表している。ただし、図
面は厚さと平面寸法との関係、比率等は現実のものとは異なり、模式的なものである。
図１は本実施形態の半導体装置の製造方法を示す工程断面図であり、半導体基板のエッジ
部周辺を示した図である。
図１（ａ）に示すように、支持基板１と半導体基板３を接着層２により接着する。具体的
には、まず石英ガラスやシリコンを主材料とする支持基板１を用意する。支持基板１の半
導体基板３と対向する面（表面）は平坦であるが、側面は平坦でなく、外側に向かって凸
形状となっている。続いて、接着層２を、ＣＶＤ法、塗布法やスパッタ法により、支持基
板１上に形成する。接着層２は、アクリル系樹脂などのＵＶ硬化性樹脂または熱硬化性樹
脂が用いられる。さらに、半導体基板３を接着層２上に接触させて、接着層２をＵＶ照射
または加熱することで、半導体基板３を支持基板１上に接着する。半導体基板３は、支持
基板１とほぼ同サイズであり、支持基板１と同じく側面は平坦でなく、外側に向かって凸
形状である。半導体基板３は、トランジスタ等の半導体素子が形成されている面を接着層
２に対向させるように接着される。なお接着層２を支持基板１上ではなく半導体基板３上
に形成し、その後半導体基板３を支持基板１に接着させることで支持基板１と半導体基板
３を接着させてもよい。
接着層２は、半導体基板３との接着面よりも外側にはみだすように支持基板１のベベル部
に形成されることがある。接着層２が、支持基板１の平坦な表面の外側、つまり支持基板
１の側面の凸部表面まではみだして形成されている。接着層２は、支持基板１上への塗布
成膜条件や半導体基板３の接着時の押圧条件により形成箇所が異なる。接着層２が、支持
基板１のベベル部だけでなく、半導体基板３のベベル部表面にも形成されることもある。
この場合、接触層２は、支持基板１の表面と対向する半導体基板３の平坦面の外側、つま
り半導体基板３の側面の凸部表面まではみだして形成される。
続いて、図１（ｂ）に示すように、半導体基板３の接着層２との接着面と反対の面面（裏
面）を、トリミングやテープ等により機械的に研磨して、半導体基板３を薄膜化する。こ
こで半導体基板３の薄膜化により、基板側面の凸部が先鋭化し、いわゆるナイフエッジ構
造となる。
次に、図１（ｃ）の２つの点線４、５で示された２つの研磨面で、支持基板１または半導
体基板３のベベル部にはみ出した接着層２を２段階で研磨することにより除去する。ベベ
ル部とは、基板側面から中心に向かって一定距離、たとえば０．５ｍｍ程度、至るまでの
領域である。ここで支持基板１と半導体基板３が互いに対向する平坦な表面に垂直な方向
Ａ－Ａ’と点線４とがなす角度（劣角）θ１を、同方向Ａ－Ａ’と点線５とがなす角度（
劣角）θ２よりも大きくする、たとえばθ１を５０°以上かつ９０°未満とし、θ２を０
°より大きく７０°以下とする。
第一の研磨では、点線４で示される研磨面で半導体基板３の裏面から支持基板１に至るま
で研磨し、接着層２を除去していく。第一の研磨では、接着層２のみならず、半導体基板
３および支持基板１の一部が除去される。第一の研磨により、半導体基板３との接着面よ
り外側にはみ出た接着層２を除去することができるが、半導体基板３の過剰研磨により半
導体素子や機能回路が損傷しないよう研磨を途中でとめる必要がある。研磨角度（劣角）
θ１が大きいため、接着層２を第一の研磨により完全に除去しようとすると、半導体基板
３に形成された半導体素子や機能回路を損傷してしまう恐れが生じる。このため、第一の
研磨後、支持基板１のベベル表面、特に側面に接着層２が残存する。
そこで、第一の研磨後に支持基板１表面に残存した接着層２を第二の研磨により除去する
。第二の研磨では、点線５で示される研磨面で支持基板１のベベル部上の接着層２が研磨
除去される。図１（ｄ）に示すとおり、接着層２を除去した時点で第二の研磨を終了する
。ここで、第二の研磨時の角度（劣角）θ２が第一の研磨時の角度（劣角）θ１より小さ
いため、第二の研磨では半導体基板３に形成された半導体素子や機能回路まで過剰研磨さ
れることなく、それらの損傷を回避することができる。 本実施形態に係る半導体装置の
製造方法によれば、支持基板１と半導体基板３の接着面からはみ出した接着層２を、半導
体基板３上に設けられた半導体素子の損傷を回避しつつ、研磨除去することができる。接
着層２がベベル部に残存することで生じるアーキングを防止することができる。
また本実施形態に係る半導体装置の製造方法によれば、第一の研磨を実施後に第二の研磨
を実施しているが、順序を反対にして、第二の研磨により支持基板１または半導体基板３
のベベル端部表面の接着層２を部分的に除去した後、第一の研磨により支持基板１または
半導体基板３のベベル表面に残存した接着層２を除去することもできる。
（実施形態２） 次に、実施形態２に係る半導体装置の製造方法について、図２および図
３を参照して説明する。なお、以下の図面の記載において、同一部分は同一符号で表して
いる。ただし、図面は厚さと平面寸法との関係、比率等は現実のものとは異なり、模式的
なものである。
図２は、実施形態２の半導体装置の製造方法を示す工程断面図であり、半導体基板のエッ
ジ部周辺を示した図である。実施形態２の半導体装置の製造方法は、実施形態１において
図１（ｂ）で示した半導体基板のナイフエッジ構造を回避するために、接着層の研磨工程
の前に半導体基板のベベル部をカットまたはトリミングしておく点で実施形態１にかかる
半導体装置の製造方法と異なる。その他の点については同様であり、説明を省略する。
本実施形態に係る半導体装置の製造方法では、図１（ａ）で示したように支持基板１と半
導体基板３を接着層２で接着後、図２（ａ）に示すように、半導体基板３のベベル部をダ
イシングブレード等を用いてカットし、除去する。カットする箇所は、半導体基板３の接
着層２との接着領域の外側のベベル部であり、例えば半導体基板側面から４００μｍ以上
基板中心方向に亘る領域である。なお、半導体素子や機能回路形成部のカットを回避でき
るのであれば、半導体基板３の接着層２との接着面上の領域までカットしてもよい。
続いて、図２（ｂ）に示すように、半導体基板３の裏面から半導体基板３を研磨して薄膜
化する。本実施形態では、半導体基板３のエッジ部が先鋭化することがなく、ナイフエッ
ジ構造にはならない。 実施形態１に示した方法では、裏面研磨とともに半導体基板３の
エッジ部の厚みが小さくなり先鋭化する。先鋭化したエッジ部は機械的強度が低下するた
め、後の接着層２の研磨工程において、先鋭化したエッジ部に研磨圧力が加わることでク
ラックが生じ、エッジ部が欠ける恐れがある。半導体基板のエッジ部の欠片が、接着層２
や半導体基板３に設けられた半導体素子や機能回路に接触することで損傷を招く恐れがあ
る。またエッジ部の欠片はアーキングの原因となることもある。
一方、本実施形態に係る半導体装置の製造方法では、半導体基板３のベベル部、特に半導
体基板３の側面の凸部が裏面研磨の前にカットされている。このため、接着層の研磨にお
ける半導体基板３のエッジ部のクラックや欠落を防止することができる。 以降の製造工
程は、実施形態１に係る半導体装置の製造方法と同様であり、図１（ｃ）および（ｄ）に
示したとおり、異なる研磨面で２段階研磨を実施して接着層２を除去する。 なお、図２
（ａ）では半導体基板３の側面の凸部全体をカットしたが、図３に示すように、半導体基
板３の側面の凸部のうち接着層２側の一部のみを研磨テープ等によりトリミングしてもよ
い。すなわち、半導体基板３のベベル部のうち、接着層側の下面から一定距離上方までの
部分領域をトリミングしてもよい。その後、図２（ｂ）に示す半導体基板３の裏面研磨に
よる薄膜化の際、半導体基板３側面に残存する凸部を除去する。これにより、半導体基板
３のナイフエッジ構造を除去したうえで接着層２を研磨除去することができ、半導体基板
３のエッジ部のクラックや欠落を防止することができる。
以上、本発明の実施形態を説明したが、本実施形態は、例として提示したものであり、発
明の範囲を限定することは意図していない。新規な実施形態は、その他の様々な形態で実
施されることが可能であり、発明の要旨を逸脱
しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその
変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその
均等の範囲に含まれる。
１ 支持基板２ 接着層３ 半導体基板４ 第一の研磨面５ 第二の研磨面θ１ 第一の
角度θ２ 第二の角度

Claims (5)

  1. 支持基板と半導体基板の第一の面とを接着層を介して接着する工程と、
    前記半導体基板の前記第一の面と反対側の第二の面を加工して、前記半導体基板を薄膜化する工程と、
    前記半導体基板の薄膜化後、前記支持基板または前記半導体基板のベベル部に形成された前記接着層の一部と、前記半導体基板と、前記支持基板と、を第一の研磨面で研磨して除去する第一の研磨工程と、
    前記第一の研磨工程後、前記支持基板または前記半導体基板のベベル部に残存する前記接着層を、前記第一の研磨面と異なる第二の研磨面で研磨して除去する第二の研磨工程と、を含み、
    前記半導体基板の前記第一の面に平行な方向と前記第一の研磨面とがなす劣角が、０°より大きくかつ４０°以下であり、
    前記半導体基板の前記第１の面に平行な方向と前記第二の研磨面とがなす劣角が、２０°以上かつ９０°未満であり、かつ前記半導体基板の前記第一の面に平行な方向と前記第一の研磨面とがなす劣角より大きい、半導体装置の製造方法。
  2. 前記半導体基板の薄膜化前に前記半導体基板側面の凸部の少なくとも一部を除去する工程をさらに含むことを特徴とする請求項１に記載の半導体装置の製造方法。
  3. 前記半導体基板の前記第一の面に垂直な方向と前記第一の研磨面とがなす劣角が、前記半導体基板の前記第一の面に垂直な方向と前記第二の研磨面とがなす劣角よりも大きいことを特徴とする請求項１または２に記載の半導体装置の製造方法。
  4. 前記半導体基板の前記第一の面に垂直な方向と前記第一の研磨面とがなす劣角が５０°以上かつ９０°未満であることを特徴とする請求項３に記載の半導体装置の製造方法。
  5. 前記半導体基板の前記第一の面に垂直な方向と前記第二の研磨面とがなす劣角が０°より大きく７０°以下であることを特徴とする請求項３又は４に記載の半導体装置の製造方法。
JP2018099668A 2018-05-24 2018-05-24 半導体装置の製造方法 Active JP7237464B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2018099668A JP7237464B2 (ja) 2018-05-24 2018-05-24 半導体装置の製造方法
CN201811568837.0A CN110534404B (zh) 2018-05-24 2018-12-21 半导体装置的制造方法
US16/273,123 US10818501B2 (en) 2018-05-24 2019-02-11 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018099668A JP7237464B2 (ja) 2018-05-24 2018-05-24 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2019204893A JP2019204893A (ja) 2019-11-28
JP7237464B2 true JP7237464B2 (ja) 2023-03-13

Family

ID=68614099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018099668A Active JP7237464B2 (ja) 2018-05-24 2018-05-24 半導体装置の製造方法

Country Status (3)

Country Link
US (1) US10818501B2 (ja)
JP (1) JP7237464B2 (ja)
CN (1) CN110534404B (ja)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010263084A (ja) 2009-05-07 2010-11-18 Sumco Corp Ｓｏｉウェーハの製造方法
JP2011115893A (ja) 2009-12-03 2011-06-16 Ebara Corp 裏面が研削された基板を研磨する方法および装置
JP2014120583A (ja) 2012-12-14 2014-06-30 Toshiba Corp 半導体装置の製造方法
JP2016046341A (ja) 2014-08-21 2016-04-04 株式会社荏原製作所 研磨方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677311A (ja) 1992-08-27 1994-03-18 Toshiba Corp 半導体基板の製造方法
JPH10270298A (ja) * 1997-03-27 1998-10-09 Mitsubishi Materials Shilicon Corp 張り合わせ基板の製造方法
US6790748B2 (en) 2002-12-19 2004-09-14 Intel Corporation Thinning techniques for wafer-to-wafer vertical stacks
JP4354769B2 (ja) 2003-09-19 2009-10-28 株式会社ディスコ ウェーハの研磨方法
FR2917232B1 (fr) * 2007-06-06 2009-10-09 Soitec Silicon On Insulator Procede de fabrication d'une structure pour epitaxie sans zone d'exclusion.
FR2935536B1 (fr) * 2008-09-02 2010-09-24 Soitec Silicon On Insulator Procede de detourage progressif
JP2010205861A (ja) 2009-03-03 2010-09-16 Okamoto Machine Tool Works Ltd 積層ウエーハの面取り装置およびそれを用いて積層ウエーハのベベル部、エッジ部を面取り加工する方法
US8551881B2 (en) 2011-04-25 2013-10-08 Nanya Technology Corporation Method of bevel trimming three dimensional semiconductor device
JP2014187110A (ja) 2013-03-22 2014-10-02 Furukawa Electric Co Ltd:The 半導体ウエハの製造方法および半導体ウエハ
JP6410152B2 (ja) * 2015-09-11 2018-10-24 東芝メモリ株式会社 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010263084A (ja) 2009-05-07 2010-11-18 Sumco Corp Ｓｏｉウェーハの製造方法
JP2011115893A (ja) 2009-12-03 2011-06-16 Ebara Corp 裏面が研削された基板を研磨する方法および装置
JP2014120583A (ja) 2012-12-14 2014-06-30 Toshiba Corp 半導体装置の製造方法
JP2016046341A (ja) 2014-08-21 2016-04-04 株式会社荏原製作所 研磨方法

Also Published As

Publication number Publication date
US10818501B2 (en) 2020-10-27
US20190362980A1 (en) 2019-11-28
CN110534404A (zh) 2019-12-03
JP2019204893A (ja) 2019-11-28
CN110534404B (zh) 2023-07-28

Similar Documents

Publication Publication Date Title
TWI484544B (zh) 使半導體片變薄的方法
US9972521B2 (en) Method for manufacturing semiconductor device to facilitate peeling of a supporting substrate bonded to a semiconductor wafer
JP6385677B2 (ja) 基板加工方法
JP2007096115A (ja) 半導体装置の製造方法
US20030129809A1 (en) Wafer splitting method using cleavage
JP2015018967A (ja) 半導体装置の製造方法および支持基板付きウェハ
US9287222B1 (en) Integrated semiconductor device and method for fabricating the same
JP4198966B2 (ja) 半導体装置の製造方法
TWI767022B (zh) 基板處理方法及基板處理系統
JP5921473B2 (ja) 半導体装置の製造方法
TW201539562A (zh) 晶圓之加工方法
JP2012195388A (ja) 半導体装置の製造方法及び半導体装置
JP2004342896A (ja) 半導体装置およびその製造方法
TW202003150A (zh) 全邊切削之晶圓加工方法
US10714528B2 (en) Chip package and manufacturing method thereof
JP7237464B2 (ja) 半導体装置の製造方法
JP4528758B2 (ja) 転写テープ及びこの転写テープを用いた半導体装置の製造方法
JP6482454B2 (ja) 電子部品の製造方法ならびに電子部品製造装置
CN111463138B (zh) 半导体器件及其制备方法
JP2001085453A (ja) 半導体装置の製造方法
JP6437404B2 (ja) 半導体装置の製造方法
US20030073264A1 (en) Method of manufacturing semiconductor device from semiconductor wafer having thick peripheral portion
JP2008034875A (ja) 半導体装置及びその製造方法
JP2009289809A (ja) 半導体装置の製造方法
JP6699515B2 (ja) 半導体ウエハおよびその製造方法

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20180907

RD07 Notification of extinguishment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7427

Effective date: 20180907

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20210317

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20220210

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20220215

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220415

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20220823

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20221017

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230131

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230301

R151 Written notification of patent or utility model registration

Ref document number: 7237464

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151