EP2532024A1 - Method for treating a temporarily bonded product wafer - Google Patents

Method for treating a temporarily bonded product wafer

Info

Publication number
EP2532024A1
EP2532024A1 EP10787688A EP10787688A EP2532024A1 EP 2532024 A1 EP2532024 A1 EP 2532024A1 EP 10787688 A EP10787688 A EP 10787688A EP 10787688 A EP10787688 A EP 10787688A EP 2532024 A1 EP2532024 A1 EP 2532024A1
Authority
EP
European Patent Office
Prior art keywords
wafer
product wafer
residual stress
flat side
thinning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP10787688A
Other languages
German (de)
French (fr)
Inventor
Jürgen Burggraf
Harald Wiesbauer
Markus Wimplinger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EV Group E Thallner GmbH
Original Assignee
EV Group E Thallner GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EV Group E Thallner GmbH filed Critical EV Group E Thallner GmbH
Publication of EP2532024A1 publication Critical patent/EP2532024A1/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer

Definitions

  • the invention relates to a method according to claim 1 and a
  • Apparatus according to claim 13 or 14 for treating a temporarily bonded product wafer Apparatus according to claim 13 or 14 for treating a temporarily bonded product wafer.
  • Novel, three-dimensional integrated circuits require reliable methods of handling thin wafers in order to be able to successfully transport the thin wafers through the necessary manufacturing processes on the back of the wafer.
  • the method of temporary bonding has become established for this purpose.
  • the product wafer is mounted with a completely or partially finished first main surface by means of a suitable method, in particular by means of adhesive technology on a carrier wafer.
  • this first main surface points in the direction of the carrier wafer.
  • the product wafer is then thinned using known grinding techniques. After this thinning process Further manufacturing steps are carried out on the back side of the thin wafer.
  • processes in which high thermal stresses were generated in the wafer, such as abrupt heating and / or cooling have led to problems.
  • the wafer has dents (English, dimples) get that have made further processing impossible. These dents are at the same time also places where the adhesive used to fix the thin wafer flows and thus the adhesive thickness is uneven.
  • the wafer is known to thin on backgrind tapes (BG tape), so no stable carrier substrates.
  • BG tape backgrind tapes
  • the wafer is usually thinned by grinding only. There is no further processing on the wafer back more. At least in this case, complex structures such as wiring lines or the like are no longer manufactured.
  • it is common to thin the wafers by a series of coarse and fine grinding processes. However, these grinding processes usually leave damage to the
  • the second relevant area is the range of thin wafers mounted on rigid carrier substrates. In this area, the wafers are also using coarse and fine grinding on the
  • target thickness thinned typically, target thicknesses of less than 100 ⁇ are desired.
  • wafers are preferably thinned to 75 ⁇ or 50 ⁇ . In the future, it is expected that the wafers will be thinned even more to 30, 20 or even ⁇ ⁇ .
  • the detailed process sequence when thinly wafers were usually determined by the required surface finish.
  • the re-thinning process has ended with the use of the fine grinding process using the Polygrind grinding wheel. To this day, no consciously chosen processes have been used to improve the surface quality for further processing, especially in thermal applications. Partly because the rigid support was considered as a sufficient means to adequately support and hold the thin wafer during the subsequent process.
  • the invention relates to a method of avoiding the above-mentioned dents when wafers are thinned and thus to ensure the quality of the temporarily bonded wafers during the process flow. If the surface defects were not avoided, the further processing would lead to the technical problems described above.
  • Dellenbi ldung arise when, as the thickness of the wafer, they also have on the front of an increasing topography, which are to be embedded in the, located between the carrier and product wafer adhesive.
  • This topography is for wafer with low topography less than ⁇ ⁇ , typically less than 20 ⁇ , which in this case has adhesive thicknesses of 10 to 30 ⁇ result. It should be noted here that usually the adhesive thickness is selected to be about ⁇ ⁇ stronger than the height of the topography.
  • topographical heights of> 30 ⁇ often with> 50 ⁇ but typically with> 70 ⁇ and in many cases with> 100 ⁇ expected.
  • the higher adhesive thickness in conjunction with the very thin wafers means that even slight stress in the wafer is sufficient to cause dents. This is a phenomenon that mainly occurs for thermoplastic adhesives which lose viscosity at elevated temperature. This represents requirements that are not found in the case of the usual (prior art) backgrind on BG tape.
  • the higher adhesive thickness allows for easier flow of the adhesive, which is associated with the very low inherent stiffness of the product wafer
  • the above-mentioned invention makes it possible to extend the temperature range in which the wafers can be processed. Especially at PECVD
  • Ultrathin wafers with this kind of stacked structures are usually processed above 50 ° C, in particular above 75 ° C and in particular above 100 ° C, whereby said invention is indispensable to prevent dents.
  • the invention is therefore based on the idea to set the voltage of the thin wafer after grinding targeted.
  • the thin wafer is mounted by means of known methods on a support.
  • This carrier wafer can basically consist of any Matertal with corresponding mechanical properties. However, silicon, glass and certain ceramic materials are preferably used. A main focus here is that the carrier wafers have a thermal
  • thermoplastic or at least predominantly thermoplastic adhesive As an example of such adhesives, the HT 10.10 material from Brewer Science Inc., Rolla,
  • Thinning process thinned This thin process takes place from a
  • Damaged crystal structure either completely or partially controlled to remove. It is further pointed out that the crystal structure can be defective not only on the surface but also up to a few micrometers below the surface, therefore the defects over a large depth, in particular lower than 0.5 ⁇ m, 1 ⁇ m, 3 ⁇ m 5 ⁇ m and even to ⁇ ⁇ , are present. By means of reducing the defects
  • Residual stress is removed a layer thickness S whose value can be determined depending on the product wafer thickness D of the product wafer after thinning or grinding of the product wafer.
  • the ratio of the layer thickness S to the product wafer thickness D lies between 1 to 300 and 1 to 10, in particular between 1 to 15 and 1 to 20, preferably between 1 to 100 and 1 to 30. It is therefore not sufficient, only a few
  • the wafer In the partial removal, it is possible to specifically set the stress of the wafer, and thus any residual stresses of the wafer, for example due to the active side layer could be available to compensate. As a result, the wafer no longer warps during subsequent processes with high thermal stress.
  • Suitable processes for removing this damaged layer are:
  • the invention consists in a process flow, characterized in that
  • CMP Cleaning and mechanical chemical polishing
  • Structure wafer is prevented in the underlying adhesive layer, especially at higher temperatures.
  • Structure wafer is extremely increased.
  • the controlling factor 0.5 ⁇ , ⁇ ⁇ , 3 ⁇ , 5 ⁇ and ⁇ ⁇ ⁇
  • the voltages are adjusted so that a future occurring stress, caused by layers that are later applied to the wafer, already in the adjustment of stress with
  • the voltage is adjusted so that the wafer preferably during the thermal process for
  • Carrier wafer bulges out, and thus counteract delamination.
  • silicone-like adhesives which crosslink either thermally or by UV light exposure, are used.
  • the process can be used for all thermosetting adhesives.
  • the method proves to be particularly advantageous in combination with thermoplastic adhesives whose viscosity increases with increasing
  • Waferstapel is introduced mainly via heat conduction.
  • the temperature of the Chucks used moves in the range of 1 00 to 400 ° C, but especially in the range of 150 to 300 ° C and preferably in the range of 1 80 to 250 ° C, where the heat transfer by heat radiation is not so important role plays. Therefore, the wafer stack in this case is heated particularly abruptly within a short time, starting on contact of the wafer stack with the chuck. Since the wafer is never in full contact with the chuck, the heat transfer is preferably at those points where contact prevails.
  • FIG. 2 shows a surface of a temporarily bonded product wafer after a treatment according to the present invention (C-SAM uptake).
  • FIG. 1 shows that the product wafer according to FIG. 1 has distinct dents
  • FIG. 2 shows that a wafer treated according to the invention has a substantially more homogeneous surface structure. Accordingly, the wafer according to FIG. 2 has less

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

The invention relates to a method for treating a product wafer temporarily bonded to a carrier wafer, comprising the following steps: grinding and/or back-thinning the product wafer on a flat side facing away from the carrier wafer to a product wafer thickness D of < 150 μm, in particular < 100 μm, preferably < 75 μm, more preferably < 50 μm, especially preferably < 30 μm, and after the grinding and/or back-thinning, treating the surface of the flat side using means for reducing an, in particular structural, internal stress of the product wafer.

Description

Verfahren zur Behandlung eines temporär gebondeten Produktwafers  Method of treating a temporarily bonded product wafer
B e s c h r e i b u n g Description
Die Erfindung betrifft ein Verfahren gemäß Anspruch 1 und eine The invention relates to a method according to claim 1 and a
Vorrichtung gemäß Anspruch 13 oder 14 zur Behandlung eines temporär gebondeten Produktwafers. Apparatus according to claim 13 or 14 for treating a temporarily bonded product wafer.
Neuartige, dreidimensional integrierte Schaltkreise benötigen verlässliche Verfahren zur Handhabung dOnner Wafer, um die dünnen Wafer durch die notwendigen Fertigungsprozesse auf der Wafer Rückseite erfolgreich transportieren zu können. In den vergangenen Jahren hat sich hierzu die Methode des Temporär-Bondens etabliert. Dabei wird der Produktwafer mit einer ganz oder teilweise fertig gestellten ersten Hauptfläche mittels eines geeigneten Verfahrens, insbesondere mittels Klebetechnologie auf einen Träger Wafer montiert. Dabei zeigt diese erste Hauptfläche in die Richtung des Trägerwafers. Der Produktwafer wird anschließend mittels bekannter Schleiftechniken gedünnt. Nach diesem Dünnungsprozess werden auf der Rückseite des dünnen Wafers weitere Fertigungsschritte durchgeführt. Dabei haben in der Vergangenheit Prozesse, bei denen im Wafer hohe thermische Spannungen erzeugt wurden, wie zum Beispiel abruptes Heizen- und/oder Kühlen, zu Problemen geführt. - Vielfach hat der Wafer dabei Dellen (engl, dimples) bekommen, die eine weitere Verarbeitung unmöglich gemacht haben. Diese Dellen sind gleichzeitig auch Stellen, an denen der zum Fixieren des dünnen Wafers verwendete Kleber verfließt und damit die Kleberdicke ungleichmäßig ist. Novel, three-dimensional integrated circuits require reliable methods of handling thin wafers in order to be able to successfully transport the thin wafers through the necessary manufacturing processes on the back of the wafer. In recent years, the method of temporary bonding has become established for this purpose. In this case, the product wafer is mounted with a completely or partially finished first main surface by means of a suitable method, in particular by means of adhesive technology on a carrier wafer. In this case, this first main surface points in the direction of the carrier wafer. The product wafer is then thinned using known grinding techniques. After this thinning process Further manufacturing steps are carried out on the back side of the thin wafer. In the past, processes in which high thermal stresses were generated in the wafer, such as abrupt heating and / or cooling, have led to problems. - In many cases, the wafer has dents (English, dimples) get that have made further processing impossible. These dents are at the same time also places where the adhesive used to fix the thin wafer flows and thus the adhesive thickness is uneven.
Bekannt ist das Wafer Dünnen auf Backgrind Tapes (BG Tape), also keine stabilen Trägersubstrate. Hier wird der Wafer zumeist mittels Schleifverfahren nur gedünnt. Es erfolgt keine weitere Bearbeitung auf der Wafer Rückseite mehr. Zumindest werden in diesem Fall keine komplexen Strukturen wie Verdrahtungsleitungen oder dergleichen mehr gefertigt. In diesem Bereich ist es üblich, die Wafer zu dünnen mittels einer Aufeinanderfolge von Grob- und Feinschleifprozessen. Diese Schleifprozesse lassen in der Regel jedoch Beschädigung der The wafer is known to thin on backgrind tapes (BG tape), so no stable carrier substrates. Here, the wafer is usually thinned by grinding only. There is no further processing on the wafer back more. At least in this case, complex structures such as wiring lines or the like are no longer manufactured. In this area, it is common to thin the wafers by a series of coarse and fine grinding processes. However, these grinding processes usually leave damage to the
Kristallstruktur auf der geschliffenen Wafer Oberfläche zurück. Diese Beschädigungen führen zu Spannungen. Daher wurde in diesem Bereich in den letzten Jahren an Möglichkeiten geforscht, um diesen beschädigten Layer zu eliminieren. Das Resultat sind sogenannte„Stress Relief Crystal structure on the ground wafer surface back. These damages lead to tension. Therefore, in recent years, possibilities have been explored in this field to eliminate this damaged layer. The result is so-called "stress relief
Prozesse". Um diese Prozesse jedoch umgehen zu können haben Processes. "However, in order to be able to circumvent these processes
Hersteller von Schleifanlagen und Schleifwerkzeugen wie z.B. die Fa. Disco in Japan auch an Schleifrädern gearbeitet, die die Notwendigkeit des Stress Reliefs eliminieren. Ein sehr populäres Produkt in diesem Bereich ist z.B. das sogenannte Polygrind Schleifrad, das es ermöglicht, die Wafer unmittelbar nach dem Dünnen zu zersägen und in die Manufacturers of grinding equipment and grinding tools, such as The company Disco in Japan also worked on grinding wheels that eliminate the need for stress relief. A very popular product in this field is e.g. The so-called Polygrind grinding wheel, which makes it possible to saw the wafers immediately after thinning and in the
endgültige Chipverpackung einzubringen, (in der Industrie unter dem Begriff„Packaging" bekannt). Der zweite relevante Bereich ist der Bereich von Dünnen Wafer, die auf starren Trägersubstraten montiert sind. In diesem Bereich werden die Wafer ebenfalls mittels Grob- und Feinschleifverfahren auf die to introduce final chip packaging (known in the industry as "packaging"). The second relevant area is the range of thin wafers mounted on rigid carrier substrates. In this area, the wafers are also using coarse and fine grinding on the
gewünschte Zieldicke gedünnt. Typischerweise werden Zieldicken von weniger als 100 μπι angestrebt. In letzter Zeit werden Wafer jedoch vorzugsweise auf 75 μιπ oder 50 μηι gedünnt. In Zukunft wird erwartet, dass die Wafer noch stärker auf 30, 20 oder gar Ι Ομηι gedünnt werden. In diesem Bereich wurde die detaillierte Prozessabfolge beim dünnen des Wafers üblicherweise durch die notwendige Oberflächengüte bestimmt. Vielfach hat der Rückdünnprozess mit der Verwendung des Feinschliff Prozesses unter Verwendung des Polygrind Schleifrades geendet. Es wurden als in diesem Bereich bis heute keine bewusst gewählten Prozesse angewendet, um die Oberflächenqualität für die weitere Bearbeitung, insbesondere bei thermischen Anwendungen, zu verbessern. Dies auch unter anderem deshalb, weil der starre Träger als ausreichendes Mittel angesehen wurde, um den dünnen Wafer während der darauffolgenden Prozess ausreichend zu stützen und flach zu halten. desired target thickness thinned. Typically, target thicknesses of less than 100 μπι are desired. Recently, however, wafers are preferably thinned to 75 μιπ or 50 μηι. In the future, it is expected that the wafers will be thinned even more to 30, 20 or even Ο Ομηι. In this area, the detailed process sequence when thinly wafers were usually determined by the required surface finish. In many cases, the re-thinning process has ended with the use of the fine grinding process using the Polygrind grinding wheel. To this day, no consciously chosen processes have been used to improve the surface quality for further processing, especially in thermal applications. Partly because the rigid support was considered as a sufficient means to adequately support and hold the thin wafer during the subsequent process.
Es ist daher die Aufgabe der vorliegenden Erfindung, eine Vorrichtung und ein Verfahren anzugeben, mit dem die weitere Handhabung bei immer dünneren, temporär fixierten Produktwafern erleichtert bzw. erst ermöglicht wird, insbesondere bei sich anschließenden thermischen Prozessen. It is therefore the object of the present invention to provide a device and a method with which the further handling is facilitated or made possible only with thinner, temporarily fixed product wafers, in particular during subsequent thermal processes.
Diese Aufgabe wird mit den Merkmalen der Ansprüche 1 , 13 und 14 gelöst. Vorteilhafte Weiterbildungen der Erfindung sind in den This object is achieved with the features of claims 1, 13 and 14. Advantageous developments of the invention are in the
Unteransprüchen angegeben. In den Rahmen der Erfindung fallen auch sämtliche Kombinationen aus zumindest zwei von in der Beschreibung, den Ansprüchen und/oder den Figuren angegebenen Merkmalen. Bei angegebenen Wertebereichen sollen auch innerhalb der genannten Subclaims specified. The scope of the invention also includes all combinations of at least two of those in the description, the claims and / or the figures given characteristics. For specified ranges of values are also within the specified
Grenzen liegende Werte als Grenzwerte offenbart und in beliebiger Kombination beanspruchbar sein. Limiting values are disclosed as limit values and can be claimed in any combination.
Die Erfindung betrifft eine Methode, die oben genannten Dellen beim Dünnen von Wafern zu vermeiden und somit die Qualität der temporär gebondeten Wafer während des Prozessflusses zu gewährleisten. Würde man die Oberflächendefekte nicht vermeiden, käme es bei der weiteren Prozessierung zu den oben beschriebenen technischen Problemen. Indem die Oberflächenbehandlung nach dem Schleifen und/oder Rückdünnen gezielt erfolgt, um die Eigenspannung des Produktwafers zu reduzieren, kann damit auf die weitere Bearbeitung des Produktwafers positiv The invention relates to a method of avoiding the above-mentioned dents when wafers are thinned and thus to ensure the quality of the temporarily bonded wafers during the process flow. If the surface defects were not avoided, the further processing would lead to the technical problems described above. The fact that the surface treatment after grinding and / or thinning is targeted in order to reduce the residual stress of the product wafer, can thus be positive for the further processing of the product wafer
Einfluss genommen werden. Denn die strukturelle Eigenspannung, die zumindest teilweise durch die oben beschriebenen Dellen verursacht wird, sorgt bei zu hoher Eigenspannung, insbesondere bei immer dünneren Wafern wegen deren geringerer Eigensteifigkeit, für die aufgeführten technischen Probleme bei der Weiterverarbeitung. Be influenced. Because the structural residual stress, which is at least partially caused by the above-described dents, ensures too high residual stress, especially with ever thinner wafers because of their lower inherent rigidity, for the listed technical problems in the further processing.
Das Phänomen der Dellen stellt erst in jüngerer Vergangenheit ein gravierendes Problem dar. Der Hauptgrund dafür dürfte in dem Umstand liegen, dass erst jetzt sehr geringe Zieldicken (siehe die Ausführungen oben) für die Dünnwafer angestrebt werden. Wenn die Wafer dünner werden, nimmt die Eigensteifigkeit der dünnen Wafer ab, wodurch dem Stress (Eigenspannung), der nach den Erkenntnissen der Anmelderin aufgrund der Kristalldefekte entsteht, nur mehr mit einem wenig stabilen Wafer entgegengewirkt wird. Vielmehr sind Wafer in diesem The phenomenon of dents has only recently been a serious problem. The main reason for this is likely to be the fact that only now are very low target thicknesses (see above) aimed for the thin wafers. As the wafers become thinner, the inherent stiffness of the thin wafers decreases, counteracting the stress (residual stress) that, according to Applicant's knowledge, is due to the crystal defects, only with a less stable wafer. Rather, wafers are in this
Dickenbereich sehr biegsam und flexibel. Es wird darauf hingewiesen, dass erst in jüngster Zeit diese Art der Trägertechnologie zur Prozessierung von ultradünnen Wafern verwendet wird um, vor allem gestapelte Dies oder sogenannte„3 D Packages" herzustellen. Thickness range very flexible and flexible. It should be noted that only recently has this type of carrier technology been used to process ultra-thin wafers, especially to produce stacked dies or so-called "3 D packages".
Besonders ungünstige Verhältnisse im Zusammenhang mit der Particularly unfavorable conditions in connection with the
Dellenbi ldung ergeben sich, wenn bei abnehmender Dicke der Wafer, diese auch auf der Vorderseite eine zunehmende Topographie aufweisen, die in den, zwischen Träger und Produktwafer befindlichen Kleber eingebettet werden sollen. Diese Topographie beträgt für Wafer mit geringer Topographie weniger als Ι Ομιη, typischerweise weniger als 20μιη, was in diesem Fall Kleberdicken von 10 bis 30μπι zur Folge hat. Man beachte hierbei, dass üblicherweise die Kleberdicke in etwa um Ι Ομιη stärker gewählt wird, als die Höhe der Topographie. Für Wafer mit hoher Topographie ist mit Topographiehöhen von >30μιη, vielfach mit >50μπι typischerweise aber mit >70μιη und in vielen Fällen mit > 100μπι zu rechnen. Dellenbi ldung arise when, as the thickness of the wafer, they also have on the front of an increasing topography, which are to be embedded in the, located between the carrier and product wafer adhesive. This topography is for wafer with low topography less than Ι Ομιη, typically less than 20μιη, which in this case has adhesive thicknesses of 10 to 30μπι result. It should be noted here that usually the adhesive thickness is selected to be about Ι Ομιη stronger than the height of the topography. For wafers with high topography topographical heights of> 30μιη, often with> 50μπι but typically with> 70μιη and in many cases with> 100μπι expected.
Die höhere Kleberdicke in Verbindung mit den sehr dünnen Wafern hat zur Folge, dass schon leichter Stress im Wafer ausreicht, um Dellen zu verursachen. Dies ist ein Phänomen, das vor allem für thermoplastische Kleber auftritt, welche bei erhöhter Temperatur an Viskosität verlieren. Dies repräsentiert Anforderungen, die im Falle des üblichen (Stand der Technik) Backgrindens auf BG Tape nicht vorzufinden sind. Die höhere Kleberdicke ermöglicht ein leichteres Fließen des Klebers, was verbunden mit der sehr geringen Eigensteifigkeit des Produktwafers die The higher adhesive thickness in conjunction with the very thin wafers means that even slight stress in the wafer is sufficient to cause dents. This is a phenomenon that mainly occurs for thermoplastic adhesives which lose viscosity at elevated temperature. This represents requirements that are not found in the case of the usual (prior art) backgrind on BG tape. The higher adhesive thickness allows for easier flow of the adhesive, which is associated with the very low inherent stiffness of the product wafer
Dellenbildung begünstigt. Der Vorteil der neuen Erfindung besteht darin, dass man Dents favored. The advantage of the new invention is that one
Oberflächendefekte beim Rückdünnen von temporär gebondeten Wafern vollkommen vermeiden kann, was eine entscheidende Surface defects in the thinning of temporarily bonded wafers can completely avoid what is a crucial
Qualitätsverbesserung des Endproduktes zur Folge. Des Weiteren ist damit eine Performanceverbesserung des Produktionsprozesses Quality improvement of the final product result. Furthermore, this improves the performance of the production process
verbunden, da die Dellen auch bei höheren Temperaturen, denen die Wafer im Produktionsprozess meistens noch unterliegen, nicht mehr auftreten. connected because the dents no longer occur even at higher temperatures, to which the wafers in the production process are still mostly subject.
Da die Dellenbildung auch temperaturabhängig ist (da mit steigender Temperatur die Viskosität thermoplastischer Kleber sinkt), kann durch die genannte Erfindung der Temperaturbereich in dem die Wafer prozessiert werden können erweitert werden. Vor allem bei PECVD  Since the dimpling is also temperature-dependent (since the viscosity of thermoplastic adhesive decreases with increasing temperature), the above-mentioned invention makes it possible to extend the temperature range in which the wafers can be processed. Especially at PECVD
Prozessen, in denen höhere Temperaturen verwendet werden und durch die Plasmaeinwirkung zusätzliche thermische Energie in den Wafer eingebracht wird, muss die Dellenbildung vollkommen unterbunden werden. Es konnte bereits nachgewiesen werden, dass genannte Erfindung die Dellenbi ldung tatsächlich unterbindet. Ultradünne Wafer mit dieser Art von gestapelten Strukturen werden meist über 50°C, im speziellen über 75°C und im Besonderen über 100°C prozessiert, womit genannte Erfindung unverzichtbar wird um Dellenbildung zu vermeiden. Processes in which higher temperatures are used and the plasma effect additional thermal energy is introduced into the wafer, the dents must be completely prevented. It has already been demonstrated that said invention actually prevents dicing. Ultrathin wafers with this kind of stacked structures are usually processed above 50 ° C, in particular above 75 ° C and in particular above 100 ° C, whereby said invention is indispensable to prevent dents.
Der Erfindung liegt also der Gedanke zugrunde, die Spannung des dünnen Wafers nach dem Schleifen gezielt einzustellen. Dabei wird der dünne Wafer mittels bekannter Verfahren auf einen Träger montiert. Dieser Trägerwafer kann grundsätzlich aus jedem Matertal mit entsprechenden mechanischen Eigenschaften bestehen. Bevorzugt finden jedoch Silizium, Glas und bestimmte Keramikmaterialien Einsatz. Ein Hauptaugenmerk liegt hier darauf, dass die Trägerwafer einen thermischen The invention is therefore based on the idea to set the voltage of the thin wafer after grinding targeted. In this case, the thin wafer is mounted by means of known methods on a support. This carrier wafer can basically consist of any Matertal with corresponding mechanical properties. However, silicon, glass and certain ceramic materials are preferably used. A main focus here is that the carrier wafers have a thermal
Ausdehnungskoeffizienten haben, der dem des Produkt Wafers (z.B. Silizium) sowohl punktuell als auch hinsichtlich Verlauf des Koeffizienten über den Temperaturbereich angepasst / möglichst identisch ist. Als bevorzugte Ausführungsvariante sei hier erwähnt, dass der Produktwafer mit der bereits prozessierten Seite auf den Trägerwafer unter Verwendung eines thermoplastischen oder zumindest überwiegend thermoplastischen Klebers aufgeklebt wird. Als Beispiel für derartige Kleber sei das HT 10.10 Material von Brewer Science Inc., Rolla, Have expansion coefficient, that of the product wafer (eg Silicon) both pointwise and with respect to the course of the coefficient over the temperature range adapted / identical as possible. As a preferred embodiment, it should be mentioned here that the product wafer with the already processed side is adhered to the carrier wafer using a thermoplastic or at least predominantly thermoplastic adhesive. As an example of such adhesives, the HT 10.10 material from Brewer Science Inc., Rolla,
Missouri, U.S.A. genannt. Anschließend wird der Wafer mittels Missouri, U.S.A. Subsequently, the wafer by means of
Schleifverfahren gedünnt. Dieser Dünnprozess erfolgt aus einem Thinning process thinned. This thin process takes place from a
Zusammenspiel aus Grob- und Feinschleifprozessen. Der entscheidende Teil der Erfindung ist es nun, den Wafer einem geeigneten weiteren Prozess zu unterziehen, der es ermöglicht, die Schicht mit der Interaction of coarse and fine grinding processes. The crucial part of the invention is now to subject the wafer to a suitable further process, which makes it possible to coat the layer with the
beschädigten Kristallstruktur entweder ganz oder kontrolliert teilweise zu entfernen. Im Weiteren wird darauf hingewiesen, dass die Kristallstruktur nicht nur an der Oberfläche, sondern auch bis zu einigen Mikrometer unterhalb der Oberfläche, defekt sein kann, daher die Defekte über eine große Tiefe, insbesondere tiefer als 0.5 μπι, 1 πι,3 μΓη 5 μπι und sogar bis Ι Ομπι, vorhanden sind. Durch die Mittel zur Reduzierung der Damaged crystal structure either completely or partially controlled to remove. It is further pointed out that the crystal structure can be defective not only on the surface but also up to a few micrometers below the surface, therefore the defects over a large depth, in particular lower than 0.5 μm, 1 μm, 3 μm 5 μm and even to Ι Ομπι, are present. By means of reducing the
Eigenspannung wird eine Schichtdicke S abgetragen, deren Wert abhängig von der Produktwaferdicke D des Produktwafers nach dem Rückdünnen bzw. Schleifen des Produktwafers festlegbar ist. Das Verhältnis der Schichtdicke S zu der Produktwaferdicke D liegt dabei zwischen 1 zu 300 und 1 zu 1 0, insbesondere zwischen 1 zu 1 50 und 1 zu 20, vorzugsweise zwischen 1 zu 1 00 und 1 zu 30. Es reicht daher nicht, nur einige Residual stress is removed a layer thickness S whose value can be determined depending on the product wafer thickness D of the product wafer after thinning or grinding of the product wafer. The ratio of the layer thickness S to the product wafer thickness D lies between 1 to 300 and 1 to 10, in particular between 1 to 15 and 1 to 20, preferably between 1 to 100 and 1 to 30. It is therefore not sufficient, only a few
Atomlagen abzutragen um die oberflächennahen Defekte zu entfernen. Ablate atomic layers to remove the near-surface defects.
Bei der teilweisen Entfernung ist es möglich, gezielt den Stress des Wafers einzustellen, und so etwaige Eigenspannungen des Wafers, der zum Beispiel aufgrund der auf der aktiven Seite befindlichen Layer vorhanden sein könnte, zu kompensieren. Damit verwölbt sich der Wafer während nachfolgender Prozesse mit einem hohen thermischen Stress nicht mehr. In the partial removal, it is possible to specifically set the stress of the wafer, and thus any residual stresses of the wafer, for example due to the active side layer could be available to compensate. As a result, the wafer no longer warps during subsequent processes with high thermal stress.
Geeignete Prozesse zur Entfernung dieses beschädigten Layers sind: Suitable processes for removing this damaged layer are:
Polierprozesse. - z.B. Der„Dry Polish Prozess" von Disco  Polishing processes. - e.g. The "Dry Polish Process" by Disco
Nassätzprozesse, die mittels geeigneter Chemikalien durchgeführt werden.  Wet etching processes, which are carried out by means of suitable chemicals.
Trockenätzprozesse  dry etching
Eine Kombination der zuvor genannten Prozesse  A combination of the aforementioned processes
Die Erfindung besteht in einem Prozessfluss, dadurch gekennzeichnet, dass The invention consists in a process flow, characterized in that
• ein Trägerwafer zu einem Strukturwafer über ein Adhäsionsmaterial temporär gebondet wird  • a carrier wafer is temporarily bonded to a structure wafer via an adhesive material
• eine Nachbehandlung des Strukturwafers nach dem Rückdünnen erfolgt  • Post-treatment of the structured wafer after re-thinning
• die Nachbehandlung des Strukturwafers eine Kombination aus  • the post-treatment of the structured wafer is a combination of
Reinigung und mechanisch chemischem Polieren (CMP) ist, dadurch gekennzeichnet, dass beim CMP die durch den Sprödbruch erzeugte Oberflächenrauigkeit, die Risse sowie die eingebauten Eigenspannungen, reduziert bzw. vollständig abgebaut werden Cleaning and mechanical chemical polishing (CMP), characterized in that the surface roughness, the cracks and the built-in residual stresses generated by the brittle fracture, are reduced or completely degraded in CMP
• durch die somit erreichte glattere Oberfläche weniger • less due to the smoother surface achieved
Strukturdefekte vorhanden sind, die bei höheren Temperaturen schließlich als Ausgangspunkt für die oben genannten  Structural defects are present, which at higher temperatures eventually serve as the starting point for the above
Oberflächendefekte (engl.: dimples) dienen.  Serve surface defects (English: dimples).
durch das CMP die Eigenspannungen im Strukturwafer dramatisch geringer sind als in Strukturwafern die durch Grinden gedünnt wurden • durch die geringeren Eigenspannungen ein lokales elastisches Knicken und / oder plastisches Verformen des sehr dünnen the internal stresses in the structure wafer are dramatically lower due to the CMP than in structural wafers thinned by grindings • Due to the lower residual stresses, a local elastic buckling and / or plastic deformation of the very thin
Strukturwafers in die darunterliegende Adhäsionsschicht, vor allem bei höheren Temperaturen, verhindert wird.  Structure wafer is prevented in the underlying adhesive layer, especially at higher temperatures.
• Ohne diese Oberflächendefekte (dimples) die Qualität des  • Without these surface defects (dimples) the quality of the
Strukturwafers extrem erhöht wird.  Structure wafer is extremely increased.
der kontrollierende Faktor 0.5μ, Ι μηι, 3 μηι, 5 μπι und Ι Ομιη the controlling factor 0.5μ, Ι μηι, 3 μηι, 5 μπι and Ι Ομι η
Gemäß einer weiteren Ausführungsform des erfindungsgemäßen According to another embodiment of the invention
Verfahrens werden die Spannungen derart eingestellt, dass ein zukünftig auftretender Stress, verursacht durch Schichten, die später auf den Wafer aufgebracht werden, bereits bei der Einstellung des Stresses mit Method, the voltages are adjusted so that a future occurring stress, caused by layers that are later applied to the wafer, already in the adjustment of stress with
berücksichtigt wird. is taken into account.
Gemäß einer weiteren Ausprägung wird die Spannung so eingestellt, dass sich der Wafer bevorzugt während des thermischen Prozesses zum According to another embodiment, the voltage is adjusted so that the wafer preferably during the thermal process for
Trägerwafer hin wölbt, und damit einem Delaminieren entgegen gewirkt wird. Carrier wafer bulges out, and thus counteract delamination.
Dieses Verfahren ist damit für die Verwendung mit al len bekannten Klebersystemen vorteilhaft. Vortei lhaft kann das Verfahren mit This method is thus advantageous for use with all known adhesive systems. Advantageously, the method can be used with
silikonähnlichen Klebern, die entweder thermisch oder durch UV-Licht- Belichtung vernetzen, eingesetzt werden. M it gleichem Vorteil kann das Verfahren für alle thermisch aushärtenden Kleber eingesetzt werden. Als besonders vorteilhaft erweist sich das Verfahren jedoch in Kombination mit thermoplastischen Klebern, deren Viskosität bei steigender silicone-like adhesives, which crosslink either thermally or by UV light exposure, are used. With the same advantage, the process can be used for all thermosetting adhesives. However, the method proves to be particularly advantageous in combination with thermoplastic adhesives whose viscosity increases with increasing
Temperatur sinkt. Diese Kleber neigten in der Vergangenheit dazu, insbesondere bei Abscheidesystemen, bei denen der Prozess im Vakuum durchgeführt wurde, zu Problemen zu führen. Dies ist dadurch bedingt, da das Aufheizen des dünnen, auf dem Träger montierten Wafers in solchen Systemen besonders ungleichmäßig geschieht, da die Wärme im Temperature drops. In the past, these adhesives have tended to cause problems, particularly in deposition systems where the process has been carried out in a vacuum. This is due to the fact that The heating of the thin wafer mounted on the carrier in such systems is particularly uneven, since the heat in the
Waferstapel überwiegend über Wärmeleitung eingebracht wird. Die Temperatur der dabei verwendeten Chucks bewegt sich im Bereich von 1 00 bis 400°C, insbesondere aber im Bereich von 150 bis 300°C und bevorzugt im Bereich von 1 80 bis 250°C, wo der Wärmetransport durch Wärmestrahlung noch keine so bedeutende Rolle spielt. Daher wird der Waferstapel in diesem Fal l besonders abrupt innerhalb kurzer Zeit, startend beim Kontakt des Waferstapels mit dem Chuck, aufgeheizt. Da der Wafer niemals vollflächig mit dem Chuck in Kontakt ist, erfolgt der Wärmetransfer bevorzugt an jenen Stellen, wo Kontakt herrscht. Waferstapel is introduced mainly via heat conduction. The temperature of the Chucks used moves in the range of 1 00 to 400 ° C, but especially in the range of 150 to 300 ° C and preferably in the range of 1 80 to 250 ° C, where the heat transfer by heat radiation is not so important role plays. Therefore, the wafer stack in this case is heated particularly abruptly within a short time, starting on contact of the wafer stack with the chuck. Since the wafer is never in full contact with the chuck, the heat transfer is preferably at those points where contact prevails.
Weitere Vorteile, Merkmale und Einzelheiten der Erfindung ergeben sich aus der nachfolgenden Beschreibung bevorzugter Ausführungsbeispiele sowie anhand der Zeichnungen; diese zeigen in: Further advantages, features and details of the invention will become apparent from the following description of preferred embodiments and from the drawings; these show in:
Fig. 1 : eine Oberfläche eines temporär gebondeten Produktwafers nach einem Schleifprozess gemäß dem Stand der Technik (C-SAM-Aufnahme), 1 shows a surface of a temporarily bonded product wafer after a grinding process according to the prior art (C-SAM image),
Fig. 2: eine Oberfläche eines temporär gebondeten Produktwafers nach einer Behandlung gemäß der vorliegenden Erfindung (C-SAM-Aufnahme). FIG. 2 shows a surface of a temporarily bonded product wafer after a treatment according to the present invention (C-SAM uptake). FIG.
Die Figuren zeigen, dass der Produktwafer gemäß Figur 1 deutliche Dellen aufweist und Figur 2 ist zu entnehmen, dass ein erfindungsgemäß behandelter Wafer eine wesentlich homogenere Oberflächenstruktur aufweist. Entsprechend hat der Wafer gemäß Figur 2 weniger The figures show that the product wafer according to FIG. 1 has distinct dents, and FIG. 2 shows that a wafer treated according to the invention has a substantially more homogeneous surface structure. Accordingly, the wafer according to FIG. 2 has less
Eigenspannungen. Residual stresses.

Claims

Verfahren zur Behandlung eines temporär gebondeten Produktwafers P aten ta n s p rü c h e Method of treating a temporarily bonded product wafer
1. Verfahren zur Behandlung eines temporär auf einem Trägerwafer gebondeten Produktwafers mit folgenden Schritten: A method of treating a product wafer temporarily bonded to a carrier wafer, comprising the steps of:
Schleifen und/oder Rückdünnen des Produktwafers an einer vom Trägerwafer abgewandten Flachseite auf eine Produktwaferdicke D von < 150μπι, insbesondere < ΙΟΟμπι, vorzugsweise < 75μιη, noch bevorzugter < 50μπι, besonders bevorzugt < 30μηι,  Sanding and / or thinning of the product wafer on a side facing away from the carrier wafer flat side to a product wafer thickness D of <150μπι, in particular <ΙΟΟμπι, preferably <75μιη, more preferably <50μπι, more preferably <30μηι,
- Nach dem Schleifen und/oder Rückdünnen  - After sanding and / or thinning
Oberflächenbehandlung der Flachseite mit Mitteln zum  Surface treatment of the flat side with means for
Reduzieren einer, insbesondere strukturellen, Eigenspannung des Produktwafers. Reduction of, in particular structural, residual stress of the product wafer.
2. Verfahren nach Anspruch 1 , 2. The method according to claim 1,
dadurch gekennzeichnet,  characterized,
dass die Oberflächenbehandlung in einem eigenen, vom  that the surface treatment in its own, from
Rückdünnen, insbesondere räumlich, getrennten, Prozess erfolgt.  Re-thinning, especially spatial, separate, process takes place.
3. Verfahren nach einem der Ansprüche 1 oder 2, 3. The method according to any one of claims 1 or 2,
dadurch gekennzeichnet,  characterized,
dass die Mittel zum Reduzieren der Eigenspannung gekennzeichnet sind durch mindestens eines der nachfolgend aufgeführten  the means for reducing the residual stress are characterized by at least one of the following
Merkmale:  Characteristics:
- Trockenpolieren der Flachseite  - Dry polishing of the flat side
- Nassätzen der Flachseite  - wet etching of the flat side
- Trockenätzen der Flachseite.  - Dry etching of the flat side.
4. Verfahren nach einem der vorhergehenden Ansprüche, 4. The method according to any one of the preceding claims,
dadurch gekennzeichnet,  characterized,
dass die Eigenspannung des Produktwafers durch die Mittel zum Reduzieren der Eigenspannung einstellbar ist.  that the residual stress of the product wafer is adjustable by the means for reducing the residual stress.
5. Verfahren nach einem der vorhergehenden Ansprüche, 5. Method according to one of the preceding claims,
dadurch gekennzeichnet,  characterized,
dass der Trägerwafer, insbesondere bei einer bestimmten und/oder über einen Temperaturbereich der Temperatur des Trägerwafers, einen mit dem Ausdehnungskoeffizienten des Produktwafers im Wesentl ichen identischen Ausdehnungskoeffizienten aufweist. that the carrier wafer, in particular at a certain temperature range and / or over a temperature range of the temperature of the carrier wafer, has an expansion coefficient which is essentially identical to the coefficient of expansion of the product wafer.
6. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, 6. The method according to any one of the preceding claims, characterized
dass der Produktwafer mit seiner der Flachseite  that the product wafer with its the flat side
gegenüberliegenden Kontaktseite unter Verwendung eines  opposite contact side using a
zumindest teilweise, insbesondere überwiegend, thermoplastischen Klebers mit dem Trägerwafer temporär verbunden ist.  at least partially, in particular predominantly, thermoplastic adhesive is temporarily connected to the carrier wafer.
7. Verfahren nach einem der vorhergehenden Ansprüche, 7. The method according to any one of the preceding claims,
dadurch gekennzeichnet,  characterized,
dass die Mittel zur Reduzierung der Eigenspannung derart  that the means for reducing the residual stress in such a way
ausgebildet sind, dass sie eine definierte Schichtdicke S einer, insbesondere durch das Schleifen und/oder Rückdünnen  are formed so that they have a defined layer thickness S one, in particular by grinding and / or thinning back
beschädigten, Kristallstruktur der Flachseite zumindest teilweise entfernen.  damaged, crystal structure of the flat side at least partially remove.
8. Verfahren nach einem der vorhergehenden Ansprüche, 8. The method according to any one of the preceding claims,
dadurch gekennzeichnet,  characterized,
dass die Eigenspannung des Produktwafers durch die Mittel zur Reduzierung der Eigenspannung so eingestellt wird, dass sich der Produktwafer während eines sich anschließenden thermischen Prozesses zum Trägerwafer hin wölbt.  in that the residual stress of the product wafer is adjusted by the means for reducing the residual stress in such a way that the product wafer bulges toward the carrier wafer during a subsequent thermal process.
9. Verfahren nach Anspruch 6, 9. The method according to claim 6,
dadurch gekennzeichnet,  characterized,
dass der Produktwafer der Kontaktseite, insbesondere in den Kleber eingebettete, Topographien aufweist. the product wafer has topographies on the contact side, in particular embedded in the adhesive.
1 0. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, 1 0. A method according to any one of the preceding claims, characterized
dass nach der Oberflächenbehandlung ein thermischer  that after the surface treatment a thermal
Verfahrensschritt, insbesondere bei Temperaturen von >50°C, vorzugsweise >75°C, bevorzugt > 100°C, folgt  Process step, in particular at temperatures of> 50 ° C, preferably> 75 ° C, preferably> 100 ° C, follows
1 1 . Verfahren nach einem der vorhergehenden Ansprüche, 1 1. Method according to one of the preceding claims,
dadurch gekennzeichnet,  characterized,
dass der thermische Verfahrensschritt ein, insbesondere  that the thermal process step, in particular
chemischer, Gasphasenabscheideverfahrensschritt ist.  chemical vapor deposition process step.
1 2. Verfahren nach Anspruch 7, 1 2. The method according to claim 7,
dadurch gekennzeichnet,  characterized,
dass die Schichtdicke S< Ι Ομπι, insbesondere <5μιη, vorzugsweise <3 μηι, noch bevorzugter < 1 μηι, besonders bevorzugt <0,5μηι beträgt.  that the layer thickness S <Ι Ομπι, in particular <5μιη, preferably <3 μηι, more preferably <1 μηι, more preferably <0,5μηι.
1 3. Vorrichtung zur Behandlung eines temporär auf einem Trägerwafer gebondeten Produktwafers mit folgenden Merkmalen: 1 3. Apparatus for treating a product wafer temporarily bonded to a carrier wafer, having the following features:
Mitteln zum Schleifen und/oder Rückdünnen des Produktwafers, Mitteln zum Reduzieren einer, insbesondere strukturellen, Eigenspannung des Produktwafers  Means for grinding and / or thinning the product wafer, means for reducing a, in particular structural, residual stress of the product wafer
14. Vorrichtung zur Ausführung eines Verfahrens nach einem der 14. Apparatus for carrying out a method according to one of
Ansprüche 1 bis 1 1 ,  Claims 1 to 1 1,
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