EP1200970A2 - Vielschichtvaristor niedriger kapazität - Google Patents
Vielschichtvaristor niedriger kapazitätInfo
- Publication number
- EP1200970A2 EP1200970A2 EP00956063A EP00956063A EP1200970A2 EP 1200970 A2 EP1200970 A2 EP 1200970A2 EP 00956063 A EP00956063 A EP 00956063A EP 00956063 A EP00956063 A EP 00956063A EP 1200970 A2 EP1200970 A2 EP 1200970A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- ceramic body
- multilayer
- multilayer varistor
- varistor
- connections
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
- H01C7/18—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material comprising a plurality of layers stacked between terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
- H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
- H01C7/105—Varistor cores
Definitions
- the present invention relates to a multilayer varistor of low capacitance with a ceramic body and two connections which are applied to the ceramic body at a distance from one another.
- Low capacitance should be understood to mean a capacitance value that is in particular less than 10 pF.
- spark gaps have been used for the electrostatic or ESD protection of high-frequency circuits and data lines, which can be implemented, for example, by two opposite ends of a conductor track. If an impermissibly high voltage occurs for a high-frequency circuit or data line to be protected, the spark gap ignites between the two opposite tips of the conductor track, so that this impermissibly high voltage is not applied to the high-frequency circuit or data line.
- the spark gap is ignited in accordance with certain physical laws, in which the so-called gas discharge characteristic curve must be followed. This process takes a certain amount of time, so that the time required to ionize the spark gap alone is generally longer than the rise time of an ESD pulse, which can be of the order of 700 ps.
- multilayer varistors are characterized by a considerably shorter response time: the response time of multilayer varistors is in the order of 500 ps, which is about a factor 2 lower than the response Talk time of spark gaps is. Nevertheless, multilayer varistors have not been used as ESD protection for high-frequency circuits or data lines, which is due to the laminar structure of the multilayer varistors. This laminar structure leads to parasitic capacitances, which makes it impossible to use multilayer varistors in high-frequency circuits with frequencies above 100 MHz. Such high-frequency circuits are, for example, high-frequency input circuits, such as antenna inputs, etc.
- FIG. 13 to 15 show an existing multilayer varistor in perspective (cf. FIG. 13), in section (cf. FIG. 14) or in an overall view with internal electrodes guided outwards (cf. FIG. 15).
- a ceramic body 1 is provided on two opposite sides with connections 8, from each of which internal connections 7 extend, which overlap in the ceramic body 1 at a distance from one another. Active zones 9 are formed in the overlap regions, while 9 isolation zones 11 are formed outside the overlap regions.
- FIG. 15 shows an element of the multilayer varistor from FIG. 14: a layer of the ceramic body 1 is placed between two internal electrodes 7, which each form metallized surfaces 12 on this layer.
- Such existing multilayer varistors are not very suitable as ESD protection for high-frequency circuits and data lines due to their capacitance.
- this capacitance is determined by the area of the inner electrodes 7 or the connections 8, the number of layers of the ceramic body 1 between the inner electrodes 7, that is to say the number of active zones 9, and the number of active zones 9 - th operating voltage resulting thicknesses of the ceramic layers or active zones 9th
- Multi-layer varistors hitherto produced in such technology have capacitances in the order of magnitude of at least 30 to 50 pF, which precludes the use of such multi-layer varistors for the ESD protection of sensitive antenna inputs, for example, despite its low response time.
- This object is achieved according to the invention in the case of a multilayer varistor of low capacitance with a ceramic body and two connections which are applied to the ceramic body at a distance from one another in that the ceramic body is constructed using film technology with a multilayer structure.
- the ceramic body is expediently provided with internal electrodes which emanate from the two connections in a comb-like manner, so that the ends of the electrodes lie opposite one another in the direction between the two connections with a gap (or spacing).
- the inner electrodes are arranged in particular in a comb-like manner, so that the electrodes no longer overlap from the two connections, but rather lie opposite one another with their ends.
- the low capacitance of the multilayer varistor is determined via the distance between these opposite ends of the electrodes, the so-called “gap”. If the gap remains the same or almost the same, the capacity can be further reduced by arranging the gaps in series. In the limit case, even the varistor voltage can be Increase further and decrease the capacity if internal electrodes are completely dispensed with.
- the influence of the connections or external termination on the varistor voltage and the capacitance in this limit case can be eliminated by applying an additional passivation layer, so that with such an embodiment the maximum varistor voltage for a given volume can be achieved with minimal capacitance.
- the inner electrodes can be designed with different electrode lengths. It is also possible to shape the tips of the inner electrodes differently from one another.
- the electrode spacing in the multilayer varistor according to the invention can be increased considerably, which leads to a corresponding reduction in the capacitance.
- the direction of current flow in the multilayer varistor according to the invention is also changed compared to the existing multilayer varistor, and a drastic increase in the varistor voltage is thus made possible.
- the current density profile can be positively influenced by the arrangement of the internal electrodes. It is thus possible to produce a multilayer varistor with a non-linear voltage / current characteristic curve, which is high-resistance at voltages of, for example, 300 V and above.
- 1 is a basic representation of a multilayer varistor in perspective to determine the respective directions
- 2 shows a sectional illustration of a multilayer varistor according to the invention with a comb-like inner electrode arrangement
- Fig. 3 is a sectional view of an inventive
- Fig. 4 is a sectional view of an inventive
- Fig. 5 is a sectional view of an inventive
- Fig. 6 is a sectional view of an inventive
- Fig. 7 is a sectional view of an inventive
- FIG. 8 shows a multilayer varistor with straight electrode tips similar to the embodiment of FIG. 2,
- Fig. 10 shows a section DD through an inventive
- FIG. 11 shows a section DD through an inventive
- Fig. 12 shows a section DD through the invention
- FIG. 1 schematically shows a multilayer varistor with a ceramic body of length 1, width b and height h, in which a current flows in the direction BB between two connections (not shown).
- a direction CC or DD runs perpendicular to the direction BB.
- FIGS. 2 to 8 show schematic sections BB of various exemplary embodiments of the multilayer varistor according to the invention
- FIGS. 9 to 12 show schematic sections DD of the multilayer varistor according to the invention with different electrode tips.
- These different electrode tips can be used especially in a multilayer varistor in accordance with the exemplary embodiments in FIGS. 2 and 8. However, it is also possible to provide such different electrode tips in the exemplary embodiments in FIGS. 3 to 5.
- the multilayer varistor according to the invention is characterized by a multilayer structure in film technology, in which different layers with and without internal electrodes match. are laid differently and form the ceramic body 1, on the two ends of which in the direction BB (see FIG. 1), metallic connections 2, 3 made of aluminum or other materials are applied.
- the connections 2, 3 can be applied, for example, by vapor deposition.
- the second now shows a first exemplary embodiment of the multilayer varistor according to the invention with internal electrodes 4, 5 in a ceramic body 1.
- the internal electrodes 4 are connected to the connection 2, while the internal electrodes 5 are connected to the connection 3.
- the ends of the inner electrodes 4 are provided at a distance or "gap" d from the ends of the inner electrodes 5.
- the inner electrodes 4, 5 are each arranged in a comb-like manner, so that the inner electrodes of the two connections 4, 5 lie opposite one another at the distance d.
- the low capacitance of the multilayer varistor is determined by this distance or gap d.
- the inner electrodes 4, 5 each have the same length. This need not be so. Rather, it is possible to design the inner electrodes 4, 5 with different lengths, as is provided in the exemplary embodiment in FIG. 3.
- the inner electrodes located in the center of the ceramic body 1 have a greater length than the inner electrodes on the edge of the ceramic body 1.
- the capacitance of the multilayer varistor can be further reduced by arranging these gaps in series, as is shown in the exemplary embodiment in FIG. 4.
- the individual gaps between inner electrodes 10 also have the length d; the interior
- electrodes 10 are interrupted several times in the interior of the ceramic body 1, so that only those internal electrodes 10 which adjoin the connections 2, 3 are connected to them, while the remaining internal electrodes are electrically separated from these connections and other internal electrodes, as shown in FIG Fig. 4 is shown.
- a total of four gaps are provided between the inner electrodes 10. This need not necessarily be so: it is also possible to provide more than four or less than four gaps between the individual rows of internal electrodes 10, if necessary.
- FIG. 5 shows a further exemplary embodiment of the multilayer varistor according to the invention, which is similar to the exemplary embodiment of FIG. 4 in that several rows of internal electrodes 10 likewise form a total of four gaps.
- the inner electrodes 10 are arranged at an offset from one another. That is, the inner electrodes 10 of different rows are at a different level in the direction DD. Such a design of the internal electrodes 10 can further reduce the capacitance.
- the varistor voltage can be increased further and the capacitance of the multilayer varistor can be reduced by completely dispensing with internal electrodes, as is shown in the exemplary embodiment in FIG. 6, in which only the connections 2, 3 are applied to the ceramic body 1 in a multilayer structure ,
- What is essential to the invention is the increase in the electrode spacing by dispensing with internal electrodes or by using non-overlapping internal electrodes.
- the resulting change in the direction of current flow in the ceramic body enables a significant increase in the varistor voltage for a given volume to be achieved.
- the capacitance at this volume is greatly reduced, so that capacitance values below 10 pF can be achieved.
- FIG. 8 shows an embodiment which is similar to the embodiment of FIG. 2 in that inner electrodes of the same length are provided. However, this need not necessarily be the case. Rather, it is also possible to provide inner electrodes of different lengths in the embodiment of FIG. 8, as is the case in the embodiment of FIG. 3.
- the internal electrodes 4, 5 can have straight electrode tips (see FIG. 9), concave electrode tips (see FIG. 10), convex electrode tips (see FIG. 11) or “pointed” electrode tips (see FIG. 12) to be provided.
- These different designs of the electrode tips can optionally also be used in the exemplary embodiments of FIGS. 4 and 5, so that here the internal electrodes 10 are to be designed in a similar manner to the internal electrodes 4, 5.
- the course of the current density can be determined by the arrangement of the internal electrodes between the two connections 2, 3 can be influenced favorably, so that a component with a non-linear voltage / current characteristic curve can be produced as a result of the multilayer structure caused by the film technology, which is high-resistance at voltages of approximately 300 V.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Thermistors And Varistors (AREA)
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19931056A DE19931056B4 (de) | 1999-07-06 | 1999-07-06 | Vielschichtvaristor niedriger Kapazität |
DE19931056 | 1999-07-06 | ||
PCT/DE2000/002204 WO2001003148A2 (de) | 1999-07-06 | 2000-07-06 | Vielschichtvaristor niedriger kapazität |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1200970A2 true EP1200970A2 (de) | 2002-05-02 |
EP1200970B1 EP1200970B1 (de) | 2004-10-20 |
Family
ID=7913753
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP00956063A Expired - Lifetime EP1200970B1 (de) | 1999-07-06 | 2000-07-06 | Vielschichtvaristor niedriger kapazität |
Country Status (6)
Country | Link |
---|---|
US (1) | US6608547B1 (de) |
EP (1) | EP1200970B1 (de) |
JP (1) | JP3863777B2 (de) |
AT (1) | ATE280429T1 (de) |
DE (2) | DE19931056B4 (de) |
WO (1) | WO2001003148A2 (de) |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7400477B2 (en) | 1998-08-24 | 2008-07-15 | Leviton Manufacturing Co., Inc. | Method of distribution of a circuit interrupting device with reset lockout and reverse wiring protection |
DE10064447C2 (de) * | 2000-12-22 | 2003-01-02 | Epcos Ag | Elektrisches Vielschichtbauelement und Entstörschaltung mit dem Bauelement |
DE10102201C2 (de) | 2001-01-18 | 2003-05-08 | Epcos Ag | Elektrisches Schaltmodul, Schaltmodulanordnung und verwendung des Schaltmoduls und der Schaltmodulanordnung |
DE10134751C1 (de) * | 2001-07-17 | 2002-10-10 | Epcos Ag | Elektrokeramisches Bauelement |
WO2003030386A1 (de) * | 2001-09-28 | 2003-04-10 | Epcos Ag | Schaltungsanordnung, schaltmodul mit der schaltungsanordnung und verwendung des schaltmoduls |
JP4008881B2 (ja) * | 2001-09-28 | 2007-11-14 | エプコス アクチエンゲゼルシャフト | 回路装置、該回路装置を有するスイッチングモジュール、および該スイッチングモジュールの使用方法 |
US7492565B2 (en) | 2001-09-28 | 2009-02-17 | Epcos Ag | Bandpass filter electrostatic discharge protection device |
WO2003030383A1 (de) * | 2001-09-28 | 2003-04-10 | Epcos Ag | Schaltungsanordnung, schaltmodul mit der schaltungsanordnung und verwendung des schaltmoduls |
US20050059371A1 (en) * | 2001-09-28 | 2005-03-17 | Christian Block | Circuit arrangement, switching module comprising said circuit arrangement and use of switching module |
WO2003030384A1 (de) * | 2001-09-28 | 2003-04-10 | Epcos Ag | Schaltungsanordnung, schaltmodul mit der schaltungsanordnung und verwendung des schaltmoduls |
WO2003030385A1 (de) * | 2001-09-28 | 2003-04-10 | Epcos Ag | Schaltungsanordnung, schaltmodul mit der schaltungsanordnung und verwendung des schaltmoduls |
DE10202915A1 (de) * | 2002-01-25 | 2003-08-21 | Epcos Ag | Elektrokeramisches Bauelement mit Innenelektroden |
DE10235011A1 (de) * | 2002-07-31 | 2004-02-26 | Epcos Ag | Elektrisches Vielschichtbauelement |
DE10246098A1 (de) * | 2002-10-02 | 2004-04-22 | Epcos Ag | Schaltungsanordnung |
DE10313891A1 (de) | 2003-03-27 | 2004-10-14 | Epcos Ag | Elektrisches Vielschichtbauelement |
JP2005203479A (ja) * | 2004-01-14 | 2005-07-28 | Matsushita Electric Ind Co Ltd | 静電気対策部品 |
US20050212648A1 (en) * | 2004-03-23 | 2005-09-29 | Inpaq Technology Co., Ltd. | Low-capacitance laminate varistor |
DE102004031878B3 (de) * | 2004-07-01 | 2005-10-06 | Epcos Ag | Elektrisches Mehrschichtbauelement mit zuverlässigem Lötkontakt |
DE102004058410B4 (de) | 2004-12-03 | 2021-02-18 | Tdk Electronics Ag | Vielschichtbauelement mit ESD-Schutzelementen |
DE102005016590A1 (de) * | 2005-04-11 | 2006-10-26 | Epcos Ag | Elektrisches Mehrschicht-Bauelement und Verfahren zur Herstellung eines Mehrschicht-Bauelements |
DE102005028498B4 (de) * | 2005-06-20 | 2015-01-22 | Epcos Ag | Elektrisches Vielschichtbauelement |
DE102005050638B4 (de) | 2005-10-20 | 2020-07-16 | Tdk Electronics Ag | Elektrisches Bauelement |
DE102007020783A1 (de) | 2007-05-03 | 2008-11-06 | Epcos Ag | Elektrisches Vielschichtbauelement |
WO2008146514A1 (ja) * | 2007-05-28 | 2008-12-04 | Murata Manufacturing Co., Ltd. | Esd保護デバイス |
JP2008311362A (ja) * | 2007-06-13 | 2008-12-25 | Tdk Corp | セラミック電子部品 |
DE102007031510A1 (de) | 2007-07-06 | 2009-01-08 | Epcos Ag | Elektrisches Vielschichtbauelement |
US7697252B2 (en) * | 2007-08-15 | 2010-04-13 | Leviton Manufacturing Company, Inc. | Overvoltage device with enhanced surge suppression |
CN101910856B (zh) | 2008-01-29 | 2014-06-18 | 立维腾制造有限公司 | 自测试故障电路中断器装置和方法 |
DE102009010212B4 (de) * | 2009-02-23 | 2017-12-07 | Epcos Ag | Elektrisches Vielschichtbauelement |
DE102010036270B4 (de) | 2010-09-03 | 2018-10-11 | Epcos Ag | Keramisches Bauelement und Verfahren zur Herstellung eines keramischen Bauelements |
DE102010044856A1 (de) * | 2010-09-09 | 2012-03-15 | Epcos Ag | Widerstandsbauelement und Verfahren zur Herstellung eines Widerstandsbauelements |
US9786437B1 (en) | 2010-12-10 | 2017-10-10 | Presidio Components, Inc. | High voltage fringe-effect capacitor |
US8599522B2 (en) | 2011-07-29 | 2013-12-03 | Leviton Manufacturing Co., Inc. | Circuit interrupter with improved surge suppression |
DE102012101606A1 (de) * | 2011-10-28 | 2013-05-02 | Epcos Ag | ESD-Schutzbauelement und Bauelement mit einem ESD-Schutzbauelement und einer LED |
DE102013102686A1 (de) * | 2013-03-15 | 2014-09-18 | Epcos Ag | Elektronisches Bauelement |
US9759758B2 (en) | 2014-04-25 | 2017-09-12 | Leviton Manufacturing Co., Inc. | Ground fault detector |
DE102016100352A1 (de) * | 2016-01-11 | 2017-07-13 | Epcos Ag | Bauelementträger mit ESD Schutzfunktion und Verfahren zur Herstellung |
DE102016108604A1 (de) * | 2016-05-10 | 2017-11-16 | Epcos Ag | Vielschichtbauelement und Verfahren zur Herstellung eines Vielschichtbauelements |
KR102556495B1 (ko) | 2018-03-05 | 2023-07-17 | 교세라 에이브이엑스 컴포넌츠 코포레이션 | 에너지 처리 용량이 향상된 케스케이드 바리스터 |
DE102018115085B4 (de) * | 2018-06-22 | 2021-03-25 | Tdk Electronics Ag | Keramisches Vielschichtbauelement und Verfahren zur Herstellung eines keramischen Vielschichtbauelements |
WO2020018651A1 (en) | 2018-07-18 | 2020-01-23 | Avx Corporation | Varistor passivation layer and method of making the same |
WO2020018746A1 (en) * | 2018-07-18 | 2020-01-23 | Hubbell Incorporated | Voltage-dependent resistor device for protecting a plurality of conductors against a power surge |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3857174A (en) | 1973-09-27 | 1974-12-31 | Gen Electric | Method of making varistor with passivating coating |
US4460623A (en) * | 1981-11-02 | 1984-07-17 | General Electric Company | Method of varistor capacitance reduction by boron diffusion |
EP0189087B1 (de) | 1985-01-17 | 1988-06-22 | Siemens Aktiengesellschaft | Spannungsabhängiger elektrischer Widerstand (Varistor) |
JP2800896B2 (ja) * | 1987-09-07 | 1998-09-21 | 株式会社村田製作所 | 電圧非直線抵抗体 |
JP2833242B2 (ja) * | 1991-03-12 | 1998-12-09 | 株式会社村田製作所 | Ntcサーミスタ素子 |
JPH0634201A (ja) * | 1992-07-17 | 1994-02-08 | Matsushita Electric Ind Co Ltd | 温風発生装置 |
JP3632860B2 (ja) * | 1993-04-23 | 2005-03-23 | Tdk株式会社 | Ntcサーミスタ |
DE4334059A1 (de) * | 1993-10-06 | 1995-04-13 | Philips Patentverwaltung | Schichtverbundfolie, Mehrfarbensiebdruckverfahren zu ihrer Herstellung und ihre Verwendung |
JPH0727140U (ja) * | 1993-10-15 | 1995-05-19 | 住友金属工業株式会社 | 積層チップコンデンサ |
JP3179313B2 (ja) * | 1995-05-31 | 2001-06-25 | 松下電器産業株式会社 | 電子部品の製造方法 |
JPH08236308A (ja) * | 1995-02-22 | 1996-09-13 | Murata Mfg Co Ltd | セラミック電子部品とその特性値調整方法 |
JPH09205005A (ja) * | 1996-01-24 | 1997-08-05 | Matsushita Electric Ind Co Ltd | 電子部品とその製造方法 |
JPH1070012A (ja) * | 1996-06-03 | 1998-03-10 | Matsushita Electric Ind Co Ltd | バリスタの製造方法 |
DE19634498C2 (de) | 1996-08-26 | 1999-01-28 | Siemens Matsushita Components | Elektro-keramisches Bauelement und Verfahren zu seiner Herstellung |
JPH10199709A (ja) * | 1997-01-09 | 1998-07-31 | Tdk Corp | 積層型バリスタ |
JPH10223408A (ja) * | 1997-01-31 | 1998-08-21 | Taiyo Yuden Co Ltd | チップ状回路部品とその製造方法 |
JP3393524B2 (ja) * | 1997-03-04 | 2003-04-07 | 株式会社村田製作所 | Ntcサーミスタ素子 |
TW394961B (en) * | 1997-03-20 | 2000-06-21 | Ceratech Corp | Low capacitance chip varistor and fabrication method thereof |
JPH1131602A (ja) * | 1997-07-10 | 1999-02-02 | Tama Electric Co Ltd | チップ部品 |
JPH11126704A (ja) * | 1997-10-23 | 1999-05-11 | Matsushita Electric Ind Co Ltd | 積層型チップサーミスタ |
JP2840834B2 (ja) | 1997-12-22 | 1998-12-24 | 株式会社村田製作所 | Ntcサーミスタ素子 |
JPH11191506A (ja) * | 1997-12-25 | 1999-07-13 | Murata Mfg Co Ltd | 積層型バリスタ |
JPH11204309A (ja) * | 1998-01-09 | 1999-07-30 | Tdk Corp | 積層型バリスタ |
JPH11273914A (ja) * | 1998-03-26 | 1999-10-08 | Murata Mfg Co Ltd | 積層型バリスタ |
-
1999
- 1999-07-06 DE DE19931056A patent/DE19931056B4/de not_active Expired - Fee Related
-
2000
- 2000-07-06 WO PCT/DE2000/002204 patent/WO2001003148A2/de active IP Right Grant
- 2000-07-06 AT AT00956063T patent/ATE280429T1/de not_active IP Right Cessation
- 2000-07-06 JP JP2001508465A patent/JP3863777B2/ja not_active Expired - Lifetime
- 2000-07-06 DE DE50008343T patent/DE50008343D1/de not_active Expired - Lifetime
- 2000-07-06 US US10/019,523 patent/US6608547B1/en not_active Expired - Fee Related
- 2000-07-06 EP EP00956063A patent/EP1200970B1/de not_active Expired - Lifetime
Non-Patent Citations (1)
Title |
---|
See references of WO0103148A2 * |
Also Published As
Publication number | Publication date |
---|---|
EP1200970B1 (de) | 2004-10-20 |
DE50008343D1 (de) | 2004-11-25 |
DE19931056B4 (de) | 2005-05-19 |
DE19931056A1 (de) | 2001-01-25 |
WO2001003148A3 (de) | 2001-07-19 |
ATE280429T1 (de) | 2004-11-15 |
WO2001003148A2 (de) | 2001-01-11 |
US6608547B1 (en) | 2003-08-19 |
JP2004507069A (ja) | 2004-03-04 |
JP3863777B2 (ja) | 2006-12-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1200970B1 (de) | Vielschichtvaristor niedriger kapazität | |
EP2143117B1 (de) | Elektrisches vielschichtbauelement mit elektrisch nicht kontaktierter abschirmstruktur | |
EP2614508B1 (de) | Widerstandsbauelement und verfahren zur herstellung eines widerstandsbauelements | |
DE3408216A1 (de) | Spannungsbegrenzende durchfuehrung | |
EP1350257B1 (de) | Elektrisches vielschichtbauelement und entstörschaltung mit dem bauelement | |
DE19628890A1 (de) | Elektronikteile mit eingebauten Induktoren | |
DE2848508C2 (de) | Flüssigkristall-Anzeigetafel | |
EP2756509B1 (de) | Vielschichtbauelement und verfahren zu dessen herstellung | |
DE69823637T2 (de) | Laminat-Varistor | |
EP1369880B1 (de) | Elektrisches Vielschichtbauelement und Schaltungsanordnung | |
EP1880399B1 (de) | Elektrisches durchführungsbauelement | |
DE4121888C2 (de) | IC-Karte | |
EP1391898B1 (de) | Elektrisches Vielschichtbauelement | |
EP1560235B1 (de) | Elektrisches Vielschichtbauelement | |
EP1538641B1 (de) | Elektrisches Bauelement und Schaltungsanordnung | |
DE102011014967B4 (de) | Elektrisches Vielschichtbauelement | |
DE19958484A1 (de) | Mehrfach-Filter | |
EP2465123B1 (de) | Elektrisches vielschichtbauelement | |
DE10045195B4 (de) | Thermistor und Verfahren zu dessen Herstellung | |
DE2439581C2 (de) | Abgleichbarer Schichtkondensator | |
DE102016218478B4 (de) | Symmetrischer Spannungsteiler | |
DE112020005494T5 (de) | Varistor | |
DE2246573B2 (de) | Abgleichbarer Schichtkondensator | |
WO2003009311A1 (de) | Elektrokeramisches bauelement | |
DE4131623A1 (de) | Bandleiterlaser |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 20011115 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: EPCOS AG |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRE;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.SCRIBED TIME-LIMIT Effective date: 20041020 Ref country code: IE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20041020 Ref country code: NL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20041020 Ref country code: FI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20041020 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D Free format text: NOT ENGLISH |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: EP |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D Free format text: GERMAN |
|
REF | Corresponds to: |
Ref document number: 50008343 Country of ref document: DE Date of ref document: 20041125 Kind code of ref document: P |
|
GBT | Gb: translation of ep patent filed (gb section 77(6)(a)/1977) | ||
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20050120 Ref country code: DK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20050120 Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20050120 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: ES Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20050131 |
|
NLV1 | Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents act | ||
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FD4D |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20050706 Ref country code: AT Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20050706 Ref country code: CY Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20050706 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LI Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20050731 Ref country code: MC Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20050731 Ref country code: BE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20050731 Ref country code: CH Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20050731 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
ET | Fr: translation filed | ||
26N | No opposition filed |
Effective date: 20050721 |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
BERE | Be: lapsed |
Owner name: *EPCOS A.G. Effective date: 20050731 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: PT Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20050320 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 17 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 18 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 19 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R082 Ref document number: 50008343 Country of ref document: DE Representative=s name: EPPING HERMANN FISCHER PATENTANWALTSGESELLSCHA, DE Ref country code: DE Ref legal event code: R081 Ref document number: 50008343 Country of ref document: DE Owner name: TDK ELECTRONICS AG, DE Free format text: FORMER OWNER: EPCOS AG, 81669 MUENCHEN, DE |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20190724 Year of fee payment: 20 Ref country code: DE Payment date: 20190723 Year of fee payment: 20 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20190725 Year of fee payment: 20 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R071 Ref document number: 50008343 Country of ref document: DE |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: PE20 Expiry date: 20200705 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION Effective date: 20200705 |