DE69810489T2 - Kostengünstiges, hochparalleles speicherprüfgerät - Google Patents

Kostengünstiges, hochparalleles speicherprüfgerät

Info

Publication number
DE69810489T2
DE69810489T2 DE69810489T DE69810489T DE69810489T2 DE 69810489 T2 DE69810489 T2 DE 69810489T2 DE 69810489 T DE69810489 T DE 69810489T DE 69810489 T DE69810489 T DE 69810489T DE 69810489 T2 DE69810489 T2 DE 69810489T2
Authority
DE
Germany
Prior art keywords
speed port
testing
inexpensive
highly parallel
parallel storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69810489T
Other languages
English (en)
Other versions
DE69810489D1 (de
Inventor
W Conner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teradyne Inc
Original Assignee
Teradyne Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teradyne Inc filed Critical Teradyne Inc
Application granted granted Critical
Publication of DE69810489D1 publication Critical patent/DE69810489D1/de
Publication of DE69810489T2 publication Critical patent/DE69810489T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration
DE69810489T 1997-09-09 1998-09-04 Kostengünstiges, hochparalleles speicherprüfgerät Expired - Fee Related DE69810489T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/926,117 US5794175A (en) 1997-09-09 1997-09-09 Low cost, highly parallel memory tester
PCT/US1998/018602 WO1999013475A1 (en) 1997-09-09 1998-09-04 Low cost, highly parallel memory tester

Publications (2)

Publication Number Publication Date
DE69810489D1 DE69810489D1 (de) 2003-02-06
DE69810489T2 true DE69810489T2 (de) 2003-10-30

Family

ID=25452781

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69810489T Expired - Fee Related DE69810489T2 (de) 1997-09-09 1998-09-04 Kostengünstiges, hochparalleles speicherprüfgerät

Country Status (6)

Country Link
US (1) US5794175A (de)
EP (1) EP1012849B1 (de)
JP (1) JP4937448B2 (de)
KR (1) KR100371953B1 (de)
DE (1) DE69810489T2 (de)
WO (1) WO1999013475A1 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19928981B4 (de) * 1998-06-24 2006-07-13 Advantest Corp. Vorrichtung und Verfahren zum Testen von Halbleiterspeichern
DE102007016622A1 (de) * 2007-04-05 2008-10-09 Qimonda Ag Halbleiter-Bauelement-Test-Verfahren und -Test-System mit reduzierter Anzahl an Test-Kanälen

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KR100216993B1 (ko) * 1997-07-11 1999-09-01 윤종용 병합 데이터 출력모드와 표준동작 모드로 동작하는 집적회로소자를 함께 검사할 수 있는 검사용 기판
DE19808664C2 (de) * 1998-03-02 2002-03-14 Infineon Technologies Ag Integrierte Schaltung und Verfahren zu ihrer Prüfung
US5991215A (en) * 1998-03-31 1999-11-23 Micron Electronics, Inc. Method for testing a memory chip in multiple passes
US6058055A (en) * 1998-03-31 2000-05-02 Micron Electronics, Inc. System for testing memory
JP4026945B2 (ja) * 1998-08-11 2007-12-26 株式会社アドバンテスト 混在ｉｃ試験装置及びこのｉｃ試験装置の制御方法
JP4018254B2 (ja) * 1998-08-20 2007-12-05 株式会社アドバンテスト 電子部品の試験方法
US6275962B1 (en) * 1998-10-23 2001-08-14 Teradyne, Inc. Remote test module for automatic test equipment
US6389525B1 (en) 1999-01-08 2002-05-14 Teradyne, Inc. Pattern generator for a packet-based memory tester
US6357018B1 (en) * 1999-01-26 2002-03-12 Dell Usa, L.P. Method and apparatus for determining continuity and integrity of a RAMBUS channel in a computer system
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JP3918344B2 (ja) * 1999-01-29 2007-05-23 横河電機株式会社 半導体試験装置
US6480978B1 (en) * 1999-03-01 2002-11-12 Formfactor, Inc. Parallel testing of integrated circuit devices using cross-DUT and within-DUT comparisons
US6452411B1 (en) 1999-03-01 2002-09-17 Formfactor, Inc. Efficient parallel testing of integrated circuit devices using a known good device to generate expected responses
US6499121B1 (en) * 1999-03-01 2002-12-24 Formfactor, Inc. Distributed interface for parallel testing of multiple devices using a single tester channel
DE19917336C2 (de) * 1999-04-16 2002-07-11 Infineon Technologies Ag Schaltungsanordnung zum Burn-In-Test eines Halbleiterbausteins
US6347287B1 (en) * 1999-05-07 2002-02-12 International Business Machines Corporation Calibration system and method for receiver guardband reductions
KR100574479B1 (ko) * 1999-06-23 2006-04-27 주식회사 하이닉스반도체 램버스 디램의 테스트장치
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DE10131712B4 (de) * 2001-06-29 2009-04-09 Qimonda Ag Elektronisches Bauelement, Testereinrichtung und Verfahren zur Kalibrierung einer Testereinrichtung
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JP4173726B2 (ja) * 2002-12-17 2008-10-29 株式会社ルネサステクノロジ インターフェイス回路
KR100505686B1 (ko) * 2003-05-26 2005-08-03 삼성전자주식회사 다수의 피시험 소자들을 병렬로 검사하는 테스트 시스템및 테스트 방법
JP4334285B2 (ja) * 2003-06-19 2009-09-30 株式会社アドバンテスト 半導体試験装置及びその制御方法
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DE10350356B3 (de) * 2003-10-29 2005-02-17 Infineon Technologies Ag Integrierte Schaltung, Testsystem und Verfahren zum Auslesen eines Fehlerdatums aus der integrierten Schaltung
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DE102007016622A1 (de) * 2007-04-05 2008-10-09 Qimonda Ag Halbleiter-Bauelement-Test-Verfahren und -Test-System mit reduzierter Anzahl an Test-Kanälen

Also Published As

Publication number Publication date
KR20010023804A (ko) 2001-03-26
KR100371953B1 (ko) 2003-02-14
JP4937448B2 (ja) 2012-05-23
EP1012849B1 (de) 2003-01-02
WO1999013475A1 (en) 1999-03-18
US5794175A (en) 1998-08-11
JP2001516121A (ja) 2001-09-25
DE69810489D1 (de) 2003-02-06
EP1012849A1 (de) 2000-06-28

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