DE69604592D1 - Speicherprüfgerät zur schnellreparatur von halbleiterspeicherchips - Google Patents

Speicherprüfgerät zur schnellreparatur von halbleiterspeicherchips

Info

Publication number
DE69604592D1
DE69604592D1 DE69604592T DE69604592T DE69604592D1 DE 69604592 D1 DE69604592 D1 DE 69604592D1 DE 69604592 T DE69604592 T DE 69604592T DE 69604592 T DE69604592 T DE 69604592T DE 69604592 D1 DE69604592 D1 DE 69604592D1
Authority
DE
Germany
Prior art keywords
test device
quick repair
semiconductor memory
memory chips
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69604592T
Other languages
English (en)
Other versions
DE69604592T2 (de
Inventor
Michael Chester
Steven Michaelson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teradyne Inc
Original Assignee
Teradyne Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teradyne Inc filed Critical Teradyne Inc
Publication of DE69604592D1 publication Critical patent/DE69604592D1/de
Application granted granted Critical
Publication of DE69604592T2 publication Critical patent/DE69604592T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
DE69604592T 1995-08-18 1996-08-08 Speicherprüfgerät zur schnellreparatur von halbleiterspeicherchips Expired - Fee Related DE69604592T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/516,709 US5795797A (en) 1995-08-18 1995-08-18 Method of making memory chips using memory tester providing fast repair
PCT/US1996/012894 WO1997007459A1 (en) 1995-08-18 1996-08-08 Memory tester providing fast repair of memory chips

Publications (2)

Publication Number Publication Date
DE69604592D1 true DE69604592D1 (de) 1999-11-11
DE69604592T2 DE69604592T2 (de) 2000-05-11

Family

ID=24056777

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69604592T Expired - Fee Related DE69604592T2 (de) 1995-08-18 1996-08-08 Speicherprüfgerät zur schnellreparatur von halbleiterspeicherchips

Country Status (6)

Country Link
US (1) US5795797A (de)
EP (1) EP0845122B1 (de)
JP (1) JP3871714B2 (de)
KR (1) KR100413918B1 (de)
DE (1) DE69604592T2 (de)
WO (1) WO1997007459A1 (de)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6094733A (en) 1996-01-25 2000-07-25 Kabushiki Kaisha Toshiba Method for testing semiconductor memory devices, and apparatus and system for testing semiconductor memory devices
US6154851A (en) * 1997-08-05 2000-11-28 Micron Technology, Inc. Memory repair
US6178549B1 (en) * 1998-03-12 2001-01-23 Winbond Electronics Corporation Memory writer with deflective memory-cell handling capability
US6442724B1 (en) 1999-04-02 2002-08-27 Teradyne, Inc. Failure capture apparatus and method for automatic test equipment
US6327680B1 (en) * 1999-05-20 2001-12-04 International Business Machines Corporation Method and apparatus for array redundancy repair detection
US6536005B1 (en) 1999-10-26 2003-03-18 Teradyne, Inc. High-speed failure capture apparatus and method for automatic test equipment
US6256757B1 (en) * 2000-01-24 2001-07-03 Credence Systems Corporation Apparatus for testing memories with redundant storage elements
JP2001267389A (ja) 2000-03-21 2001-09-28 Hiroshima Nippon Denki Kk 半導体メモリ生産システム及び半導体メモリ生産方法
US6499118B1 (en) * 2000-05-17 2002-12-24 Teradyne, Inc. Redundancy analysis method and apparatus for ATE
US6795942B1 (en) * 2000-07-06 2004-09-21 Lsi Logic Corporation Built-in redundancy analysis for memories with row and column repair
GB2370380B (en) 2000-12-19 2003-12-31 Picochip Designs Ltd Processor architecture
US6373758B1 (en) * 2001-02-23 2002-04-16 Hewlett-Packard Company System and method of operating a programmable column fail counter for redundancy allocation
US6862703B2 (en) * 2001-08-13 2005-03-01 Credence Systems Corporation Apparatus for testing memories with redundant storage elements
US6717869B2 (en) * 2002-04-25 2004-04-06 D.S.P. Group Ltd. Integrated circuit having redundant, self-organized architecture for improving yield
GB2391083B (en) * 2002-07-19 2006-03-01 Picochip Designs Ltd Processor array
US7003704B2 (en) * 2002-11-12 2006-02-21 International Business Machines Corporation Two-dimensional redundancy calculation
US7509543B2 (en) 2003-06-17 2009-03-24 Micron Technology, Inc. Circuit and method for error test, recordation, and repair
US7437632B2 (en) * 2003-06-24 2008-10-14 Micron Technology, Inc. Circuits and methods for repairing defects in memory devices
TW594881B (en) * 2003-07-01 2004-06-21 Au Optronics Corp Method of repairing thin film transistor circuit on display panel by local thin film deposition
US20080270854A1 (en) 2007-04-24 2008-10-30 Micron Technology, Inc. System and method for running test and redundancy analysis in parallel
GB2454865B (en) 2007-11-05 2012-06-13 Picochip Designs Ltd Power control
GB2470037B (en) 2009-05-07 2013-07-10 Picochip Designs Ltd Methods and devices for reducing interference in an uplink
GB2470771B (en) 2009-06-05 2012-07-18 Picochip Designs Ltd A method and device in a communication network
GB2470891B (en) 2009-06-05 2013-11-27 Picochip Designs Ltd A method and device in a communication network
GB2474071B (en) 2009-10-05 2013-08-07 Picochip Designs Ltd Femtocell base station
GB2482869B (en) 2010-08-16 2013-11-06 Picochip Designs Ltd Femtocell access control
US8947957B2 (en) * 2010-09-22 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. Built-in self repair for memory
GB2489919B (en) 2011-04-05 2018-02-14 Intel Corp Filter
GB2489716B (en) 2011-04-05 2015-06-24 Intel Corp Multimode base system
GB2491098B (en) 2011-05-16 2015-05-20 Intel Corp Accessing a base station
US11360840B2 (en) 2020-01-20 2022-06-14 Samsung Electronics Co., Ltd. Method and apparatus for performing redundancy analysis of a semiconductor device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4414665A (en) * 1979-11-21 1983-11-08 Nippon Telegraph & Telephone Public Corp. Semiconductor memory device test apparatus
US4736373A (en) * 1981-08-03 1988-04-05 Pacific Western Systems, Inc. Memory tester having concurrent failure data readout and memory repair analysis
JPS59180898A (ja) * 1983-03-31 1984-10-15 Hitachi Ltd 不良ビット救済方法
DE3482901D1 (de) * 1983-05-11 1990-09-13 Hitachi Ltd Pruefgeraet fuer redundanzspeicher.
US4639915A (en) * 1983-10-06 1987-01-27 Eaton Corporation High speed redundancy processor
US4876685A (en) * 1987-06-08 1989-10-24 Teradyne, Inc. Failure information processing in automatic memory tester
JPH04177700A (ja) * 1990-11-13 1992-06-24 Toshiba Corp メモリ不良解析装置
US5514628A (en) * 1995-05-26 1996-05-07 Texas Instruments Incorporated Two-step sinter method utilized in conjunction with memory cell replacement by redundancies

Also Published As

Publication number Publication date
JP3871714B2 (ja) 2007-01-24
EP0845122B1 (de) 1999-10-06
DE69604592T2 (de) 2000-05-11
US5795797A (en) 1998-08-18
KR100413918B1 (ko) 2004-02-18
JPH11511287A (ja) 1999-09-28
EP0845122A1 (de) 1998-06-03
KR19990037714A (ko) 1999-05-25
WO1997007459A1 (en) 1997-02-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee