DE69419951D1 - Halbleiterspeicher mit eingebauter Einbrennprüfung - Google Patents

Halbleiterspeicher mit eingebauter Einbrennprüfung

Info

Publication number
DE69419951D1
DE69419951D1 DE69419951T DE69419951T DE69419951D1 DE 69419951 D1 DE69419951 D1 DE 69419951D1 DE 69419951 T DE69419951 T DE 69419951T DE 69419951 T DE69419951 T DE 69419951T DE 69419951 D1 DE69419951 D1 DE 69419951D1
Authority
DE
Germany
Prior art keywords
burn
built
test
semiconductor memory
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69419951T
Other languages
English (en)
Other versions
DE69419951T2 (de
Inventor
Takashi Ohsawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69419951D1 publication Critical patent/DE69419951D1/de
Publication of DE69419951T2 publication Critical patent/DE69419951T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage
DE69419951T 1993-03-10 1994-01-03 Halbleiterspeicher mit eingebauter Einbrennprüfung Expired - Fee Related DE69419951T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5049699A JP2885597B2 (ja) 1993-03-10 1993-03-10 半導体メモリ

Publications (2)

Publication Number Publication Date
DE69419951D1 true DE69419951D1 (de) 1999-09-16
DE69419951T2 DE69419951T2 (de) 1999-12-23

Family

ID=12838434

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69419951T Expired - Fee Related DE69419951T2 (de) 1993-03-10 1994-01-03 Halbleiterspeicher mit eingebauter Einbrennprüfung

Country Status (5)

Country Link
US (1) US5424990A (de)
EP (1) EP0615253B1 (de)
JP (1) JP2885597B2 (de)
KR (1) KR970001202B1 (de)
DE (1) DE69419951T2 (de)

Families Citing this family (32)

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US5440524A (en) * 1994-02-01 1995-08-08 Integrated Device Technology, Inc. Method and apparatus for simuilataneous long writes of multiple cells of a row in a static ram
JPH0887887A (ja) * 1994-09-17 1996-04-02 Toshiba Corp 半導体記憶装置
US5917766A (en) * 1996-05-28 1999-06-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device that can carry out read disturb testing and burn-in testing reliably
US5841714A (en) * 1996-10-21 1998-11-24 Micron Technology, Inc. Supervoltage circuit
KR100240883B1 (ko) * 1997-02-06 2000-01-15 윤종용 Cmos sram 장치
JP3660783B2 (ja) * 1997-06-30 2005-06-15 松下電器産業株式会社 半導体集積回路
US5999466A (en) * 1998-01-13 1999-12-07 Micron Technology, Inc. Method, apparatus and system for voltage screening of integrated circuits
JP3259679B2 (ja) * 1998-03-23 2002-02-25 日本電気株式会社 半導体メモリバーンインテスト回路
KR100281900B1 (ko) * 1998-09-08 2001-02-15 윤종용 개선된 웨이퍼 번인 테스트 스킴을 갖는 반도체 메모리장치
JP4266254B2 (ja) * 1999-07-19 2009-05-20 株式会社ルネサステクノロジ 半導体記憶装置
JP2001143497A (ja) * 1999-11-17 2001-05-25 Hitachi Ltd 半導体記憶装置
DE10014388A1 (de) 2000-03-23 2001-10-04 Infineon Technologies Ag Verfahren zur Durchführung eines Burn-in-Prozesses eines Speichers
KR100390738B1 (ko) * 2000-06-07 2003-07-12 가부시끼가이샤 도시바 반도체 메모리 집적 회로
JP4184586B2 (ja) * 2000-09-28 2008-11-19 株式会社東芝 半導体記憶装置
US6449200B1 (en) 2001-07-17 2002-09-10 International Business Machines Corporation Duty-cycle-efficient SRAM cell test
US6510091B1 (en) 2001-08-01 2003-01-21 International Business Machines Corporation Dynamic precharge decode scheme for fast DRAM
JP4022392B2 (ja) * 2001-12-11 2007-12-19 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置およびそのテスト方法並びにテスト回路
KR100470997B1 (ko) * 2002-04-26 2005-03-10 삼성전자주식회사 웨이퍼 번인 테스트에 사용하기 적합한 전압 발생기제어방법 및 전압 발생기의 동작제어를 위한 제어회로를갖는 반도체 메모리 장치
KR100513365B1 (ko) 2002-12-30 2005-09-07 주식회사 하이닉스반도체 어드레스 카운터 스트로브 테스트 모드 장치
KR100505711B1 (ko) * 2003-09-30 2005-08-03 삼성전자주식회사 칼럼 선택 신호 제어 방법 및 칼럼 선택 신호 제어 회로
JP4207017B2 (ja) 2004-08-10 2009-01-14 セイコーエプソン株式会社 電気光学装置用基板及びその検査方法、並びに電気光学装置及び電子機器
DE102004044150B4 (de) * 2004-09-13 2011-08-18 Qimonda AG, 81739 Verbesserte künstliche Alterung von Chips mit Speicher
US20080285358A1 (en) * 2007-05-15 2008-11-20 Qimonda North America Corp. Method and circuit for stressing upper level interconnects in semiconductor devices
JP5352077B2 (ja) * 2007-11-12 2013-11-27 ルネサスエレクトロニクス株式会社 半導体集積回路
JP5195393B2 (ja) * 2008-12-19 2013-05-08 富士通セミコンダクター株式会社 半導体メモリ、半導体メモリの製造方法および半導体メモリの試験方法
US8611164B2 (en) 2011-08-01 2013-12-17 International Business Machines Corporation Device and method for detecting resistive defect
US9852783B1 (en) * 2016-09-23 2017-12-26 Qualcomm Technologies, Inc. Metal-oxide semiconductor (MOS) transistor offset-cancelling (OC), zero-sensing (ZS) dead zone, current-latched sense amplifiers (SAs) (CLSAs) (OCZS-SAs) for sensing differential voltages
KR102652802B1 (ko) 2016-11-01 2024-04-01 에스케이하이닉스 주식회사 웨이퍼 번인 테스트 회로 및 이를 포함하는 반도체 장치
US11202939B2 (en) 2017-04-24 2021-12-21 Bridgestone Sports Co., Ltd. Multi-piece solid golf ball
US10765917B2 (en) 2017-04-24 2020-09-08 Bridgestone Sports Co., Ltd. Multi-piece solid golf ball
JP6904038B2 (ja) 2017-04-24 2021-07-14 ブリヂストンスポーツ株式会社 マルチピースソリッドゴルフボール
US20230267987A1 (en) * 2022-02-24 2023-08-24 Changxin Memory Technologies, Inc. Method and apparatus for intensifying current leakage between adjacent memory cells, and method and apparatus for current leakage detection

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1982000917A1 (en) * 1980-09-08 1982-03-18 Proebsting R Tape burn-in circuit
JPS59107493A (ja) * 1982-12-09 1984-06-21 Ricoh Co Ltd テスト回路付きｅｐｒｏｍメモリ装置
JPS62198147A (ja) * 1986-02-26 1987-09-01 Hitachi Vlsi Eng Corp 半導体集積回路装置
JPS63311693A (ja) * 1987-06-12 1988-12-20 Hitachi Ltd 半導体記憶装置
JP2558881B2 (ja) * 1989-06-30 1996-11-27 株式会社東芝 半導体メモリ装置
JP2829134B2 (ja) * 1990-12-27 1998-11-25 株式会社東芝 半導体記憶装置
JPH07123134B2 (ja) * 1990-12-27 1995-12-25 株式会社東芝 半導体装置
JP3143950B2 (ja) * 1991-04-30 2001-03-07 日本電気株式会社 ダイナミックメモリー

Also Published As

Publication number Publication date
DE69419951T2 (de) 1999-12-23
KR940022581A (ko) 1994-10-21
JPH06267293A (ja) 1994-09-22
EP0615253A2 (de) 1994-09-14
EP0615253A3 (de) 1994-10-12
JP2885597B2 (ja) 1999-04-26
EP0615253B1 (de) 1999-08-11
KR970001202B1 (ko) 1997-01-29
US5424990A (en) 1995-06-13

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee