KR930015989U - 메모리 장치의 테스트 모드회로 - Google Patents

메모리 장치의 테스트 모드회로

Info

Publication number
KR930015989U
KR930015989U KR2019910023411U KR910023411U KR930015989U KR 930015989 U KR930015989 U KR 930015989U KR 2019910023411 U KR2019910023411 U KR 2019910023411U KR 910023411 U KR910023411 U KR 910023411U KR 930015989 U KR930015989 U KR 930015989U
Authority
KR
South Korea
Prior art keywords
memory device
test mode
device test
mode circuit
circuit
Prior art date
Application number
KR2019910023411U
Other languages
English (en)
Other versions
KR950000305Y1 (ko
Inventor
김종호
Original Assignee
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성일렉트론 주식회사 filed Critical 금성일렉트론 주식회사
Priority to KR2019910023411U priority Critical patent/KR950000305Y1/ko
Priority to DE4243611A priority patent/DE4243611B4/de
Priority to US07/995,974 priority patent/US5418790A/en
Priority to JP35732092A priority patent/JP3338900B2/ja
Publication of KR930015989U publication Critical patent/KR930015989U/ko
Application granted granted Critical
Publication of KR950000305Y1 publication Critical patent/KR950000305Y1/ko

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
KR2019910023411U 1991-12-23 1991-12-23 메모리 장치의 테스트 모드회로 KR950000305Y1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR2019910023411U KR950000305Y1 (ko) 1991-12-23 1991-12-23 메모리 장치의 테스트 모드회로
DE4243611A DE4243611B4 (de) 1991-12-23 1992-12-22 Testmodusschaltung für eine Speichervorrichtung
US07/995,974 US5418790A (en) 1991-12-23 1992-12-23 Interference grasping test mode circuit for a semiconductor memory device
JP35732092A JP3338900B2 (ja) 1991-12-23 1992-12-24 メモリ装置のテストモード回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019910023411U KR950000305Y1 (ko) 1991-12-23 1991-12-23 메모리 장치의 테스트 모드회로

Publications (2)

Publication Number Publication Date
KR930015989U true KR930015989U (ko) 1993-07-28
KR950000305Y1 KR950000305Y1 (ko) 1995-01-16

Family

ID=19325175

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019910023411U KR950000305Y1 (ko) 1991-12-23 1991-12-23 메모리 장치의 테스트 모드회로

Country Status (4)

Country Link
US (1) US5418790A (ko)
JP (1) JP3338900B2 (ko)
KR (1) KR950000305Y1 (ko)
DE (1) DE4243611B4 (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE502576C2 (sv) * 1993-11-26 1995-11-13 Ellemtel Utvecklings Ab Feltolerant kösystem
JP3563779B2 (ja) * 1994-09-13 2004-09-08 株式会社ルネサステクノロジ 半導体記憶装置
EP0744755A1 (en) * 1995-05-25 1996-11-27 International Business Machines Corporation Test method and device for embedded memories on semiconductor substrates
DE19612441C2 (de) * 1996-03-28 1998-04-09 Siemens Ag Schaltungsanordnung mit einer Testschaltung
US5936976A (en) * 1997-07-25 1999-08-10 Vlsi Technology, Inc. Selecting a test data input bus to supply test data to logical blocks within an integrated circuit
JP3842971B2 (ja) * 1998-02-17 2006-11-08 インフィネオン テクノロジース アクチエンゲゼルシャフト テスト装置およびデジタル半導体回路装置の検査方法
US6292908B1 (en) * 1998-10-19 2001-09-18 International Business Machines Corporation Method and apparatus for monitoring internal bus signals by using a reduced image of the internal bus
KR100772718B1 (ko) * 2000-06-30 2007-11-02 주식회사 하이닉스반도체 반도체메모리 장치의 데이터 압축 테스트 방법
US7246280B2 (en) * 2004-03-23 2007-07-17 Samsung Electronics Co., Ltd. Memory module with parallel testing
KR100587233B1 (ko) * 2004-06-14 2006-06-08 삼성전자주식회사 반도체 메모리소자의 번인테스트 방법
US8091001B2 (en) * 2006-11-30 2012-01-03 Quicklogic Corporation FPGA programming structure for ATPG test coverage
KR101321481B1 (ko) * 2011-11-04 2013-10-28 에스케이하이닉스 주식회사 반도체 메모리 장치 및 이를 위한 테스트 회로

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5157629A (en) * 1985-11-22 1992-10-20 Hitachi, Ltd. Selective application of voltages for testing storage cells in semiconductor memory arrangements
EP0253161B1 (en) * 1986-06-25 1991-10-16 Nec Corporation Testing circuit for random access memory device
JPH02146199A (ja) * 1988-11-28 1990-06-05 Mitsubishi Electric Corp 半導体記憶装置のテスト回路
JP2779538B2 (ja) * 1989-04-13 1998-07-23 三菱電機株式会社 半導体集積回路メモリのためのテスト信号発生器およびテスト方法
JP2780354B2 (ja) * 1989-07-04 1998-07-30 富士通株式会社 半導体メモリ装置
SU1711235A1 (ru) * 1989-07-24 1992-02-07 Московский энергетический институт Устройство дл формировани тестов пам ти
SU1705876A1 (ru) * 1990-03-27 1992-01-15 Московский энергетический институт Устройство дл контрол блоков оперативной пам ти

Also Published As

Publication number Publication date
US5418790A (en) 1995-05-23
KR950000305Y1 (ko) 1995-01-16
JPH065097A (ja) 1994-01-14
DE4243611A1 (en) 1993-06-24
JP3338900B2 (ja) 2002-10-28
DE4243611B4 (de) 2006-09-21

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