DE19680290T1 - Schaltungstestvorrichtung - Google Patents

Schaltungstestvorrichtung

Info

Publication number
DE19680290T1
DE19680290T1 DE19680290T DE19680290T DE19680290T1 DE 19680290 T1 DE19680290 T1 DE 19680290T1 DE 19680290 T DE19680290 T DE 19680290T DE 19680290 T DE19680290 T DE 19680290T DE 19680290 T1 DE19680290 T1 DE 19680290T1
Authority
DE
Germany
Prior art keywords
test device
circuit test
circuit
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19680290T
Other languages
English (en)
Inventor
Kouji Takahashi
Takashi Kusano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Publication of DE19680290T1 publication Critical patent/DE19680290T1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31919—Storing and outputting test patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/31813—Test pattern generators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE19680290T 1995-03-13 1996-03-13 Schaltungstestvorrichtung Withdrawn DE19680290T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7052432A JPH08248096A (ja) 1995-03-13 1995-03-13 回路試験装置
PCT/JP1996/000627 WO1996028744A1 (fr) 1995-03-13 1996-03-13 Verificateur de circuit

Publications (1)

Publication Number Publication Date
DE19680290T1 true DE19680290T1 (de) 1997-05-22

Family

ID=12914603

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19680290T Withdrawn DE19680290T1 (de) 1995-03-13 1996-03-13 Schaltungstestvorrichtung

Country Status (5)

Country Link
US (1) US5930271A (de)
JP (1) JPH08248096A (de)
KR (1) KR100238956B1 (de)
DE (1) DE19680290T1 (de)
WO (1) WO1996028744A1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09288153A (ja) * 1996-04-19 1997-11-04 Advantest Corp 半導体試験装置
TW366450B (en) * 1997-03-21 1999-08-11 Matsushita Electric Ind Co Ltd IC function block, semiconductor circuit, method of checking semiconductor circuits and the design method
JPH11203158A (ja) * 1998-01-13 1999-07-30 Mitsubishi Electric Corp テスト回路付パイプライン回路およびテスト回路付パイプライン回路をテストするための自動テストパターン生成方法
JP2000352575A (ja) * 1999-06-10 2000-12-19 Mitsubishi Electric Corp 組み込み型自己テスト回路およびテスト方法
US6606705B1 (en) * 1999-09-15 2003-08-12 Intel Corporation Method and apparatus for configuring an I/O buffer having an initialized default signaling level to operate at a sampled external circuit signaling level
US6624662B1 (en) 2000-06-30 2003-09-23 Intel Corporation Buffer with compensating drive strength
US6651205B2 (en) * 2001-02-02 2003-11-18 Advantest Corp. Test pattern conversion apparatus and conversion method
US20020118215A1 (en) * 2001-02-23 2002-08-29 Brian Ball Method and system for providing block animation
DE10121309B4 (de) * 2001-05-02 2004-01-29 Infineon Technologies Ag Testschaltung zum Testen einer zu testenden Schaltung
US7003697B2 (en) * 2001-07-02 2006-02-21 Nextest Systems, Corporation Apparatus having pattern scrambler for testing a semiconductor device and method for operating same
US7100098B2 (en) * 2003-06-12 2006-08-29 Agilent Technologies, Inc. Systems and methods for testing performance of an electronic device
JP4063207B2 (ja) * 2003-12-04 2008-03-19 株式会社リコー 画像処理装置検査システムと方法およびプログラム
JP4542852B2 (ja) * 2004-08-20 2010-09-15 株式会社アドバンテスト 試験装置及び試験方法
DE102005056930A1 (de) * 2005-11-29 2007-05-31 Infineon Technologies Ag Halbleiter-Bauelement-Test-Verfahren, Halbleiter-Bauelement-Testgerät, sowie zwischen ein Testgerät und ein zu testendes Halbleiter-Bauelement geschaltete Einrichtung
US7502708B2 (en) * 2006-10-12 2009-03-10 Advantest Corporation Test apparatus, and control method
KR100974669B1 (ko) * 2009-11-26 2010-08-09 주식회사 아이티엔티 룩업 테이블을 내장한 보스트 회로 장치 또는 패턴 생성 장치, 및 이를 이용한 테스트 대상 디바이스에 대한 테스트 데이터 출력 방법
US9360523B2 (en) * 2014-04-18 2016-06-07 Breker Verification Systems Display in a graphical format of test results generated using scenario models
DE102016201141B4 (de) * 2016-01-27 2017-11-16 Wago Verwaltungsgesellschaft Mbh Sicherheitsanordnung

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4775977A (en) * 1985-11-19 1988-10-04 Ando Electric Co., Ltd. Pattern generating apparatus
DE3902835A1 (de) * 1989-01-31 1990-08-02 Siemens Ag Verfahren zur erzeugung von pruefmustern fuer einen baustein
US5072178A (en) * 1989-06-09 1991-12-10 Hitachi, Ltd. Method and apparatus for testing logic circuitry by applying a logical test pattern

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01253665A (ja) * 1988-04-02 1989-10-09 Hitachi Electron Eng Co Ltd 遅延回路内蔵ｌｓｉ用テスタ
JP2641739B2 (ja) * 1988-07-29 1997-08-20 富士通株式会社 試験装置
JPH0280984A (ja) * 1988-09-19 1990-03-22 Hitachi Ltd アドレス演算命令生成方法
JPH03122578A (ja) * 1989-10-04 1991-05-24 Nec Corp 論理集積回路
JPH04168377A (ja) * 1990-10-31 1992-06-16 Nec Corp Ｉｃ試験装置
JP2964644B2 (ja) * 1990-12-10 1999-10-18 安藤電気株式会社 高速パターン発生器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4775977A (en) * 1985-11-19 1988-10-04 Ando Electric Co., Ltd. Pattern generating apparatus
DE3902835A1 (de) * 1989-01-31 1990-08-02 Siemens Ag Verfahren zur erzeugung von pruefmustern fuer einen baustein
US5072178A (en) * 1989-06-09 1991-12-10 Hitachi, Ltd. Method and apparatus for testing logic circuitry by applying a logical test pattern

Also Published As

Publication number Publication date
JPH08248096A (ja) 1996-09-27
WO1996028744A1 (fr) 1996-09-19
KR970703535A (ko) 1997-07-03
US5930271A (en) 1999-07-27
KR100238956B1 (ko) 2000-01-15

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8139 Disposal/non-payment of the annual fee