DE69317964D1 - Dynamischer RAM mit Spannungsstressanlegeschaltung - Google Patents

Dynamischer RAM mit Spannungsstressanlegeschaltung

Info

Publication number
DE69317964D1
DE69317964D1 DE69317964T DE69317964T DE69317964D1 DE 69317964 D1 DE69317964 D1 DE 69317964D1 DE 69317964 T DE69317964 T DE 69317964T DE 69317964 T DE69317964 T DE 69317964T DE 69317964 D1 DE69317964 D1 DE 69317964D1
Authority
DE
Germany
Prior art keywords
dynamic
circuit
mode
screening
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69317964T
Other languages
English (en)
Other versions
DE69317964T2 (de
Inventor
Masaki Ogihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Publication of DE69317964D1 publication Critical patent/DE69317964D1/de
Application granted granted Critical
Publication of DE69317964T2 publication Critical patent/DE69317964T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE69317964T 1992-08-31 1993-08-31 Dynamischer RAM mit Spannungsstressanlegeschaltung Expired - Fee Related DE69317964T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4230692A JP2977385B2 (ja) 1992-08-31 1992-08-31 ダイナミックメモリ装置

Publications (2)

Publication Number Publication Date
DE69317964D1 true DE69317964D1 (de) 1998-05-20
DE69317964T2 DE69317964T2 (de) 1998-09-10

Family

ID=16911820

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69317964T Expired - Fee Related DE69317964T2 (de) 1992-08-31 1993-08-31 Dynamischer RAM mit Spannungsstressanlegeschaltung

Country Status (5)

Country Link
US (1) US5475646A (de)
EP (1) EP0585870B1 (de)
JP (1) JP2977385B2 (de)
KR (1) KR950014097B1 (de)
DE (1) DE69317964T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3059024B2 (ja) * 1993-06-15 2000-07-04 沖電気工業株式会社 半導体記憶回路
JP3759758B2 (ja) * 1994-02-03 2006-03-29 株式会社ルネサステクノロジ 半導体記憶装置
JP3495787B2 (ja) * 1994-06-30 2004-02-09 株式会社ルネサステクノロジ 半導体装置
JP2697634B2 (ja) * 1994-09-30 1998-01-14 日本電気株式会社 同期型半導体記憶装置
KR0140481B1 (ko) * 1994-12-31 1998-07-01 김주용 동기식 메모리장치의 데이타신호 분배회로
JP2818571B2 (ja) * 1996-02-21 1998-10-30 山形日本電気株式会社 半導体記憶装置
KR100206600B1 (ko) * 1996-06-03 1999-07-01 김영환 싱크로노스 디램의 리프레쉬 카운터 테스트 모드방법 및 그 장치
KR100226266B1 (ko) * 1996-06-29 1999-10-15 김영환 반도체 메모리장치의 카스 버퍼회로
KR100225951B1 (ko) * 1996-10-22 1999-10-15 김영환 노이즈 감소형 반도체 메모리 장치
KR100260358B1 (ko) * 1996-12-30 2000-07-01 김영환 반도체 메모리소자의 출력버퍼회로
KR100259336B1 (ko) * 1997-04-15 2000-06-15 김영환 반도체 소자의 오토 리프레쉬 제어회로
DE19735406A1 (de) 1997-08-14 1999-02-18 Siemens Ag Halbleiterbauelement und Verfahren zum Testen und Betreiben eines Halbleiterbauelementes
JPH11345486A (ja) * 1998-06-01 1999-12-14 Mitsubishi Electric Corp セルフ・リフレッシュ制御回路を備えたｄｒａｍおよびシステムｌｓｉ
KR100324821B1 (ko) 1999-06-29 2002-02-28 박종섭 반도체 메모리 소자의 자동 리프레쉬 방법 및 장치
US6728156B2 (en) * 2002-03-11 2004-04-27 International Business Machines Corporation Memory array system
JP2004053257A (ja) * 2002-07-16 2004-02-19 Renesas Technology Corp 半導体故障解析装置
US6781908B1 (en) * 2003-02-19 2004-08-24 Freescale Semiconductor, Inc. Memory having variable refresh control and method therefor
JP2005174432A (ja) * 2003-12-10 2005-06-30 Matsushita Electric Ind Co Ltd 半導体記憶装置
KR100641953B1 (ko) * 2004-06-29 2006-11-02 주식회사 하이닉스반도체 내부신호 측정장치 및 그 방법
US7484140B2 (en) * 2004-07-07 2009-01-27 Freescale Semiconductor, Inc. Memory having variable refresh control and method therefor
JP2007226853A (ja) * 2006-02-21 2007-09-06 Toshiba Corp マルチチップパッケージ
KR100854497B1 (ko) 2006-07-10 2008-08-26 삼성전자주식회사 반도체 메모리 장치 및 이의 동작 방법
KR100873613B1 (ko) * 2006-11-14 2008-12-12 주식회사 하이닉스반도체 반도체 메모리 장치의 전압 생성 회로 및 방법
KR100952438B1 (ko) 2008-02-29 2010-04-14 주식회사 하이닉스반도체 반도체 메모리 장치

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0059188A1 (de) * 1980-09-08 1982-09-08 Mostek Corporation Band-alterungsschaltung
JPS61126690A (ja) * 1984-11-26 1986-06-14 Hitachi Ltd 半導体メモリ
JPS62250593A (ja) * 1986-04-23 1987-10-31 Hitachi Ltd ダイナミツク型ｒａｍ
US5051995A (en) * 1988-03-14 1991-09-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having a test mode setting circuit
JPH081747B2 (ja) * 1989-05-08 1996-01-10 三菱電機株式会社 半導体記憶装置およびその動作方法
JPH07105160B2 (ja) * 1989-05-20 1995-11-13 東芝マイクロエレクトロニクス株式会社 半導体記憶装置
JPH0821607B2 (ja) * 1990-05-11 1996-03-04 株式会社東芝 ダイナミック記憶装置およびそのバーンイン方法

Also Published As

Publication number Publication date
KR950014097B1 (ko) 1995-11-21
KR940004654A (ko) 1994-03-15
EP0585870A3 (de) 1994-11-17
JPH0676569A (ja) 1994-03-18
US5475646A (en) 1995-12-12
JP2977385B2 (ja) 1999-11-15
EP0585870A2 (de) 1994-03-09
DE69317964T2 (de) 1998-09-10
EP0585870B1 (de) 1998-04-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee