DE69013250T2 - Leseanordnung für eine Halbleiterspeicheranordnung. - Google Patents

Leseanordnung für eine Halbleiterspeicheranordnung.

Info

Publication number
DE69013250T2
DE69013250T2 DE69013250T DE69013250T DE69013250T2 DE 69013250 T2 DE69013250 T2 DE 69013250T2 DE 69013250 T DE69013250 T DE 69013250T DE 69013250 T DE69013250 T DE 69013250T DE 69013250 T2 DE69013250 T2 DE 69013250T2
Authority
DE
Germany
Prior art keywords
arrangement
semiconductor memory
reading
memory arrangement
reading arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69013250T
Other languages
English (en)
Other versions
DE69013250D1 (de
Inventor
Satoru Hoshi
Takayuki Kawaguchi
Masami Masuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Publication of DE69013250D1 publication Critical patent/DE69013250D1/de
Application granted granted Critical
Publication of DE69013250T2 publication Critical patent/DE69013250T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
DE69013250T 1989-07-12 1990-07-12 Leseanordnung für eine Halbleiterspeicheranordnung. Expired - Fee Related DE69013250T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1179816A JPH0646513B2 (ja) 1989-07-12 1989-07-12 半導体記憶装置のデータ読出回路

Publications (2)

Publication Number Publication Date
DE69013250D1 DE69013250D1 (de) 1994-11-17
DE69013250T2 true DE69013250T2 (de) 1995-03-16

Family

ID=16072394

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69013250T Expired - Fee Related DE69013250T2 (de) 1989-07-12 1990-07-12 Leseanordnung für eine Halbleiterspeicheranordnung.

Country Status (5)

Country Link
US (1) US5068831A (de)
EP (1) EP0408031B1 (de)
JP (1) JPH0646513B2 (de)
KR (1) KR930008578B1 (de)
DE (1) DE69013250T2 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5345420A (en) * 1986-10-27 1994-09-06 Seiko Epson Corporation Semiconductor memory device
US5237534A (en) * 1989-04-27 1993-08-17 Kabushiki Kaisha Toshiba Data sense circuit for a semiconductor nonvolatile memory device
US5793667A (en) * 1990-09-19 1998-08-11 The United States Of America As Represented By The Secretary Of The Navy Sense amplifier control system for ferroelectric memories
US5305268A (en) * 1990-12-13 1994-04-19 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with column equilibrate on change of data during a write cycle
US5151879A (en) * 1990-12-27 1992-09-29 Motorola, Inc. Sense amplifier with latch
JP3319610B2 (ja) * 1991-11-22 2002-09-03 日本テキサス・インスツルメンツ株式会社 信号伝達回路
JP2680936B2 (ja) * 1991-02-13 1997-11-19 シャープ株式会社 半導体記憶装置
JP2509004B2 (ja) * 1991-03-04 1996-06-19 株式会社東芝 半導体記憶装置
JP2745251B2 (ja) * 1991-06-12 1998-04-28 三菱電機株式会社 半導体メモリ装置
KR940010838B1 (ko) * 1991-10-28 1994-11-17 삼성전자 주식회사 데이타 출력 콘트롤 회로
JPH05159575A (ja) * 1991-12-04 1993-06-25 Oki Electric Ind Co Ltd ダイナミックランダムアクセスメモリ
JPH05166365A (ja) * 1991-12-12 1993-07-02 Toshiba Corp ダイナミック型半導体記憶装置
US5295104A (en) * 1991-12-17 1994-03-15 Sgs-Thomson Microelectronics, Inc. Integrated circuit with precharged internal data bus
EP0547889B1 (de) * 1991-12-17 1999-04-14 STMicroelectronics, Inc. Tristate-Treiberschaltung für interne Datenbusleitungen
JPH05217365A (ja) * 1992-02-03 1993-08-27 Mitsubishi Electric Corp 半導体記憶装置
JPH05217367A (ja) * 1992-02-03 1993-08-27 Mitsubishi Electric Corp 半導体記憶装置
KR950009234B1 (ko) * 1992-02-19 1995-08-18 삼성전자주식회사 반도체 메모리장치의 비트라인 분리클럭 발생장치
JP2667946B2 (ja) * 1992-09-21 1997-10-27 三菱電機株式会社 半導体記憶装置
US5347183A (en) * 1992-10-05 1994-09-13 Cypress Semiconductor Corporation Sense amplifier with limited output voltage swing and cross-coupled tail device feedback
US5381364A (en) * 1993-06-24 1995-01-10 Ramtron International Corporation Ferroelectric-based RAM sensing scheme including bit-line capacitance isolation
US5402379A (en) * 1993-08-31 1995-03-28 Sgs-Thomson Microelectronics, Inc. Precharge device for an integrated circuit internal bus
JPH07326192A (ja) * 1994-05-31 1995-12-12 Toshiba Micro Comput Eng Corp 半導体記憶装置
US5508644A (en) * 1994-09-28 1996-04-16 Motorola, Inc. Sense amplifier for differential voltage detection with low input capacitance
KR0158112B1 (ko) * 1995-04-25 1999-02-01 김광호 다수개의 뱅크들을 가지는 반도체 메모리 장치
JP3202559B2 (ja) * 1995-10-13 2001-08-27 日本電気株式会社 半導体メモリ
JPH10302472A (ja) * 1997-04-24 1998-11-13 Texas Instr Japan Ltd 半導体メモリ装置
US5835433A (en) * 1997-06-09 1998-11-10 Micron Technology, Inc. Floating isolation gate from DRAM sensing
US6426656B1 (en) * 2000-04-19 2002-07-30 Velio Communications, Inc. High speed, low-power inter-chip transmission system
US7134034B1 (en) * 2003-10-15 2006-11-07 Integrated Device Technology, Inc. Data paths with receiver timing fixable to a downstream stage and methods of operation thereof
JP4028840B2 (ja) * 2003-12-17 2007-12-26 シャープ株式会社 半導体読み出し回路
US7888962B1 (en) 2004-07-07 2011-02-15 Cypress Semiconductor Corporation Impedance matching circuit
US8036846B1 (en) 2005-10-20 2011-10-11 Cypress Semiconductor Corporation Variable impedance sense architecture and method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4239994A (en) * 1978-08-07 1980-12-16 Rca Corporation Asymmetrically precharged sense amplifier
JPS62167698A (ja) * 1986-01-20 1987-07-24 Fujitsu Ltd 半導体記億装置
US4825410A (en) * 1987-10-26 1989-04-25 International Business Machines Corporation Sense amplifier control circuit
US4943944A (en) * 1987-11-25 1990-07-24 Kabushiki Kaisha Toshiba Semiconductor memory using dynamic ram cells

Also Published As

Publication number Publication date
US5068831A (en) 1991-11-26
EP0408031A2 (de) 1991-01-16
DE69013250D1 (de) 1994-11-17
KR930008578B1 (ko) 1993-09-09
KR910003669A (ko) 1991-02-28
EP0408031B1 (de) 1994-10-12
JPH0344891A (ja) 1991-02-26
EP0408031A3 (en) 1992-08-05
JPH0646513B2 (ja) 1994-06-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee